| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | usb251xb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
[all …]
|
| H A D | maxim,max33359.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim TCPCI Type-C PD controller
10 - Badhri Jagan Sridharan <badhri@google.com>
12 description: Maxim TCPCI Type-C PD controller
17 - maxim,max33359
27 $ref: ../connector/usb-connector.yaml#
32 - compatible
33 - reg
[all …]
|
| H A D | qcom,pmic-typec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,pmic-typec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC based USB Type-C block
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm PMIC Type-C block
18 - qcom,pm8150b-typec
22 $ref: /schemas/connector/usb-connector.yaml#
26 description: Type-C port and pdphy SPMI register base offsets
[all …]
|
| /openbmc/linux/drivers/usb/core/ |
| H A D | generic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/usb/core/generic.c - generic driver for USB devices (not interfaces)
5 * (C) Copyright 2005 Greg Kroah-Hartman <gregkh@suse.de>
9 * (C) Copyright Johannes Erdfelt 1999-2001
14 * (C) Copyright David Brownell 2000-2004
17 * (C) Copyright Greg Kroah-Hartman 2002-2003
34 return desc->bInterfaceClass == USB_CLASS_COMM in is_rndis()
35 && desc->bInterfaceSubClass == 2 in is_rndis()
36 && desc->bInterfaceProtocol == 0xff; in is_rndis()
41 return desc->bInterfaceClass == USB_CLASS_MISC in is_activesync()
[all …]
|
| /openbmc/bmcweb/redfish-core/include/registries/ |
| H A D | resource_event_message_registry.hpp | 1 // SPDX-License-Identifier: Apache-2.0
2 // SPDX-FileCopyrightText: Copyright OpenBMC Authors
6 * This is an auto-generated header which contains definitions
18 // clang-format off
23 …"Copyright 2014-2023 DMTF in cooperation with the Storage Networking Industry Association (SNIA). …
178 "Indicates that the power state of a resource has changed to powered off.",
179 "The resource `%1` has powered off.",
190 "Indicates that the power state of a resource has changed to powered on.",
191 "The resource `%1` has powered on.",
236 "Indicates that a self-test has completed.",
[all …]
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/Decorator/ |
| H A D | PowerState.interface.yaml | 4 - name: PowerState
5 type: enum[self.State]
11 - name: State
15 - name: "On"
17 The state of the object is powered on.
18 - name: "Off"
20 The state of the object is powered off.
21 - name: PoweringOn
24 - name: PoweringOff
27 - name: Unknown
|
| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
[all …]
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/ |
| H A D | Chassis.interface.yaml | 4 - name: RequestedPowerTransition
5 type: enum[self.Transition]
11 - xyz.openbmc_project.State.Chassis.Error.BMCNotReady
12 - xyz.openbmc_project.Common.Error.Unavailable
14 - name: CurrentPowerState
15 type: enum[self.PowerState]
17 A read-only property describing the current chassis power state. A
21 - name: CurrentPowerStatus
22 type: enum[self.PowerStatus]
24 A read-only property describing the current chassis power status. This
[all …]
|
| /openbmc/linux/drivers/net/wireless/st/cw1200/ |
| H A D | cw1200_sdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mac80211 SDIO driver for ST-Ericsson CW1200 device
5 * Copyright (c) 2010, ST-Ericsson
22 #include <linux/platform_data/net-cw1200.h>
26 MODULE_DESCRIPTION("mac80211 ST-Ericsson CW1200 SDIO driver");
60 static int cw1200_sdio_memcpy_fromio(struct hwbus_priv *self, in cw1200_sdio_memcpy_fromio() argument
64 return sdio_memcpy_fromio(self->func, dst, addr, count); in cw1200_sdio_memcpy_fromio()
67 static int cw1200_sdio_memcpy_toio(struct hwbus_priv *self, in cw1200_sdio_memcpy_toio() argument
71 return sdio_memcpy_toio(self->func, addr, (void *)src, count); in cw1200_sdio_memcpy_toio()
74 static void cw1200_sdio_lock(struct hwbus_priv *self) in cw1200_sdio_lock() argument
[all …]
|
| H A D | cw1200_spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mac80211 SPI driver for ST-Ericsson CW1200 device
9 * Copyright (c) 2010, ST-Ericsson
25 #include <linux/platform_data/net-cw1200.h>
29 MODULE_DESCRIPTION("mac80211 ST-Ericsson CW1200 SPI driver");
52 Hardware expects 32-bit data to be written as 16-bit BE words:
57 static int cw1200_spi_memcpy_fromio(struct hwbus_priv *self, in cw1200_spi_memcpy_fromio() argument
89 if (self->func->bits_per_word == 8) in cw1200_spi_memcpy_fromio()
96 ret = spi_sync(self->func, &m); in cw1200_spi_memcpy_fromio()
112 if (self->func->bits_per_word == 8) in cw1200_spi_memcpy_fromio()
[all …]
|
| /openbmc/u-boot/include/ |
| H A D | usbroothubdes.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * Based on ohci-hcd.c
46 * Bit 7: Bus-powered
47 * 6: Self-powered,
48 * 5 Remote-wakwup,
75 0x29, /* __u8 bDescriptorType; Hub-descriptor */
88 0x03, /* __u8 bDescriptorType; String-descriptor */
95 0x03, /* __u8 bDescriptorType; String-descriptor */
98 '-', /* __u8 Unicode */
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,coresight-cpu-debug.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
18 external debug module is mainly used for two modes: self-hosted debug and
21 module provides sample-based profiling extension, which can be used to sample
[all …]
|
| /openbmc/u-boot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 2 # Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
9 # SPDX-License-Identifier: GPL-2.0+
11 # Refer doc/README.kwbimage for more details about how-to configure
23 # Configure RGMII-0 interface pad voltage to 1.8V
28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
29 # bit23-14: zero
30 # bit24: 1= enable exit self refresh mode on DDR access
32 # bit29-26: zero
33 # bit31-30: 01
37 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/linux/drivers/crypto/intel/qat/qat_4xxx/ |
| H A D | adf_4xxx_hw_data.c | 1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2020 - 2021 Intel Corporation */
121 static u32 get_accel_mask(struct adf_hw_device_data *self) in get_accel_mask() argument
126 static u32 get_ae_mask(struct adf_hw_device_data *self) in get_ae_mask() argument
128 u32 me_disable = self->fuses; in get_ae_mask()
133 static u32 get_num_accels(struct adf_hw_device_data *self) in get_num_accels() argument
138 static u32 get_num_aes(struct adf_hw_device_data *self) in get_num_aes() argument
140 if (!self || !self->ae_mask) in get_num_aes()
143 return hweight32(self->ae_mask); in get_num_aes()
146 static u32 get_misc_bar_id(struct adf_hw_device_data *self) in get_misc_bar_id() argument
[all …]
|
| /openbmc/u-boot/board/LaCie/netspace_v2/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
26 # bit24: 1= enable exit self refresh mode on DDR access
28 # bit29-26: zero
29 # bit31-30: 01
33 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| H A D | kwbimage-is2.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
26 # bit24: 1= enable exit self refresh mode on DDR access
28 # bit29-26: zero
29 # bit31-30: 01
33 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| H A D | kwbimage-ns2l.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
26 # bit24: 1= enable exit self refresh mode on DDR access
28 # bit29-26: zero
29 # bit31-30: 01
33 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/u-boot/board/cloudengines/pogo_e02/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit23-14: zero
29 # bit24: 1= enable exit self refresh mode on DDR access
31 # bit29-26: zero
32 # bit31-30: 01
36 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/u-boot/board/iomega/iconnect/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
3 # (C) Copyright 2009-2012
6 # Refer doc/README.kwbimage for more details about how-to configure
18 # Configure RGMII-0 interface pad voltage to 1.8V
23 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
24 # bit23-14: 0x0,
25 # bit24: 0x1, enable exit self refresh mode on DDR access
27 # bit29-26: 0x0,
28 # bit31-30: 0x1,
32 # bit5: 0x0, clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/u-boot/board/LaCie/net2big_v2/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
26 # bit24: 1= enable exit self refresh mode on DDR access
28 # bit29-26: zero
29 # bit31-30: 01
33 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/u-boot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
4 # Jason Cooper <u-boot@lakedaemon.net>
8 # Written-by: Siddarth Gore <gores@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0/1 interface pad voltage to 1.8V
27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit23-14: zero
29 # bit24: 1= enable exit self refresh mode on DDR access
31 # bit29-26: zero
32 # bit31-30: 01
[all …]
|
| /openbmc/u-boot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
4 # Jason Cooper <u-boot@lakedaemon.net>
8 # Written-by: Siddarth Gore <gores@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0/1 interface pad voltage to 1.8V
24 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
25 # bit23-14: zero
26 # bit24: 1= enable exit self refresh mode on DDR access
28 # bit29-26: zero
29 # bit31-30: 01
[all …]
|
| /openbmc/u-boot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 # Refer to doc/README.kwbimage for more details about how-to
18 # Configure RGMII-0 interface pad voltage to 1.8V
23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
24 # bit23-14: zero
25 # bit24: 1= enable exit self refresh mode on DDR access
27 # bit29-26: zero
28 # bit31-30: 01
32 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/u-boot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Written-by: Siddarth Gore <gores@marvell.com>
6 # Refer doc/README.kwbimage for more details about how-to configure
18 # Configure RGMII-0/1 interface pad voltage to 1.8V
23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
24 # bit23-14: zero
25 # bit24: 1= enable exit self refresh mode on DDR access
27 # bit29-26: zero
28 # bit31-30: 01
32 # bit 5: 0=clk is driven during self refresh, we don't care for APX
[all …]
|
| /openbmc/u-boot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
21 # Configure RGMII-0 interface pad voltage to 1.8V
26 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
27 # bit23-14: zero
28 # bit24: 1= enable exit self refresh mode on DDR access
30 # bit29-26: zero
31 # bit31-30: 01
35 # bit 5: 0=clk is driven during self refresh, we don't care for APX
37 # bit14: 0=input buffer always powered up
[all …]
|