cloudengines/pogo_e02/kwbimage.cfg

1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
28 # bit23-14: zero
29 # bit24: 1= enable exit self refresh mode on DDR access
31 # bit29-26: zero
32 # bit31-30: 01
36 # bit 5:    0=clk is driven during self refresh, we don't care for APX
38 # bit14:    0=input buffer always powered up
40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
41 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
42 # bit30-28: 3 required
46 # bit3-0:   TRAS lsbs
47 # bit7-4:   TRCD
48 # bit11- 8: TRP
49 # bit15-12: TWR
50 # bit19-16: TWTR
52 # bit23-21: 0x0
53 # bit27-24: TRRD
54 # bit31-28: TRTP
57 # bit6-0:   TRFC
58 # bit8-7:   TR2R
59 # bit10-9:  TR2W
60 # bit12-11: TW2W
61 # bit31-13: zero required
64 # bit1-0:   00, Cs0width=x8
65 # bit3-2:   11, Cs0size=1Gb
66 # bit5-4:   00, Cs1width=x8
67 # bit7-6:   11, Cs1size=1Gb
68 # bit9-8:   00, Cs2width=nonexistent
69 # bit11-10: 00, Cs2size =nonexistent
70 # bit13-12: 00, Cs3width=nonexistent
71 # bit15-14: 00, Cs3size =nonexistent
76 # bit31-20: 0 required
80 # bit31-1: 0 required
83 # bit3-0:   0x0, DDR cmd
84 # bit31-4:  0 required
87 # bit2-0:   2, BurstLen=2 required
89 # bit6-4:   4, CL=5
92 # bit11-9:  6, auto-precharge write recovery ????????????
94 # bit31-13: 0 required
100 # bit5-3:  000, required
102 # bit9-7:  000, required
106 # bit31-13: 0 required
109 # bit2-0:  111, required
111 # bit6-4:  111, required
117 # bit15-12: 1111 required
118 # bit31-16: 0    required
127 # bit3-2:  00, CS0 hit selected
128 # bit23-4: ones, required
129 # bit31-24: 0x0F, Size (i.e. 256MB)
138 # bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
139 # bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
140 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
141 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
144 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
145 # bit3-2:  01, ODT1 active NEVER!
146 # bit31-4: zero, required