iomega/iconnect/kwbimage.cfg

1 # SPDX-License-Identifier: GPL-2.0+
3 # (C) Copyright 2009-2012
6 # Refer doc/README.kwbimage for more details about how-to configure
18 # Configure RGMII-0 interface pad voltage to 1.8V
23 # bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
24 # bit23-14: 0x0,
25 # bit24:    0x1,   enable exit self refresh mode on DDR access
27 # bit29-26: 0x0,
28 # bit31-30: 0x1,
32 # bit5:     0x0, clk is driven during self refresh, we don't care for APX
34 # bit14:    0x0, input buffer always powered up
36 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
38 # bit30-28: 0x3, required
42 # bit3-0:   TRAS lsbs
43 # bit7-4:   TRCD
44 # bit11-8:  TRP
45 # bit15-12: TWR
46 # bit19-16: TWTR
48 # bit23-21: 0x0
49 # bit27-24: TRRD
50 # bit31-28: TRTP
53 # bit6-0:   TRFC
54 # bit8-7:   TR2R
55 # bit10-9:  TR2W
56 # bit12-11: TW2W
57 # bit31-13: 0x0, required
60 # bit1-0:   00,  Cs0width (x8)
61 # bit3-2:   11,  Cs0size (1Gb)
62 # bit5-4:   00,  Cs1width (x8)
63 # bit7-6:   11,  Cs1size (1Gb)
64 # bit9-8:   00,  Cs2width (nonexistent)
65 # bit11-10: 00,  Cs2size (nonexistent)
66 # bit13-12: 00,  Cs3width (nonexistent)
67 # bit15-14: 00,  Cs3size (nonexistent)
72 # bit31-20: 0x0, required
76 # bit31-1: 0x0, required
79 # bit3-0:   0x0, DDR cmd
80 # bit31-4:  0x0, required
83 # bit2-0:   0x2, BurstLen=2 required
85 # bit6-4:   0x4, CL=5
88 # bit11-9:  0x6, auto-precharge write recovery
90 # bit31-13: 0x0, required
96 # bit5-3:   0x0, required
98 # bit9-7:   0x0, required
102 # bit31-13: 0x0, required
105 # bit2-0:   0x7, required
107 # bit6-4:   0x7, required
113 # bit15-12: 0xf, required
114 # bit31-16: 0x0, required
123 # bit3-2:   0x0,     CS0 hit selected
124 # bit23-4:  0xfffff, required
125 # bit31-24: 0x0f,    Size (i.e. 256MB)
134 # bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
135 # bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
136 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
137 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
140 # bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
141 # bit3-2:  0x1, ODT1 active NEVER!
142 # bit31-4: 0x0, required