Marvell/sheevaplug/kwbimage.cfg

1 # SPDX-License-Identifier: GPL-2.0+
5 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 # Refer to doc/README.kwbimage for more details about how-to
18 # Configure RGMII-0 interface pad voltage to 1.8V
23 # bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
24 # bit23-14: zero
25 # bit24: 1= enable exit self refresh mode on DDR access
27 # bit29-26: zero
28 # bit31-30: 01
32 # bit 5:    0=clk is driven during self refresh, we don't care for APX
34 # bit14:    0=input buffer always powered up
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
38 # bit30-28: 3 required
42 # bit3-0:   TRAS lsbs
43 # bit7-4:   TRCD
44 # bit11- 8: TRP
45 # bit15-12: TWR
46 # bit19-16: TWTR
48 # bit23-21: 0x0
49 # bit27-24: TRRD
50 # bit31-28: TRTP
53 # bit6-0:   TRFC
54 # bit8-7:   TR2R
55 # bit10-9:  TR2W
56 # bit12-11: TW2W
57 # bit31-13: zero required
60 # bit1-0:   00, Cs0width=x8
61 # bit3-2:   11, Cs0size=1Gb
62 # bit5-4:   00, Cs1width=x8
63 # bit7-6:   11, Cs1size=1Gb
64 # bit9-8:   00, Cs2width=nonexistent
65 # bit11-10: 00, Cs2size =nonexistent
66 # bit13-12: 00, Cs3width=nonexistent
67 # bit15-14: 00, Cs3size =nonexistent
72 # bit31-20: 0 required
76 # bit31-1: 0 required
79 # bit3-0:   0x0, DDR cmd
80 # bit31-4:  0 required
83 # bit2-0:   2, BurstLen=2 required
85 # bit6-4:   4, CL=5
88 # bit11-9:  6, auto-precharge write recovery ????????????
90 # bit31-13: 0 required
96 # bit5-3:  000, required
98 # bit9-7:  000, required
102 # bit31-13: 0 required
105 # bit2-0:  111, required
107 # bit6-4:  111, required
113 # bit15-12: 1111 required
114 # bit31-16: 0    required
123 # bit3-2:  00, CS0 hit selected
124 # bit23-4: ones, required
125 # bit31-24: 0x0F, Size (i.e. 256MB)
135 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
136 # bit3-2:  01, ODT1 active NEVER!
137 # bit31-4: zero, required