Seagate/nas220/kwbimage.cfg

2 # Copyright (C) 2014  Evgeni Dobrev <evgeni@studio-punkt.com>
9 # SPDX-License-Identifier:      GPL-2.0+
11 # Refer doc/README.kwbimage for more details about how-to configure
23 # Configure RGMII-0 interface pad voltage to 1.8V
28 # bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
29 # bit23-14: zero
30 # bit24: 1= enable exit self refresh mode on DDR access
32 # bit29-26: zero
33 # bit31-30: 01
37 # bit 5:    0=clk is driven during self refresh, we don't care for APX
39 # bit14:    0=input buffer always powered up
41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
42 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
43 # bit30-28: 3 required
47 # bit7-4:   TRCD
48 # bit11- 8: TRP
49 # bit15-12: TWR
50 # bit19-16: TWTR
52 # bit23-21: 0x0
53 # bit27-24: TRRD
54 # bit31-28: TRTP
57 # bit6-0:   TRFC
58 # bit8-7:   TR2R
59 # bit10-9:  TR2W
60 # bit12-11: TW2W
61 # bit31-13: zero required
65 # bit1-0:   00, Cs0width=x8
66 # bit3-2:   11, Cs0size=1Gb
67 # bit5-4:   00, Cs1width=nonexistent
68 # bit7-6:   00, Cs1size =nonexistent
69 # bit9-8:   00, Cs2width=nonexistent
70 # bit11-10: 00, Cs2size =nonexistent
71 # bit13-12: 00, Cs3width=nonexistent
72 # bit15-14: 00, Cs3size =nonexistent
77 # bit31-20: 0 required
81 # bit31-1: 0 required
84 # bit3-0:   0x0, DDR cmd
85 # bit31-4:  0 required
88 # bit2-0:   2, BurstLen=2 required
90 # bit6-4:   4, CL=5
93 # bit11-9:  6, auto-precharge write recovery ????????????
95 # bit31-13: 0 required
102 # bit5-3:  000, required
104 # bit9-7:  000, required
108 # bit31-13: 0 required
111 # bit2-0:  111, required
113 # bit6-4:  111, required
119 # bit15-12: 1111 required
120 # bit31-16: 0    required
125 # bit3-2:  00, CS0 hit selected
126 # bit23-4: ones, required
127 # bit31-24: 0x07, Size (i.e. 128MB)
138 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
139 # bit3-2:  01, ODT1 active NEVER!
140 # bit31-4: zero, required