1*9637c4b2SEvgeni Dobrev# 2*9637c4b2SEvgeni Dobrev# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> 3*9637c4b2SEvgeni Dobrev# 4*9637c4b2SEvgeni Dobrev# Based on sheevaplug/kwbimage.cfg originally written by 5*9637c4b2SEvgeni Dobrev# Prafulla Wadaskar <prafulla@marvell.com> 6*9637c4b2SEvgeni Dobrev# (C) Copyright 2009 7*9637c4b2SEvgeni Dobrev# Marvell Semiconductor <www.marvell.com> 8*9637c4b2SEvgeni Dobrev# 9*9637c4b2SEvgeni Dobrev# SPDX-License-Identifier: GPL-2.0+ 10*9637c4b2SEvgeni Dobrev# 11*9637c4b2SEvgeni Dobrev# Refer doc/README.kwbimage for more details about how-to configure 12*9637c4b2SEvgeni Dobrev# and create kirkwood boot image 13*9637c4b2SEvgeni Dobrev# 14*9637c4b2SEvgeni Dobrev 15*9637c4b2SEvgeni Dobrev# Boot Media configurations 16*9637c4b2SEvgeni DobrevBOOT_FROM nand 17*9637c4b2SEvgeni DobrevNAND_ECC_MODE default 18*9637c4b2SEvgeni DobrevNAND_PAGE_SIZE 0x0200 19*9637c4b2SEvgeni Dobrev 20*9637c4b2SEvgeni Dobrev# SOC registers configuration using bootrom header extension 21*9637c4b2SEvgeni Dobrev# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 22*9637c4b2SEvgeni Dobrev 23*9637c4b2SEvgeni Dobrev# Configure RGMII-0 interface pad voltage to 1.8V 24*9637c4b2SEvgeni DobrevDATA 0xFFD100e0 0x1b1b1b9b 25*9637c4b2SEvgeni Dobrev 26*9637c4b2SEvgeni Dobrev#Dram initalization for SINGLE x16 CL=5 @ 400MHz 27*9637c4b2SEvgeni DobrevDATA 0xFFD01400 0x43000618 # DDR Configuration register 28*9637c4b2SEvgeni Dobrev# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 29*9637c4b2SEvgeni Dobrev# bit23-14: zero 30*9637c4b2SEvgeni Dobrev# bit24: 1= enable exit self refresh mode on DDR access 31*9637c4b2SEvgeni Dobrev# bit25: 1 required 32*9637c4b2SEvgeni Dobrev# bit29-26: zero 33*9637c4b2SEvgeni Dobrev# bit31-30: 01 34*9637c4b2SEvgeni Dobrev 35*9637c4b2SEvgeni DobrevDATA 0xFFD01404 0x35143000 # DDR Controller Control Low 36*9637c4b2SEvgeni Dobrev# bit 4: 0=addr/cmd in smame cycle 37*9637c4b2SEvgeni Dobrev# bit 5: 0=clk is driven during self refresh, we don't care for APX 38*9637c4b2SEvgeni Dobrev# bit 6: 0=use recommended falling edge of clk for addr/cmd 39*9637c4b2SEvgeni Dobrev# bit14: 0=input buffer always powered up 40*9637c4b2SEvgeni Dobrev# bit18: 1=cpu lock transaction enabled 41*9637c4b2SEvgeni Dobrev# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 42*9637c4b2SEvgeni Dobrev# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 43*9637c4b2SEvgeni Dobrev# bit30-28: 3 required 44*9637c4b2SEvgeni Dobrev# bit31: 0=no additional STARTBURST delay 45*9637c4b2SEvgeni Dobrev 46*9637c4b2SEvgeni DobrevDATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1) 47*9637c4b2SEvgeni Dobrev# bit7-4: TRCD 48*9637c4b2SEvgeni Dobrev# bit11- 8: TRP 49*9637c4b2SEvgeni Dobrev# bit15-12: TWR 50*9637c4b2SEvgeni Dobrev# bit19-16: TWTR 51*9637c4b2SEvgeni Dobrev# bit20: TRAS msb 52*9637c4b2SEvgeni Dobrev# bit23-21: 0x0 53*9637c4b2SEvgeni Dobrev# bit27-24: TRRD 54*9637c4b2SEvgeni Dobrev# bit31-28: TRTP 55*9637c4b2SEvgeni Dobrev 56*9637c4b2SEvgeni DobrevDATA 0xFFD0140C 0x00000819 # DDR Timing (High) 57*9637c4b2SEvgeni Dobrev# bit6-0: TRFC 58*9637c4b2SEvgeni Dobrev# bit8-7: TR2R 59*9637c4b2SEvgeni Dobrev# bit10-9: TR2W 60*9637c4b2SEvgeni Dobrev# bit12-11: TW2W 61*9637c4b2SEvgeni Dobrev# bit31-13: zero required 62*9637c4b2SEvgeni Dobrev 63*9637c4b2SEvgeni Dobrev 64*9637c4b2SEvgeni DobrevDATA 0xFFD01410 0x0000000d # DDR Address Control 65*9637c4b2SEvgeni Dobrev# bit1-0: 00, Cs0width=x8 66*9637c4b2SEvgeni Dobrev# bit3-2: 11, Cs0size=1Gb 67*9637c4b2SEvgeni Dobrev# bit5-4: 00, Cs1width=nonexistent 68*9637c4b2SEvgeni Dobrev# bit7-6: 00, Cs1size =nonexistent 69*9637c4b2SEvgeni Dobrev# bit9-8: 00, Cs2width=nonexistent 70*9637c4b2SEvgeni Dobrev# bit11-10: 00, Cs2size =nonexistent 71*9637c4b2SEvgeni Dobrev# bit13-12: 00, Cs3width=nonexistent 72*9637c4b2SEvgeni Dobrev# bit15-14: 00, Cs3size =nonexistent 73*9637c4b2SEvgeni Dobrev# bit16: 0, Cs0AddrSel 74*9637c4b2SEvgeni Dobrev# bit17: 0, Cs1AddrSel 75*9637c4b2SEvgeni Dobrev# bit18: 0, Cs2AddrSel 76*9637c4b2SEvgeni Dobrev# bit19: 0, Cs3AddrSel 77*9637c4b2SEvgeni Dobrev# bit31-20: 0 required 78*9637c4b2SEvgeni Dobrev 79*9637c4b2SEvgeni DobrevDATA 0xFFD01414 0x00000000 # DDR Open Pages Control 80*9637c4b2SEvgeni Dobrev# bit0: 0, OpenPage enabled 81*9637c4b2SEvgeni Dobrev# bit31-1: 0 required 82*9637c4b2SEvgeni Dobrev 83*9637c4b2SEvgeni DobrevDATA 0xFFD01418 0x00000000 # DDR Operation 84*9637c4b2SEvgeni Dobrev# bit3-0: 0x0, DDR cmd 85*9637c4b2SEvgeni Dobrev# bit31-4: 0 required 86*9637c4b2SEvgeni Dobrev 87*9637c4b2SEvgeni DobrevDATA 0xFFD0141C 0x00000632 # DDR Mode 88*9637c4b2SEvgeni Dobrev# bit2-0: 2, BurstLen=2 required 89*9637c4b2SEvgeni Dobrev# bit3: 0, BurstType=0 required 90*9637c4b2SEvgeni Dobrev# bit6-4: 4, CL=5 91*9637c4b2SEvgeni Dobrev# bit7: 0, TestMode=0 normal 92*9637c4b2SEvgeni Dobrev# bit8: 0, DLL reset=0 normal 93*9637c4b2SEvgeni Dobrev# bit11-9: 6, auto-precharge write recovery ???????????? 94*9637c4b2SEvgeni Dobrev# bit12: 0, PD must be zero 95*9637c4b2SEvgeni Dobrev# bit31-13: 0 required 96*9637c4b2SEvgeni Dobrev 97*9637c4b2SEvgeni Dobrev 98*9637c4b2SEvgeni DobrevDATA 0xFFD01420 0x00000040 # DDR Extended Mode 99*9637c4b2SEvgeni Dobrev# bit0: 0, DDR DLL enabled 100*9637c4b2SEvgeni Dobrev# bit1: 0, DDR drive strenght normal 101*9637c4b2SEvgeni Dobrev# bit2: 0, DDR ODT control lsd (disabled) 102*9637c4b2SEvgeni Dobrev# bit5-3: 000, required 103*9637c4b2SEvgeni Dobrev# bit6: 1, DDR ODT control msb, (disabled) 104*9637c4b2SEvgeni Dobrev# bit9-7: 000, required 105*9637c4b2SEvgeni Dobrev# bit10: 0, differential DQS enabled 106*9637c4b2SEvgeni Dobrev# bit11: 0, required 107*9637c4b2SEvgeni Dobrev# bit12: 0, DDR output buffer enabled 108*9637c4b2SEvgeni Dobrev# bit31-13: 0 required 109*9637c4b2SEvgeni Dobrev 110*9637c4b2SEvgeni DobrevDATA 0xFFD01424 0x0000F07F # DDR Controller Control High 111*9637c4b2SEvgeni Dobrev# bit2-0: 111, required 112*9637c4b2SEvgeni Dobrev# bit3 : 1 , MBUS Burst Chop disabled 113*9637c4b2SEvgeni Dobrev# bit6-4: 111, required 114*9637c4b2SEvgeni Dobrev# bit7 : 0 115*9637c4b2SEvgeni Dobrev# bit8 : 0 116*9637c4b2SEvgeni Dobrev# bit9 : 0 , no half clock cycle addition to dataout 117*9637c4b2SEvgeni Dobrev# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 118*9637c4b2SEvgeni Dobrev# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 119*9637c4b2SEvgeni Dobrev# bit15-12: 1111 required 120*9637c4b2SEvgeni Dobrev# bit31-16: 0 required 121*9637c4b2SEvgeni Dobrev 122*9637c4b2SEvgeni DobrevDATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size 123*9637c4b2SEvgeni Dobrev# bit0: 1, Window enabled 124*9637c4b2SEvgeni Dobrev# bit1: 0, Write Protect disabled 125*9637c4b2SEvgeni Dobrev# bit3-2: 00, CS0 hit selected 126*9637c4b2SEvgeni Dobrev# bit23-4: ones, required 127*9637c4b2SEvgeni Dobrev# bit31-24: 0x07, Size (i.e. 128MB) 128*9637c4b2SEvgeni Dobrev 129*9637c4b2SEvgeni DobrevDATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 130*9637c4b2SEvgeni Dobrev 131*9637c4b2SEvgeni DobrevDATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled 132*9637c4b2SEvgeni Dobrev 133*9637c4b2SEvgeni DobrevDATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 134*9637c4b2SEvgeni DobrevDATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 135*9637c4b2SEvgeni Dobrev 136*9637c4b2SEvgeni DobrevDATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 137*9637c4b2SEvgeni DobrevDATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 138*9637c4b2SEvgeni Dobrev# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 139*9637c4b2SEvgeni Dobrev# bit3-2: 01, ODT1 active NEVER! 140*9637c4b2SEvgeni Dobrev# bit31-4: zero, required 141*9637c4b2SEvgeni Dobrev 142*9637c4b2SEvgeni DobrevDATA 0xFFD0149C 0x0000E803 # CPU ODT Control 143*9637c4b2SEvgeni Dobrev 144*9637c4b2SEvgeni DobrevDATA 0xFFD01480 0x00000001 # DDR Initialization Control 145*9637c4b2SEvgeni Dobrev#bit0=1, enable DDR init upon this register write 146*9637c4b2SEvgeni Dobrev 147*9637c4b2SEvgeni DobrevDATA 0xffd01620 0x00465000 148*9637c4b2SEvgeni Dobrev 149*9637c4b2SEvgeni Dobrev# End of Header extension 150*9637c4b2SEvgeni DobrevDATA 0x0 0x0 151*9637c4b2SEvgeni Dobrev 152