| /openbmc/u-boot/drivers/gpio/ |
| H A D | at91_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0+
52 writel(mask, &at91_port->puer); in at91_set_port_pullup()
54 writel(mask, &at91_port->pudr); in at91_set_port_pullup()
55 writel(mask, &at91_port->per); in at91_set_port_pullup()
58 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_pullup() argument
62 if (at91_port && (pin < GPIO_PER_BANK)) in at91_set_pio_pullup()
63 at91_set_port_pullup(at91_port, pin, use_pullup); in at91_set_pio_pullup()
69 * mux the pin to the "GPIO" peripheral role.
71 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) in at91_set_pio_periph() argument
76 if (at91_port && (pin < GPIO_PER_BANK)) { in at91_set_pio_periph()
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| /openbmc/u-boot/drivers/pinctrl/ |
| H A D | pinctrl-at91.c | 1 // SPDX-License-Identifier: GPL-2.0+
67 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
68 * on new IP with support for periph C and D the way to mux in
72 * @mux_A_periph: assign the corresponding pin to the peripheral A function.
73 * @mux_B_periph: assign the corresponding pin to the peripheral B function.
74 * @mux_C_periph: assign the corresponding pin to the peripheral C function.
75 * @mux_D_periph: assign the corresponding pin to the peripheral D function.
91 void (*set_drivestrength)(struct at91_port *pio, u32 pin,
95 static u32 two_bit_pin_value_shift_amount(u32 pin) in two_bit_pin_value_shift_amount() argument
97 /* return the shift value for a pin for "two bit" per pin registers, in two_bit_pin_value_shift_amount()
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinmux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin muxing portions of the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 #include <linux/radix-tree.h>
38 const struct pinmux_ops *ops = pctldev->desc->pmxops; in pinmux_check_ops()
44 !ops->get_functions_count || in pinmux_check_ops()
45 !ops->get_function_name || in pinmux_check_ops()
46 !ops->get_function_groups || in pinmux_check_ops()
47 !ops->set_mux) { in pinmux_check_ops()
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| H A D | pinctrl-lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinctrl-lantiq.c
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
17 #include "pinctrl-lantiq.h"
22 return info->num_grps; in ltq_get_group_count()
29 if (selector >= info->num_grps) in ltq_get_group_name()
31 return info->grps[selector].name; in ltq_get_group_name()
40 if (selector >= info->num_grps) in ltq_get_group_pins()
41 return -EINVAL; in ltq_get_group_pins()
42 *pins = info->grps[selector].pins; in ltq_get_group_pins()
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| H A D | pinctrl-at91.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include "pinctrl-at91.h"
46 * @ops: at91 pinctrl mux ops
114 * struct at91_pmx_func - describes AT91 pinmux functions
116 * @groups: corresponding pin groups
134 * struct at91_pmx_pin - describes an At91 pin mux
135 * @bank: the bank of the pin
136 * @pin: the pin number in the @bank
137 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
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| H A D | pinctrl-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
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| H A D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
19 - skew-delay is supported on the Ethernet pins
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| H A D | lantiq,pinctrl-falcon.txt | 4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
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| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
15 used for a specific device or function. This node represents both mux and config
16 of the pins in that group. The 'mux' selects the function mode(also named mux
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
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| H A D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
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| H A D | qcom,ipq8064-pinctrl.txt | 4 - compatible: "qcom,ipq8064-pinctrl"
5 - reg: Should be the base address and length of the TLMM block.
6 - interrupts: Should be the parent IRQ of the TLMM block.
7 - interrupt-controller: Marks the device node as an interrupt controller.
8 - #interrupt-cells: Should be two.
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells : Should be two.
11 The first cell is the gpio pin number and the
13 - gpio-ranges: see ../gpio/gpio.txt
17 - gpio-reserved-ranges: see ../gpio/gpio.txt
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| H A D | qcom,ipq4019-pinctrl.txt | 7 - compatible: "qcom,ipq4019-pinctrl"
8 - reg: Should be the base address and length of the TLMM block.
9 - interrupts: Should be the parent IRQ of the TLMM block.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two.
14 The first cell is the gpio pin number and the
16 - gpio-ranges: see ../gpio/gpio.txt
20 - gpio-reserved-ranges: see ../gpio/gpio.txt
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| H A D | pinctrl-vt8500.txt | 1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
3 These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 bit 0 - active low
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| /openbmc/linux/drivers/pinctrl/bcm/ |
| H A D | pinctrl-ns2-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * corresponding mfio pin group is selected as gpio.
16 #include <linux/pinctrl/pinconf-generic.h>
22 #include "../pinctrl-utils.h"
45 * @offset: register offset for mux configuration of a group
46 * @shift: bit shift for mux configuration of a group
63 * @is_configured: flag to indicate whether a mux setting has already
67 struct ns2_mux mux; member
77 * @mux: Northstar2 group based IOMUX configuration
83 const struct ns2_mux mux; member
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| H A D | pinctrl-nsp-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
10 * gpio_a (8 - 11)
11 * +----------
13 * gpio_a (8-11) | gpio_b (0 - 3)
14 * ------------------------+-------+----------
16 * | pwm (0 - 3)
17 * +----------
27 #include <linux/pinctrl/pinconf-generic.h>
33 #include "../pinctrl-utils.h"
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| /openbmc/u-boot/drivers/pinctrl/rockchip/ |
| H A D | pinctrl-rockchip-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) in rockchip_verify_config() argument
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config()
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
26 return -EINVAL; in rockchip_verify_config()
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { in rockchip_verify_config()
30 debug("pin conf pin %d >= %d\n", pin, in rockchip_verify_config()
32 return -EINVAL; in rockchip_verify_config()
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| /openbmc/u-boot/board/sunxi/ |
| H A D | gmac.c | 11 int pin; local
17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
27 setbits_le32(&ccm->gmac_clk_cfg,
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
35 /* Configure pin mux settings for GMAC */
37 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
39 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
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| /openbmc/linux/Documentation/devicetree/bindings/mux/ |
| H A D | gpio-mux.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
17 multiplexer GPIO pins, where the first pin is the least significant
18 bit. An active pin is a binary 1, an inactive pin is a binary 0.
22 const: gpio-mux
24 mux-gpios:
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| /openbmc/linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
77 * @groups: An array of pin groups that may select this function.
87 * struct tegra_pingroup - Tegra pin group
88 * @name The name of the pin group.
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| /openbmc/linux/drivers/pinctrl/visconti/ |
| H A D | pinctrl-common.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include "pinctrl-common.h"
19 #include "../pinctrl-utils.h"
42 const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin]; in visconti_pin_config_set() local
49 dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name); in visconti_pin_config_set()
51 spin_lock_irqsave(&priv->lock, flags); in visconti_pin_config_set()
64 val = readl(priv->base + pin->pudsel_offset); in visconti_pin_config_set()
65 val &= ~BIT(pin->pud_shift); in visconti_pin_config_set()
66 val |= set_val << pin->pud_shift; in visconti_pin_config_set()
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| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | st,stm32-pinctrl.txt | 1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
5 also provides ability to multiplex and configure the output of various on-chip
8 Pin controller node:
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
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| /openbmc/linux/drivers/pinctrl/freescale/ |
| H A D | pinctrl-imx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
22 * struct imx_pin_mmio - MMIO pin configurations
23 * @mux_mode: the mux mode for this pin.
24 * @input_reg: the select input register offset for this pin if any
26 * @input_val: the select input value for this pin.
27 * @configs: the config for this pin.
37 * struct imx_pin_scu - SCU pin configurations
38 * @mux: the mux mode for this pin.
39 * @configs: the config for this pin.
47 * struct imx_pin - describes a single i.MX pin
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
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| /openbmc/linux/Documentation/i2c/muxes/ |
| H A D | i2c-mux-gpio.rst | 2 Kernel driver i2c-mux-gpio
8 -----------
10 i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
11 from a master I2C bus and a hardware MUX controlled through GPIO pins.
15 ---------- ---------- Bus segment 1 - - - - -
16 | | SCL/SDA | |-------------- | |
17 | |------------| |
19 | Linux | GPIO 1..N | MUX |--------------- Devices
20 | |------------| | | |
22 | | | |---------------| |
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