15835823dSIan Campbell #include <common.h>
25835823dSIan Campbell #include <netdev.h>
35835823dSIan Campbell #include <miiphy.h>
45835823dSIan Campbell #include <asm/gpio.h>
55835823dSIan Campbell #include <asm/io.h>
65835823dSIan Campbell #include <asm/arch/clock.h>
75835823dSIan Campbell #include <asm/arch/gpio.h>
85835823dSIan Campbell
eth_init_board(void)9fc8991c6SHans de Goede void eth_init_board(void)
105835823dSIan Campbell {
115835823dSIan Campbell int pin;
125835823dSIan Campbell struct sunxi_ccm_reg *const ccm =
135835823dSIan Campbell (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
145835823dSIan Campbell
155835823dSIan Campbell /* Set up clock gating */
1644d8ae5bSHans de Goede #ifdef CONFIG_SUNXI_GEN_SUN6I
17eafec320SHans de Goede setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18eafec320SHans de Goede setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
1944d8ae5bSHans de Goede #else
2044d8ae5bSHans de Goede setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
21eafec320SHans de Goede #endif
225835823dSIan Campbell
235835823dSIan Campbell /* Set MII clock */
24ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII
255835823dSIan Campbell setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
265835823dSIan Campbell CCM_GMAC_CTRL_GPIT_RGMII);
27c13f60d9SHans de Goede setbits_le32(&ccm->gmac_clk_cfg,
28c13f60d9SHans de Goede CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
29ef7e723bSChen-Yu Tsai #else
30ef7e723bSChen-Yu Tsai setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
31ef7e723bSChen-Yu Tsai CCM_GMAC_CTRL_GPIT_MII);
32ef7e723bSChen-Yu Tsai #endif
335835823dSIan Campbell
34eafec320SHans de Goede #ifndef CONFIG_MACH_SUN6I
355835823dSIan Campbell /* Configure pin mux settings for GMAC */
36*aba39249SStefan Mavrodiev #ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
37*aba39249SStefan Mavrodiev for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
38*aba39249SStefan Mavrodiev #else
395835823dSIan Campbell for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
40*aba39249SStefan Mavrodiev #endif
41ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII
425835823dSIan Campbell /* skip unused pins in RGMII mode */
435835823dSIan Campbell if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
445835823dSIan Campbell continue;
45ef7e723bSChen-Yu Tsai #endif
46487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
475835823dSIan Campbell sunxi_gpio_set_drv(pin, 3);
485835823dSIan Campbell }
49eafec320SHans de Goede #elif defined CONFIG_RGMII
50eafec320SHans de Goede /* Configure sun6i RGMII mode pin mux settings */
51eafec320SHans de Goede for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
52487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
53eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3);
54eafec320SHans de Goede }
55eafec320SHans de Goede for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
56487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
57eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3);
58eafec320SHans de Goede }
59eafec320SHans de Goede for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
60487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
61eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3);
62eafec320SHans de Goede }
63eafec320SHans de Goede for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
64487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
65eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3);
66eafec320SHans de Goede }
67eafec320SHans de Goede #elif defined CONFIG_GMII
68eafec320SHans de Goede /* Configure sun6i GMII mode pin mux settings */
69eafec320SHans de Goede for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
70487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
71eafec320SHans de Goede sunxi_gpio_set_drv(pin, 2);
72eafec320SHans de Goede }
73eafec320SHans de Goede #else
74eafec320SHans de Goede /* Configure sun6i MII mode pin mux settings */
75eafec320SHans de Goede for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
76487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
77eafec320SHans de Goede for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
78487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
79eafec320SHans de Goede for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
80487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
81eafec320SHans de Goede for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
82487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
83eafec320SHans de Goede for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
84487b3277SPaul Kocialkowski sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
85eafec320SHans de Goede #endif
865835823dSIan Campbell }
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