Lines Matching +full:pin +full:- +full:mux

1 /* SPDX-License-Identifier: GPL-2.0-only */
47 /* argument: Integer, range is HW-dependant */
49 /* argument: Integer, range is HW-dependant */
51 /* argument: Integer, range is HW-dependant */
53 /* argument: Integer, range is HW-dependant */
55 /* argument: Integer, range is HW-dependant */
75 * struct tegra_function - Tegra pinctrl mux function
77 * @groups: An array of pin groups that may select this function.
87 * struct tegra_pingroup - Tegra pin group
88 * @name The name of the pin group.
89 * @pins An array of pin IDs included in this pin group.
91 * @funcs The mux functions which can be muxed onto this group.
92 * @mux_reg: Mux register offset.
93 * This register contains the mux, einput, odrain, lock,
95 * @mux_bank: Mux register bank.
96 * @mux_bit: Mux register bit.
97 * @pupd_reg: Pull-up/down register offset.
98 * @pupd_bank: Pull-up/down register bank.
99 * @pupd_bit: Pull-up/down register bit.
100 * @tri_reg: Tri-state register offset.
101 * @tri_bank: Tri-state register bank.
102 * @tri_bit: Tri-state register bit.
103 * @einput_bit: Enable-input register bit.
104 * @odrain_bit: Open-drain register bit.
128 * -1 in a *_reg field means that feature is unsupported for this group.
129 * *_bank and *_reg values are irrelevant when *_reg is -1.
130 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
132 * A representation of a group of pins (possibly just one pin) in the Tegra
133 * pin controller. Each group allows some parameter or parameters to be
134 * configured. The most common is mux function selection. Many others exist
135 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
178 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
179 * @ngpios: The number of GPIO pins the pin controller HW affects.
180 * @pins: An array describing all pins the pin controller affects.
185 * @functions: An array describing all mux functions the SoC supports.
187 * @groups: An array describing all pin groups the pin SoC supports.