1 // SPDX-License-Identifier: GPL-2.0+
67  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
68  * on new IP with support for periph C and D the way to mux in
72  * @mux_A_periph: assign the corresponding pin to the peripheral A function.
73  * @mux_B_periph: assign the corresponding pin to the peripheral B function.
74  * @mux_C_periph: assign the corresponding pin to the peripheral C function.
75  * @mux_D_periph: assign the corresponding pin to the peripheral D function.
91 	void (*set_drivestrength)(struct at91_port *pio, u32 pin,
95 static u32 two_bit_pin_value_shift_amount(u32 pin)  in two_bit_pin_value_shift_amount()  argument
97 	/* return the shift value for a pin for "two bit" per pin registers,  in two_bit_pin_value_shift_amount()
99 	return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)  in two_bit_pin_value_shift_amount()
100 			? pin - MAX_NB_GPIO_PER_BANK/2 : pin);  in two_bit_pin_value_shift_amount()
105 	writel(mask, &pio->idr);  in at91_mux_disable_interrupt()
111 		writel(mask, &pio->mux.pio3.ppddr);  in at91_mux_set_pullup()
113 	writel(mask, (on ? &pio->puer : &pio->pudr));  in at91_mux_set_pullup()
119 	writel(mask, (val ? &pio->sodr : &pio->codr));  in at91_mux_set_output()
120 	writel(mask, (is_on ? &pio->oer : &pio->odr));  in at91_mux_set_output()
125 	writel(mask, (on ? &pio->mder : &pio->mddr));  in at91_mux_set_multidrive()
130 	writel(mask, &pio->mux.pio2.asr);  in at91_mux_set_A_periph()
135 	writel(mask, &pio->mux.pio2.bsr);  in at91_mux_set_B_periph()
140 	writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_A_periph()
141 	writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_A_periph()
146 	writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_B_periph()
147 	writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_B_periph()
152 	writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_C_periph()
153 	writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_C_periph()
158 	writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);  in at91_mux_pio3_set_D_periph()
159 	writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);  in at91_mux_pio3_set_D_periph()
164 	writel(mask, (is_on ? &pio->ifer : &pio->ifdr));  in at91_mux_set_deglitch()
171 		writel(mask, &pio->mux.pio3.ifscdr);  in at91_mux_pio3_set_deglitch()
179 		writel(mask, &pio->mux.pio3.ifscer);  in at91_mux_pio3_set_debounce()
180 		writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);  in at91_mux_pio3_set_debounce()
181 		writel(mask, &pio->ifer);  in at91_mux_pio3_set_debounce()
183 		writel(mask, &pio->mux.pio3.ifscdr);  in at91_mux_pio3_set_debounce()
191 		writel(mask, &pio->pudr);  in at91_mux_pio3_set_pulldown()
193 	writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));  in at91_mux_pio3_set_pulldown()
199 	writel(readl(&pio->schmitt) | mask, &pio->schmitt);  in at91_mux_pio3_disable_schmitt_trig()
202 static void set_drive_strength(void *reg, u32 pin, u32 strength)  in set_drive_strength()  argument
204 	u32 shift = two_bit_pin_value_shift_amount(pin);  in set_drive_strength()
210 					       u32 pin, u32 setting)  in at91_mux_sama5d3_set_drivestrength()  argument
214 	reg = &pio->driver12;  in at91_mux_sama5d3_set_drivestrength()
215 	if (pin >= MAX_NB_GPIO_PER_BANK / 2)  in at91_mux_sama5d3_set_drivestrength()
216 		reg = &pio->driver2;  in at91_mux_sama5d3_set_drivestrength()
223 	set_drive_strength(reg, pin, setting);  in at91_mux_sama5d3_set_drivestrength()
227 					      u32 pin, u32 setting)  in at91_mux_sam9x5_set_drivestrength()  argument
231 	reg = &pio->driver1;  in at91_mux_sam9x5_set_drivestrength()
232 	if (pin >= MAX_NB_GPIO_PER_BANK / 2)  in at91_mux_sam9x5_set_drivestrength()
233 		reg = &pio->driver12;  in at91_mux_sam9x5_set_drivestrength()
241 	setting = DRIVE_STRENGTH_HI - setting;  in at91_mux_sam9x5_set_drivestrength()
243 	set_drive_strength(reg, pin, setting);  in at91_mux_sam9x5_set_drivestrength()
278 	writel(mask, &pio->pdr);  in at91_mux_gpio_disable()
283 	writel(mask, &pio->per);  in at91_mux_gpio_enable()
284 	writel(mask, (input ? &pio->odr : &pio->oer));  in at91_mux_gpio_enable()
288 			struct at91_port *pio, u32 mask, enum at91_mux mux)  in at91_pmx_set()  argument
291 	switch (mux) {  in at91_pmx_set()
296 		ops->mux_A_periph(pio, mask);  in at91_pmx_set()
299 		ops->mux_B_periph(pio, mask);  in at91_pmx_set()
302 		if (!ops->mux_C_periph)  in at91_pmx_set()
303 			return -EINVAL;  in at91_pmx_set()
304 		ops->mux_C_periph(pio, mask);  in at91_pmx_set()
307 		if (!ops->mux_D_periph)  in at91_pmx_set()
308 			return -EINVAL;  in at91_pmx_set()
309 		ops->mux_D_periph(pio, mask);  in at91_pmx_set()
312 	if (mux)  in at91_pmx_set()
319 			    struct at91_port *pio, u32 pin, u32 config)  in at91_pinconf_set()  argument
321 	u32 mask = BIT(pin);  in at91_pinconf_set()
324 		return -EINVAL;  in at91_pinconf_set()
330 	if (ops->set_deglitch)  in at91_pinconf_set()
331 		ops->set_deglitch(pio, mask, config & DEGLITCH);  in at91_pinconf_set()
332 	if (ops->set_debounce)  in at91_pinconf_set()
333 		ops->set_debounce(pio, mask, config & DEBOUNCE,  in at91_pinconf_set()
335 	if (ops->set_pulldown)  in at91_pinconf_set()
336 		ops->set_pulldown(pio, mask, config & PULL_DOWN);  in at91_pinconf_set()
337 	if (ops->disable_schmitt_trig && config & DIS_SCHMIT)  in at91_pinconf_set()
338 		ops->disable_schmitt_trig(pio, mask);  in at91_pinconf_set()
339 	if (ops->set_drivestrength)  in at91_pinconf_set()
340 		ops->set_drivestrength(pio, pin,  in at91_pinconf_set()
346 static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)  in at91_pin_check_config()  argument
350 	if (bank >= priv->nbanks) {  in at91_pin_check_config()
351 		debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);  in at91_pin_check_config()
352 		return -EINVAL;  in at91_pin_check_config()
355 	if (pin >= MAX_NB_GPIO_PER_BANK) {  in at91_pin_check_config()
356 		debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);  in at91_pin_check_config()
357 		return -EINVAL;  in at91_pin_check_config()
366 	const void *blob = gd->fdt_blob;  in at91_pinctrl_set_state()
370 	u32 bank, pin;  in at91_pinctrl_set_state()  local
374 	enum at91_mux mux;  in at91_pinctrl_set_state()  local
380 	 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,  in at91_pinctrl_set_state()
389 		return -EINVAL;  in at91_pinctrl_set_state()
393 		pin = *list++;  in at91_pinctrl_set_state()
394 		mux = *list++;  in at91_pinctrl_set_state()
397 		ret = at91_pin_check_config(dev, bank, pin);  in at91_pinctrl_set_state()
401 		pio = priv->reg_base[bank];  in at91_pinctrl_set_state()
402 		mask = BIT(pin);  in at91_pinctrl_set_state()
404 		ret = at91_pmx_set(ops, pio, mask, mux);  in at91_pinctrl_set_state()
408 		ret = at91_pinconf_set(ops, pio, pin, conf);  in at91_pinctrl_set_state()
431 		priv->reg_base[index] = (struct at91_port *)addr_base;  in at91_pinctrl_probe()
434 	priv->nbanks = index;  in at91_pinctrl_probe()
440 	{ .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
441 	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
442 	{ .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },