Searched +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy (Results 1 – 25 of 79) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Masahiro Yamada <yamada.masahiro@socionext.com>15 - enum:16 - amd,pensando-elba-sd4hc17 - microchip,mpfs-sd4hc18 - socionext,uniphier-sd4hc19 - const: cdns,sd4hc34 # PHY DLL input delays:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - Ulf Hansson <ulf.hansson@linaro.org>14 - $ref: sdhci-common.yaml#19 - enum:20 - ti,am62-sdhci21 - ti,am64-sdhci-4bit[all …]
1 // SPDX-License-Identifier: GPL-2.0+17 /* HRS - Host Register Set (specific to Cadence) */18 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */37 /* SRS - Slot Register Set (SDHCI-compatible) */40 /* PHY */55 * The tuned val register is 6 bit-wide, but not the whole of the range is56 * available. The range 0-42 seems to be available (then 43 wraps around to 0)73 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },74 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },75 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra USB PHY10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>17 - items:18 - enum:[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later17 #include "sdhci-pltfm.h"19 /* HRS - Host Register Set (specific to Cadence) */20 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */39 /* SRS - Slot Register Set (SDHCI-compatible) */42 /* PHY */57 * The tuned val register is 6 bit-wide, but not the whole of the range is58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>9 * Based on sdhci-of-esdhc.c18 #include <linux/clk-provider.h>23 #include <linux/phy/phy.h>26 #include <linux/firmware/xlnx-zynqmp.h>29 #include "sdhci-cqhci.h"30 #include "sdhci-pltfm.h"92 * On some SoCs the syscon area has a feature where the upper 16-bits of93 * each 32-bit register act as a write mask for the lower 16-bits. This allows[all …]
1 // SPDX-License-Identifier: GPL-2.03 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com18 #include "sdhci-cqhci.h"19 #include "sdhci-pltfm.h"29 /* PHY Registers */88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",108 "ti,itap-del-sel-legacy",110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2018 Intel Corporation. */15 #define OPTION_UNSET -136 /* Transmit Interrupt Delay in units of 1.024 microseconds37 * Tx interrupt delay needs to typically be set to something non-zero39 * Valid Range: 0-6553541 E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");46 /* Transmit Absolute Interrupt Delay in units of 1.024 microseconds48 * Valid Range: 0-6553550 E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */2 /* Copyright(c) 1999 - 2018 Intel Corporation. */17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */104 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */198 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/thermal/thermal.h>14 compatible = "socionext,uniphier-pxs3";15 #address-cells = <2>;16 #size-cells = <2>;17 interrupt-parent = <&gic>;20 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/thermal/thermal.h>14 compatible = "socionext,uniphier-ld20";15 #address-cells = <2>;16 #size-cells = <2>;17 interrupt-parent = <&gic>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>13 compatible = "socionext,uniphier-ld11";14 #address-cells = <2>;15 #size-cells = <2>;16 interrupt-parent = <&gic>;19 #address-cells = <2>;20 #size-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>14 compatible = "socionext,uniphier-ld11";15 #address-cells = <2>;16 #size-cells = <2>;17 interrupt-parent = <&gic>;20 #address-cells = <2>;21 #size-cells = <0>;23 cpu-map {[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>14 compatible = "socionext,uniphier-pxs3";15 #address-cells = <2>;16 #size-cells = <2>;17 interrupt-parent = <&gic>;20 #address-cells = <2>;21 #size-cells = <0>;23 cpu-map {[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/thermal/thermal.h>15 compatible = "socionext,uniphier-ld20";16 #address-cells = <2>;17 #size-cells = <2>;18 interrupt-parent = <&gic>;21 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * Copyright (c) 2009-2015 NVIDIA Corporation12 #include <asm-generic/gpio.h>14 #include <asm/arch-tegra/usb.h>15 #include <asm/arch-tegra/clk_rst.h>37 PARAM_DIVM, /* PLL INPUT DIVIDER */41 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */42 PARAM_STABLE_COUNT, /* PLL-U STABLE count */43 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */44 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */[all …]
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2 PHY Abstraction Layer10 PHY. The PHY concerns itself with negotiating link parameters with the link17 the PHY management code with the network driver. This has resulted in large23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.26 #. Increase code-reuse27 #. Increase overall code-maintainability30 Basically, this layer is meant to provide an interface to PHY devices which37 Most network devices are connected to a PHY by means of a management bus.47 mii_id is the address on the bus for the PHY, and regnum is the register67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2018 Intel Corporation. */62 "Copyright (c) 1999-2016 Intel Corporation.";77 /* ixgbe_pci_tbl - PCI Device ID Table152 …"Maximum number of virtual functions to allocate per physical function - default is zero and maxim…158 "Allow unsupported and untested SFP+ modules on 82599-based adapters");161 static int debug = -1;181 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); in netif_is_ixgbe()190 parent_bus = adapter->pdev->bus->parent; in ixgbe_read_pci_cfg_word_parent()192 return -1; in ixgbe_read_pci_cfg_word_parent()[all …]
2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal42 * AR5210-Specific TXDP registers46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */[all …]
4 Copyright(c) 1999 - 2006 Intel Corporation.23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497115 * RW - register is both readable and writable116 * RO - register is read only117 * WO - register is write only118 * R/clr - register is read only and is cleared when read119 * A - register array121 #define E1000_CTRL 0x00000 /* Device Control - RW */122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 2007 - 2018 Intel Corporation. */9 #include <linux/delay.h>104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \130 "legacy-rx",139 struct e1000_hw *hw = &adapter->hw; in igb_get_link_ksettings()140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_link_ksettings()141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_get_link_ksettings()146 status = pm_runtime_suspended(&adapter->pdev->dev) ? in igb_get_link_ksettings()[all …]
41 #include <linux/delay.h>121 * PSR control version legacy131 * ABM control version legacy141 * Physical framebuffer address location, 64-bit.243 * @knee_threshold: Current x-position of ACE knee (u0.16).263 * union dmub_addr - DMUB physical/virtual 64-bit address.328 * Back to back flip, therefore cannot power down PHY361 * @force_phy_power_on: Force phy power on380 * @disable_delay_alpm_on: Force disable delay alpm on429 * @phy_power_state: Indicates current phy power state[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright(c) 1999 - 2006 Intel Corporation. */89 * e1000_set_phy_type - Set the phy type member in the hw struct.94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()97 switch (hw->phy_id) { in e1000_set_phy_type()103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()107 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()108 hw->mac_type == e1000_82547 || in e1000_set_phy_type()[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649736 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)51 writel((value), ((a)->hw_addr + E1000_##reg))53 readl((a)->hw_addr + E1000_##reg)55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))169 /* PHY status info structure and supporting enums */[all …]