1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22439e4bfSJean-Christophe PLAGNIOL-VILLARD /******************************************************************************* 32439e4bfSJean-Christophe PLAGNIOL-VILLARD 42439e4bfSJean-Christophe PLAGNIOL-VILLARD 52439e4bfSJean-Christophe PLAGNIOL-VILLARD Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 62c2668f9SRoy Zang Copyright 2011 Freescale Semiconductor, Inc. 72439e4bfSJean-Christophe PLAGNIOL-VILLARD 82439e4bfSJean-Christophe PLAGNIOL-VILLARD Contact Information: 92439e4bfSJean-Christophe PLAGNIOL-VILLARD Linux NICS <linux.nics@intel.com> 102439e4bfSJean-Christophe PLAGNIOL-VILLARD Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 112439e4bfSJean-Christophe PLAGNIOL-VILLARD 122439e4bfSJean-Christophe PLAGNIOL-VILLARD *******************************************************************************/ 132439e4bfSJean-Christophe PLAGNIOL-VILLARD 142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* e1000_hw.h 152439e4bfSJean-Christophe PLAGNIOL-VILLARD * Structures, enums, and macros for the MAC 162439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 172439e4bfSJean-Christophe PLAGNIOL-VILLARD 182439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifndef _E1000_HW_H_ 192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define _E1000_HW_H_ 202439e4bfSJean-Christophe PLAGNIOL-VILLARD 21ce5207e1SKyle Moffett #include <linux/list.h> 222439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <malloc.h> 232439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <net.h> 24c6d80a15SSimon Glass /* Avoids a compile error since struct eth_device is not defined */ 25c6d80a15SSimon Glass #ifndef CONFIG_DM_ETH 26ad3381cfSBen Warren #include <netdev.h> 27c6d80a15SSimon Glass #endif 282439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 292439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <pci.h> 302439e4bfSJean-Christophe PLAGNIOL-VILLARD 31ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 32ce5207e1SKyle Moffett #include <spi.h> 33ce5207e1SKyle Moffett #endif 34ce5207e1SKyle Moffett 35d60626f8SKyle Moffett #define E1000_ERR(NIC, fmt, args...) \ 36d60626f8SKyle Moffett printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args) 372439e4bfSJean-Christophe PLAGNIOL-VILLARD 382439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef E1000_DEBUG 39d60626f8SKyle Moffett #define E1000_DBG(NIC, fmt, args...) \ 40d60626f8SKyle Moffett printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args) 412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEBUGOUT(fmt, args...) printf(fmt ,##args) 42d60626f8SKyle Moffett #define DEBUGFUNC() printf("%s\n", __func__); 432439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 44d60626f8SKyle Moffett #define E1000_DBG(HW, args...) do { } while (0) 45d60626f8SKyle Moffett #define DEBUGFUNC() do { } while (0) 46d60626f8SKyle Moffett #define DEBUGOUT(fmt, args...) do { } while (0) 472439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 482439e4bfSJean-Christophe PLAGNIOL-VILLARD 492326a94dSKyle Moffett /* I/O wrapper functions */ 502326a94dSKyle Moffett #define E1000_WRITE_REG(a, reg, value) \ 517a341066SWolfgang Denk writel((value), ((a)->hw_addr + E1000_##reg)) 522326a94dSKyle Moffett #define E1000_READ_REG(a, reg) \ 537a341066SWolfgang Denk readl((a)->hw_addr + E1000_##reg) 542326a94dSKyle Moffett #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 557a341066SWolfgang Denk writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) 562326a94dSKyle Moffett #define E1000_READ_REG_ARRAY(a, reg, offset) \ 577a341066SWolfgang Denk readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) 582326a94dSKyle Moffett #define E1000_WRITE_FLUSH(a) \ 597a341066SWolfgang Denk do { E1000_READ_REG(a, STATUS); } while (0) 602326a94dSKyle Moffett 612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Forward declarations of structures used by the shared code */ 622439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw; 632439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw_stats; 642439e4bfSJean-Christophe PLAGNIOL-VILLARD 652326a94dSKyle Moffett /* Internal E1000 helper functions */ 66ce5207e1SKyle Moffett struct e1000_hw *e1000_find_card(unsigned int cardnum); 678712adfdSRojhalat Ibrahim 688712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 692326a94dSKyle Moffett int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 702326a94dSKyle Moffett void e1000_standby_eeprom(struct e1000_hw *hw); 712326a94dSKyle Moffett void e1000_release_eeprom(struct e1000_hw *hw); 722326a94dSKyle Moffett void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 732326a94dSKyle Moffett void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); 748712adfdSRojhalat Ibrahim #endif 752326a94dSKyle Moffett 76ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 77ce5207e1SKyle Moffett int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, 78ce5207e1SKyle Moffett int argc, char * const argv[]); 79ce5207e1SKyle Moffett #endif 80ce5207e1SKyle Moffett 812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Enumerated types specific to the e1000 hardware */ 822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Media Access Controlers */ 832439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 842439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_undefined = 0, 852439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82542_rev2_0, 862439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82542_rev2_1, 872439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82543, 882439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82544, 892439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82540, 902439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82545, 91aa070789SRoy Zang e1000_82545_rev_3, 922439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_82546, 93aa070789SRoy Zang e1000_82546_rev_3, 94ac3315c2SAndre Schwarz e1000_82541, 95ac3315c2SAndre Schwarz e1000_82541_rev_2, 96aa070789SRoy Zang e1000_82547, 97aa070789SRoy Zang e1000_82547_rev_2, 98aa070789SRoy Zang e1000_82571, 99aa070789SRoy Zang e1000_82572, 100aa070789SRoy Zang e1000_82573, 1012c2668f9SRoy Zang e1000_82574, 102aa070789SRoy Zang e1000_80003es2lan, 103aa070789SRoy Zang e1000_ich8lan, 10495186063SMarek Vasut e1000_igb, 1052439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_num_macs 1062439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_mac_type; 1072439e4bfSJean-Christophe PLAGNIOL-VILLARD 1082439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Media Types */ 1092439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1102439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_media_type_copper = 0, 1112439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_media_type_fiber = 1, 112aa070789SRoy Zang e1000_media_type_internal_serdes = 2, 1132439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_num_media_types 1142439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_media_type; 1152439e4bfSJean-Christophe PLAGNIOL-VILLARD 1162439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 117aa070789SRoy Zang e1000_eeprom_uninitialized = 0, 118aa070789SRoy Zang e1000_eeprom_spi, 119aa070789SRoy Zang e1000_eeprom_microwire, 120aa070789SRoy Zang e1000_eeprom_flash, 121aa070789SRoy Zang e1000_eeprom_ich8, 122aa070789SRoy Zang e1000_eeprom_none, /* No NVM support */ 12395186063SMarek Vasut e1000_eeprom_invm, 124aa070789SRoy Zang e1000_num_eeprom_types 125aa070789SRoy Zang } e1000_eeprom_type; 126aa070789SRoy Zang 127aa070789SRoy Zang typedef enum { 1282439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_10_half = 0, 1292439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_10_full = 1, 1302439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_100_half = 2, 1312439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_100_full = 3 1322439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_speed_duplex_type; 1332439e4bfSJean-Christophe PLAGNIOL-VILLARD 1342439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow Control Settings */ 1352439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1362439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_fc_none = 0, 1372439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_fc_rx_pause = 1, 1382439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_fc_tx_pause = 2, 1392439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_fc_full = 3, 1402439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_fc_default = 0xFF 1412439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_fc_type; 1422439e4bfSJean-Christophe PLAGNIOL-VILLARD 1432439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCI bus types */ 1442439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1452439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_type_unknown = 0, 1462439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_type_pci, 147aa070789SRoy Zang e1000_bus_type_pcix, 148aa070789SRoy Zang e1000_bus_type_pci_express, 149aa070789SRoy Zang e1000_bus_type_reserved 1502439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_bus_type; 1512439e4bfSJean-Christophe PLAGNIOL-VILLARD 1522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCI bus speeds */ 1532439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1542439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_speed_unknown = 0, 1552439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_speed_33, 1562439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_speed_66, 1572439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_speed_100, 1582439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_speed_133, 1592439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_speed_reserved 1602439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_bus_speed; 1612439e4bfSJean-Christophe PLAGNIOL-VILLARD 1622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCI bus widths */ 1632439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1642439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_width_unknown = 0, 1652439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_width_32, 1662439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_bus_width_64 1672439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_bus_width; 1682439e4bfSJean-Christophe PLAGNIOL-VILLARD 1692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY status info structure and supporting enums */ 1702439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1712439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length_50 = 0, 1722439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length_50_80, 1732439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length_80_110, 1742439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length_110_140, 1752439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length_140, 1762439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length_undefined = 0xFF 1772439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_cable_length; 1782439e4bfSJean-Christophe PLAGNIOL-VILLARD 1792439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1802439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_10bt_ext_dist_enable_normal = 0, 1812439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_10bt_ext_dist_enable_lower, 1822439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_10bt_ext_dist_enable_undefined = 0xFF 1832439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_10bt_ext_dist_enable; 1842439e4bfSJean-Christophe PLAGNIOL-VILLARD 1852439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1862439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_rev_polarity_normal = 0, 1872439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_rev_polarity_reversed, 1882439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_rev_polarity_undefined = 0xFF 1892439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_rev_polarity; 1902439e4bfSJean-Christophe PLAGNIOL-VILLARD 1912439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1922439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_polarity_reversal_enabled = 0, 1932439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_polarity_reversal_disabled, 1942439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_polarity_reversal_undefined = 0xFF 1952439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_polarity_reversal; 1962439e4bfSJean-Christophe PLAGNIOL-VILLARD 1972439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 1982439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_auto_x_mode_manual_mdi = 0, 1992439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_auto_x_mode_manual_mdix, 2002439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_auto_x_mode_auto1, 2012439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_auto_x_mode_auto2, 2022439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_auto_x_mode_undefined = 0xFF 2032439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_auto_x_mode; 2042439e4bfSJean-Christophe PLAGNIOL-VILLARD 2052439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef enum { 2062439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_1000t_rx_status_not_ok = 0, 2072439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_1000t_rx_status_ok, 2082439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_1000t_rx_status_undefined = 0xFF 2092439e4bfSJean-Christophe PLAGNIOL-VILLARD } e1000_1000t_rx_status; 2102439e4bfSJean-Christophe PLAGNIOL-VILLARD 211ac3315c2SAndre Schwarz typedef enum { 212ac3315c2SAndre Schwarz e1000_phy_m88 = 0, 213ac3315c2SAndre Schwarz e1000_phy_igp, 214ac3315c2SAndre Schwarz e1000_phy_igp_2, 215aa070789SRoy Zang e1000_phy_gg82563, 216aa070789SRoy Zang e1000_phy_igp_3, 217aa070789SRoy Zang e1000_phy_ife, 21895186063SMarek Vasut e1000_phy_igb, 2192c2668f9SRoy Zang e1000_phy_bm, 220ac3315c2SAndre Schwarz e1000_phy_undefined = 0xFF 221ac3315c2SAndre Schwarz } e1000_phy_type; 222ac3315c2SAndre Schwarz 2232439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_phy_info { 2242439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_cable_length cable_length; 2252439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_10bt_ext_dist_enable extended_10bt_distance; 2262439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_rev_polarity cable_polarity; 2272439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_polarity_reversal polarity_correction; 2282439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_auto_x_mode mdix_mode; 2292439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_1000t_rx_status local_rx; 2302439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_1000t_rx_status remote_rx; 2312439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 2322439e4bfSJean-Christophe PLAGNIOL-VILLARD 2332439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_phy_stats { 2342439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t idle_errors; 2352439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t receive_errors; 2362439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 2372439e4bfSJean-Christophe PLAGNIOL-VILLARD 2382439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Error Codes */ 2392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_SUCCESS 0 2402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ERR_EEPROM 1 2412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ERR_PHY 2 2422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ERR_CONFIG 3 2432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ERR_PARAM 4 2442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ERR_MAC_TYPE 5 245ac3315c2SAndre Schwarz #define E1000_ERR_PHY_TYPE 6 246ac3315c2SAndre Schwarz #define E1000_ERR_NOLINK 7 247ac3315c2SAndre Schwarz #define E1000_ERR_TIMEOUT 8 248ac3315c2SAndre Schwarz #define E1000_ERR_RESET 9 249ac3315c2SAndre Schwarz #define E1000_ERR_MASTER_REQUESTS_PENDING 10 250ac3315c2SAndre Schwarz #define E1000_ERR_HOST_INTERFACE_COMMAND 11 251ac3315c2SAndre Schwarz #define E1000_BLK_PHY_RESET 12 252aa070789SRoy Zang #define E1000_ERR_SWFW_SYNC 13 2532439e4bfSJean-Christophe PLAGNIOL-VILLARD 2542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCI Device IDs */ 2552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82542 0x1000 2562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82543GC_FIBER 0x1001 2572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82543GC_COPPER 0x1004 2582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82544EI_COPPER 0x1008 2592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82544EI_FIBER 0x1009 2602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82544GC_COPPER 0x100C 2612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82544GC_LOM 0x100D 2622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82540EM 0x100E 2632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82540EM_LOM 0x1015 264aa070789SRoy Zang #define E1000_DEV_ID_82540EP_LOM 0x1016 265aa070789SRoy Zang #define E1000_DEV_ID_82540EP 0x1017 266aa070789SRoy Zang #define E1000_DEV_ID_82540EP_LP 0x101E 2672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82545EM_COPPER 0x100F 2682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82545EM_FIBER 0x1011 269aa070789SRoy Zang #define E1000_DEV_ID_82545GM_COPPER 0x1026 270aa070789SRoy Zang #define E1000_DEV_ID_82545GM_FIBER 0x1027 271aa070789SRoy Zang #define E1000_DEV_ID_82545GM_SERDES 0x1028 2722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82546EB_COPPER 0x1010 2732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DEV_ID_82546EB_FIBER 0x1012 274aa070789SRoy Zang #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 275aa070789SRoy Zang #define E1000_DEV_ID_82541EI 0x1013 276aa070789SRoy Zang #define E1000_DEV_ID_82541EI_MOBILE 0x1018 277aa070789SRoy Zang #define E1000_DEV_ID_82541ER_LOM 0x1014 278ac3315c2SAndre Schwarz #define E1000_DEV_ID_82541ER 0x1078 279aa070789SRoy Zang #define E1000_DEV_ID_82547GI 0x1075 280aa070789SRoy Zang #define E1000_DEV_ID_82541GI 0x1076 281aa070789SRoy Zang #define E1000_DEV_ID_82541GI_MOBILE 0x1077 282aa3b8bf9SWolfgang Grandegger #define E1000_DEV_ID_82541GI_LF 0x107C 283aa070789SRoy Zang #define E1000_DEV_ID_82546GB_COPPER 0x1079 284aa070789SRoy Zang #define E1000_DEV_ID_82546GB_FIBER 0x107A 285aa070789SRoy Zang #define E1000_DEV_ID_82546GB_SERDES 0x107B 286aa070789SRoy Zang #define E1000_DEV_ID_82546GB_PCIE 0x108A 287aa070789SRoy Zang #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 288aa070789SRoy Zang #define E1000_DEV_ID_82547EI 0x1019 289aa070789SRoy Zang #define E1000_DEV_ID_82547EI_MOBILE 0x101A 290aa070789SRoy Zang #define E1000_DEV_ID_82571EB_COPPER 0x105E 291aa070789SRoy Zang #define E1000_DEV_ID_82571EB_FIBER 0x105F 292aa070789SRoy Zang #define E1000_DEV_ID_82571EB_SERDES 0x1060 293aa070789SRoy Zang #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 294aa070789SRoy Zang #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 295aa070789SRoy Zang #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 296aa070789SRoy Zang #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC 297aa070789SRoy Zang #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 298aa070789SRoy Zang #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 299aa070789SRoy Zang #define E1000_DEV_ID_82572EI_COPPER 0x107D 300aa070789SRoy Zang #define E1000_DEV_ID_82572EI_FIBER 0x107E 301aa070789SRoy Zang #define E1000_DEV_ID_82572EI_SERDES 0x107F 302aa070789SRoy Zang #define E1000_DEV_ID_82572EI 0x10B9 303aa070789SRoy Zang #define E1000_DEV_ID_82573E 0x108B 304aa070789SRoy Zang #define E1000_DEV_ID_82573E_IAMT 0x108C 305aa070789SRoy Zang #define E1000_DEV_ID_82573L 0x109A 3062c2668f9SRoy Zang #define E1000_DEV_ID_82574L 0x10D3 307aa070789SRoy Zang #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 308aa070789SRoy Zang #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 309aa070789SRoy Zang #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 310aa070789SRoy Zang #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 311aa070789SRoy Zang #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 312aa070789SRoy Zang 313aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 314aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 315aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IGP_C 0x104B 316aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IFE 0x104C 317aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 318aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 319aa070789SRoy Zang #define E1000_DEV_ID_ICH8_IGP_M 0x104D 320aa070789SRoy Zang 321aa070789SRoy Zang #define IGP03E1000_E_PHY_ID 0x02A80390 322aa070789SRoy Zang #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 323aa070789SRoy Zang #define IFE_PLUS_E_PHY_ID 0x02A80320 324aa070789SRoy Zang #define IFE_C_E_PHY_ID 0x02A80310 325aa070789SRoy Zang 326aa070789SRoy Zang #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, 327aa070789SRoy Zang Control and Address */ 328aa070789SRoy Zang #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special 329aa070789SRoy Zang control register */ 330472d5460SYork Sun #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false 331aa070789SRoy Zang Carrier Counter */ 332aa070789SRoy Zang #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet 333aa070789SRoy Zang Counter */ 334aa070789SRoy Zang #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error 335aa070789SRoy Zang Frame Counter */ 336aa070789SRoy Zang #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error 337aa070789SRoy Zang Counter */ 338aa070789SRoy Zang #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive 339aa070789SRoy Zang Premature End Of Frame 340aa070789SRoy Zang Error Counter */ 341aa070789SRoy Zang #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of 342aa070789SRoy Zang Frame Error Counter */ 343aa070789SRoy Zang #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber 344aa070789SRoy Zang Detect Counter */ 345aa070789SRoy Zang #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and 346aa070789SRoy Zang Status */ 347aa070789SRoy Zang #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and 348aa070789SRoy Zang LED configuration */ 349aa070789SRoy Zang #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 350aa070789SRoy Zang #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control 351aa070789SRoy Zang (HWI) */ 352aa070789SRoy Zang 353aa070789SRoy Zang #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto 354aa070789SRoy Zang reduced power down */ 355aa070789SRoy Zang #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power 356aa070789SRoy Zang state of 100BASE-TX */ 357aa070789SRoy Zang #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power 358aa070789SRoy Zang state of 10BASE-T */ 359aa070789SRoy Zang #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T 360aa070789SRoy Zang polarity */ 361aa070789SRoy Zang #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY 362aa070789SRoy Zang address */ 363aa070789SRoy Zang #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed 364aa070789SRoy Zang result 1=100Mbs, 0=10Mbs */ 365aa070789SRoy Zang #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation 366aa070789SRoy Zang duplex result 1=Full, 0=Half */ 367aa070789SRoy Zang #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 368aa070789SRoy Zang 369aa070789SRoy Zang #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down 370aa070789SRoy Zang disabled */ 371aa070789SRoy Zang #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 372aa070789SRoy Zang 0=Normal */ 373aa070789SRoy Zang #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity 374aa070789SRoy Zang Disabled, 0=Enabled */ 375aa070789SRoy Zang #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 376aa070789SRoy Zang 0=Normal Jabber Operation */ 377aa070789SRoy Zang #define IFE_PSC_FORCE_POLARITY_SHIFT 5 378aa070789SRoy Zang #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 379aa070789SRoy Zang 380aa070789SRoy Zang #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X 381aa070789SRoy Zang feature, default 0=disabled */ 382aa070789SRoy Zang #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 383aa070789SRoy Zang 0=force MDI */ 384aa070789SRoy Zang #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 385aa070789SRoy Zang #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm 386aa070789SRoy Zang is completed */ 387aa070789SRoy Zang #define IFE_PMC_MDIX_MODE_SHIFT 6 388aa070789SRoy Zang #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 389aa070789SRoy Zang 390aa070789SRoy Zang #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI 391aa070789SRoy Zang feature */ 392aa070789SRoy Zang #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 393aa070789SRoy Zang 0=failed */ 394aa070789SRoy Zang #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses 395aa070789SRoy Zang on the wire */ 396aa070789SRoy Zang #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 397aa070789SRoy Zang #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 398aa070789SRoy Zang #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication 399aa070789SRoy Zang type of problem on the line */ 400aa070789SRoy Zang #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to 401aa070789SRoy Zang the cable problem, in 80cm granularity */ 402aa070789SRoy Zang #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 403aa070789SRoy Zang #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 404aa070789SRoy Zang #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 405aa070789SRoy Zang off */ 406aa070789SRoy Zang #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 407aa070789SRoy Zang 408aa070789SRoy Zang 4098915f118SPaul Gortmaker #define NUM_DEV_IDS 16 4102439e4bfSJean-Christophe PLAGNIOL-VILLARD 4112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NODE_ADDRESS_SIZE 6 4122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ETH_LENGTH_OF_ADDRESS 6 4132439e4bfSJean-Christophe PLAGNIOL-VILLARD 4142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* MAC decode size is 128K - This is the size of BAR0 */ 4152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAC_DECODE_SIZE (128 * 1024) 4162439e4bfSJean-Christophe PLAGNIOL-VILLARD 4172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_2_0_REV_ID 2 4182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_2_1_REV_ID 3 419aa070789SRoy Zang #define E1000_REVISION_0 0 420aa070789SRoy Zang #define E1000_REVISION_1 1 421aa070789SRoy Zang #define E1000_REVISION_2 2 422aa070789SRoy Zang #define E1000_REVISION_3 3 4232439e4bfSJean-Christophe PLAGNIOL-VILLARD 4242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SPEED_10 10 4252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SPEED_100 100 4262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SPEED_1000 1000 4272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define HALF_DUPLEX 1 4282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FULL_DUPLEX 2 4292439e4bfSJean-Christophe PLAGNIOL-VILLARD 4302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The sizes (in bytes) of a ethernet packet */ 4312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ENET_HEADER_SIZE 14 4322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 4332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 4342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAXIMUM_ETHERNET_PACKET_SIZE \ 435a7c3d5e2SBin Meng (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) 4362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MINIMUM_ETHERNET_PACKET_SIZE \ 437a7c3d5e2SBin Meng (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) 438a7c3d5e2SBin Meng #define CRC_LENGTH ETH_FCS_LEN 4392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAX_JUMBO_FRAME_SIZE 0x3F00 4402439e4bfSJean-Christophe PLAGNIOL-VILLARD 4412439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 802.1q VLAN Packet Sizes */ 4422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 4432439e4bfSJean-Christophe PLAGNIOL-VILLARD 4442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Ethertype field values */ 4452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 4462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 4472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 4482439e4bfSJean-Christophe PLAGNIOL-VILLARD 4492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Packet Header defines */ 4502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IP_PROTOCOL_TCP 6 4512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IP_PROTOCOL_UDP 0x11 4522439e4bfSJean-Christophe PLAGNIOL-VILLARD 4532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* This defines the bits that are set in the Interrupt Mask 4542439e4bfSJean-Christophe PLAGNIOL-VILLARD * Set/Read Register. Each bit is documented below: 4552439e4bfSJean-Christophe PLAGNIOL-VILLARD * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 4562439e4bfSJean-Christophe PLAGNIOL-VILLARD * o RXSEQ = Receive Sequence Error 4572439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define POLL_IMS_ENABLE_MASK ( \ 4592439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_RXDMT0 | \ 4602439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_RXSEQ) 4612439e4bfSJean-Christophe PLAGNIOL-VILLARD 4622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* This defines the bits that are set in the Interrupt Mask 4632439e4bfSJean-Christophe PLAGNIOL-VILLARD * Set/Read Register. Each bit is documented below: 4642439e4bfSJean-Christophe PLAGNIOL-VILLARD * o RXT0 = Receiver Timer Interrupt (ring 0) 4652439e4bfSJean-Christophe PLAGNIOL-VILLARD * o TXDW = Transmit Descriptor Written Back 4662439e4bfSJean-Christophe PLAGNIOL-VILLARD * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 4672439e4bfSJean-Christophe PLAGNIOL-VILLARD * o RXSEQ = Receive Sequence Error 4682439e4bfSJean-Christophe PLAGNIOL-VILLARD * o LSC = Link Status Change 4692439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IMS_ENABLE_MASK ( \ 4712439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_RXT0 | \ 4722439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_TXDW | \ 4732439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_RXDMT0 | \ 4742439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_RXSEQ | \ 4752439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_IMS_LSC) 4762439e4bfSJean-Christophe PLAGNIOL-VILLARD 4772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of high/low register pairs in the RAR. The RAR (Receive Address 4782439e4bfSJean-Christophe PLAGNIOL-VILLARD * Registers) holds the directed and multicast addresses that we monitor. We 4792439e4bfSJean-Christophe PLAGNIOL-VILLARD * reserve one of these spots for our directed address, allowing us room for 4802439e4bfSJean-Christophe PLAGNIOL-VILLARD * E1000_RAR_ENTRIES - 1 multicast addresses. 4812439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 4822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RAR_ENTRIES 16 4832439e4bfSJean-Christophe PLAGNIOL-VILLARD 4842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MIN_NUMBER_OF_DESCRIPTORS 8 4852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 4862439e4bfSJean-Christophe PLAGNIOL-VILLARD 4872439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Descriptor */ 4882439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_rx_desc { 4892439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 4902439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t length; /* Length of data DMAed into data buffer */ 4912439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t csum; /* Packet checksum */ 4922439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t status; /* Descriptor status */ 4932439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t errors; /* Descriptor Errors */ 4942439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t special; 4952439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 4962439e4bfSJean-Christophe PLAGNIOL-VILLARD 4972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Decriptor bit definitions */ 4982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 4992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 5002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 5012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 5022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 5032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 5042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 5052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 5062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 5072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 5082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 5092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 5102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 5112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 5122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 5132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 5142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 5152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 5162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ 5172439e4bfSJean-Christophe PLAGNIOL-VILLARD 5182439e4bfSJean-Christophe PLAGNIOL-VILLARD /* mask to determine if packets should be dropped due to frame errors */ 5192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 5202439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_RXD_ERR_CE | \ 5212439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_RXD_ERR_SE | \ 5222439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_RXD_ERR_SEQ | \ 5232439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_RXD_ERR_CXE | \ 5242439e4bfSJean-Christophe PLAGNIOL-VILLARD E1000_RXD_ERR_RXE) 5252439e4bfSJean-Christophe PLAGNIOL-VILLARD 5262439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Descriptor */ 5272439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_tx_desc { 5282439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 5292439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 5302439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t data; 5312439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 5322439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t length; /* Data buffer length */ 5332439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t cso; /* Checksum offset */ 5342439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t cmd; /* Descriptor control */ 5352439e4bfSJean-Christophe PLAGNIOL-VILLARD } flags; 5362439e4bfSJean-Christophe PLAGNIOL-VILLARD } lower; 5372439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 5382439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t data; 5392439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 5402439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t status; /* Descriptor status */ 5412439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t css; /* Checksum start */ 5422439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t special; 5432439e4bfSJean-Christophe PLAGNIOL-VILLARD } fields; 5442439e4bfSJean-Christophe PLAGNIOL-VILLARD } upper; 5452439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 5462439e4bfSJean-Christophe PLAGNIOL-VILLARD 5472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Descriptor bit definitions */ 5482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 5492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 5502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 5512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 5522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 5532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 5542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 5552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 5562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 5572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 5582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 5592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 5602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 5612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 5622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 5632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 5642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 5652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 5662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 5672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 5682439e4bfSJean-Christophe PLAGNIOL-VILLARD 5692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Offload Context Descriptor */ 5702439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_context_desc { 5712439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 5722439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t ip_config; 5732439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 5742439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t ipcss; /* IP checksum start */ 5752439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t ipcso; /* IP checksum offset */ 5762439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t ipcse; /* IP checksum end */ 5772439e4bfSJean-Christophe PLAGNIOL-VILLARD } ip_fields; 5782439e4bfSJean-Christophe PLAGNIOL-VILLARD } lower_setup; 5792439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 5802439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t tcp_config; 5812439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 5822439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t tucss; /* TCP checksum start */ 5832439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t tucso; /* TCP checksum offset */ 5842439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t tucse; /* TCP checksum end */ 5852439e4bfSJean-Christophe PLAGNIOL-VILLARD } tcp_fields; 5862439e4bfSJean-Christophe PLAGNIOL-VILLARD } upper_setup; 5872439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t cmd_and_length; /* */ 5882439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 5892439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t data; 5902439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 5912439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t status; /* Descriptor status */ 5922439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t hdr_len; /* Header length */ 5932439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t mss; /* Maximum segment size */ 5942439e4bfSJean-Christophe PLAGNIOL-VILLARD } fields; 5952439e4bfSJean-Christophe PLAGNIOL-VILLARD } tcp_seg_setup; 5962439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 5972439e4bfSJean-Christophe PLAGNIOL-VILLARD 5982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Offload data descriptor */ 5992439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_data_desc { 6002439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 6012439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 6022439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t data; 6032439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 6042439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t length; /* Data buffer length */ 6052439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t typ_len_ext; /* */ 6062439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t cmd; /* */ 6072439e4bfSJean-Christophe PLAGNIOL-VILLARD } flags; 6082439e4bfSJean-Christophe PLAGNIOL-VILLARD } lower; 6092439e4bfSJean-Christophe PLAGNIOL-VILLARD union { 6102439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t data; 6112439e4bfSJean-Christophe PLAGNIOL-VILLARD struct { 6122439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t status; /* Descriptor status */ 6132439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t popts; /* Packet Options */ 6142439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t special; /* */ 6152439e4bfSJean-Christophe PLAGNIOL-VILLARD } fields; 6162439e4bfSJean-Christophe PLAGNIOL-VILLARD } upper; 6172439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6182439e4bfSJean-Christophe PLAGNIOL-VILLARD 6192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Filters */ 6202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 6212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 6222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 6232439e4bfSJean-Christophe PLAGNIOL-VILLARD 6242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Address Register */ 6252439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_rar { 6262439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t low; /* receive address low */ 6272439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t high; /* receive address high */ 6282439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6292439e4bfSJean-Christophe PLAGNIOL-VILLARD 6302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of entries in the Multicast Table Array (MTA). */ 6312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_NUM_MTA_REGISTERS 128 6322439e4bfSJean-Christophe PLAGNIOL-VILLARD 6332439e4bfSJean-Christophe PLAGNIOL-VILLARD /* IPv4 Address Table Entry */ 6342439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_ipv4_at_entry { 6352439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t ipv4_addr; /* IP Address (RW) */ 6362439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t reserved; 6372439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6382439e4bfSJean-Christophe PLAGNIOL-VILLARD 6392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Four wakeup IP addresses are supported */ 6402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 6412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 6422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IP6AT_SIZE 1 6432439e4bfSJean-Christophe PLAGNIOL-VILLARD 6442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* IPv6 Address Table Entry */ 6452439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_ipv6_at_entry { 6462439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint8_t ipv6_addr[16]; 6472439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6482439e4bfSJean-Christophe PLAGNIOL-VILLARD 6492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flexible Filter Length Table Entry */ 6502439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_fflt_entry { 6512439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t length; /* Flexible Filter Length (RW) */ 6522439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t reserved; 6532439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6542439e4bfSJean-Christophe PLAGNIOL-VILLARD 6552439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flexible Filter Mask Table Entry */ 6562439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_ffmt_entry { 6572439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 6582439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t reserved; 6592439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6602439e4bfSJean-Christophe PLAGNIOL-VILLARD 6612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flexible Filter Value Table Entry */ 6622439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_ffvt_entry { 6632439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t value; /* Flexible Filter Value (RW) */ 6642439e4bfSJean-Christophe PLAGNIOL-VILLARD volatile uint32_t reserved; 6652439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6662439e4bfSJean-Christophe PLAGNIOL-VILLARD 6672439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Four Flexible Filters are supported */ 6682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 6692439e4bfSJean-Christophe PLAGNIOL-VILLARD 6702439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 6712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 6722439e4bfSJean-Christophe PLAGNIOL-VILLARD 6732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 6742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 6752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 6762439e4bfSJean-Christophe PLAGNIOL-VILLARD 6772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Register Set. (82543, 82544) 6782439e4bfSJean-Christophe PLAGNIOL-VILLARD * 6792439e4bfSJean-Christophe PLAGNIOL-VILLARD * Registers are defined to be 32 bits and should be accessed as 32 bit values. 6802439e4bfSJean-Christophe PLAGNIOL-VILLARD * These registers are physically located on the NIC, but are mapped into the 6812439e4bfSJean-Christophe PLAGNIOL-VILLARD * host memory address space. 6822439e4bfSJean-Christophe PLAGNIOL-VILLARD * 6832439e4bfSJean-Christophe PLAGNIOL-VILLARD * RW - register is both readable and writable 6842439e4bfSJean-Christophe PLAGNIOL-VILLARD * RO - register is read only 6852439e4bfSJean-Christophe PLAGNIOL-VILLARD * WO - register is write only 6862439e4bfSJean-Christophe PLAGNIOL-VILLARD * R/clr - register is read only and is cleared when read 6872439e4bfSJean-Christophe PLAGNIOL-VILLARD * A - register array 6882439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL 0x00000 /* Device Control - RW */ 6902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS 0x00008 /* Device Status - RO */ 6912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 69295186063SMarek Vasut #define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */ 6932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 69495186063SMarek Vasut #define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */ 6952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 6962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC 0x00020 /* MDI Control - RW */ 6972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 6982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 6992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 7002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 7012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 7022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 7032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 7042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 7052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 70695186063SMarek Vasut #define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */ 7072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL 0x00100 /* RX Control - RW */ 7082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 7092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 7102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 7112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL 0x00400 /* TX Control - RW */ 712aa070789SRoy Zang #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 7132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 7142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 7152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 7162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 717aa070789SRoy Zang #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 718aa070789SRoy Zang #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 719aa070789SRoy Zang #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 72095186063SMarek Vasut #define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */ 721aa070789SRoy Zang #define FEXTNVM_SW_CONFIG 0x0001 7222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 723aa070789SRoy Zang #define E1000_PBS 0x01008 /* Packet Buffer Size */ 724aa070789SRoy Zang #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 72595186063SMarek Vasut #define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */ 726aa070789SRoy Zang #define E1000_FLASH_UPDATES 1000 727aa070789SRoy Zang #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 728aa070789SRoy Zang #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 729aa070789SRoy Zang #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 73095186063SMarek Vasut #define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */ 731aa070789SRoy Zang #define E1000_FLSWCTL 0x01030 /* FLASH control register */ 732aa070789SRoy Zang #define E1000_FLSWDATA 0x01034 /* FLASH data register */ 733aa070789SRoy Zang #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 734aa070789SRoy Zang #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 735aa070789SRoy Zang #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 7362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 7372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 7382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 7392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 7402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 7412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 7422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 7432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 7442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 7452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 7462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 7472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 748aa070789SRoy Zang #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 749aa070789SRoy Zang #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 750aa070789SRoy Zang #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 751aa070789SRoy Zang #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 752aa070789SRoy Zang #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 7532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 7542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 7552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 7562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 7572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 7582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 7592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 7602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 7612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 762aa070789SRoy Zang #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 763aa070789SRoy Zang #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 764aa070789SRoy Zang #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 765aa070789SRoy Zang #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 766aa070789SRoy Zang #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 767aa070789SRoy Zang #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 768aa070789SRoy Zang #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 769aa070789SRoy Zang #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 7702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 7712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 7722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 7732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 7742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 7752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 7762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 7772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 7782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 7792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 7802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_DC 0x04030 /* Defer Count - R/clr */ 7812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 7822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 7832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 7842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 7852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 7862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 7872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 7882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 7892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 7902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 7912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 7922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 7932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 7942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 7952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 7962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 7972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 7982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 7992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 8002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 8012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 8022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 8032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 8042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 8052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 8062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 8072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 8082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 8092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 8102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 8112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 8122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 8132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 8142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 8152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 8162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 8172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 8182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 8192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 8202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 8212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 8222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 8232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 8242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 8252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 8262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 8272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 8282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 8292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 8302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RA 0x05400 /* Receive Address - RW Array */ 8312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 8322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 8332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 8342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 8352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC 0x05820 /* Management Control - RW */ 8362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 8372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 8382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 8392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 8402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 8412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 8422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 8432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 8442439e4bfSJean-Christophe PLAGNIOL-VILLARD 8452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Register Set (82542) 8462439e4bfSJean-Christophe PLAGNIOL-VILLARD * 8472439e4bfSJean-Christophe PLAGNIOL-VILLARD * Some of the 82542 registers are located at different offsets than they are 8482439e4bfSJean-Christophe PLAGNIOL-VILLARD * in more current versions of the 8254x. Despite the difference in location, 8492439e4bfSJean-Christophe PLAGNIOL-VILLARD * the registers function in the same manner. 8502439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 8512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_CTRL E1000_CTRL 8522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_STATUS E1000_STATUS 8532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_EECD E1000_EECD 8542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_EERD E1000_EERD 8552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_CTRL_EXT E1000_CTRL_EXT 8562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MDIC E1000_MDIC 8572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCAL E1000_FCAL 8582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCAH E1000_FCAH 8592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCT E1000_FCT 8602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_VET E1000_VET 8612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RA 0x00040 8622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_ICR E1000_ICR 8632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_ITR E1000_ITR 8642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_ICS E1000_ICS 8652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_IMS E1000_IMS 8662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_IMC E1000_IMC 8672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RCTL E1000_RCTL 8682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RDTR 0x00108 8692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RDBAL 0x00110 8702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RDBAH 0x00114 8712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RDLEN 0x00118 8722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RDH 0x00120 8732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RDT 0x00128 8742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCRTH 0x00160 8752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCRTL 0x00168 8762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCTTV E1000_FCTTV 8772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TXCW E1000_TXCW 8782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RXCW E1000_RXCW 8792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MTA 0x00200 8802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TCTL E1000_TCTL 8812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TIPG E1000_TIPG 8822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TDBAL 0x00420 8832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TDBAH 0x00424 8842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TDLEN 0x00428 8852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TDH 0x00430 8862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TDT 0x00438 8872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TIDV 0x00440 8882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TBT E1000_TBT 8892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_AIT E1000_AIT 8902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_VFTA 0x00600 8912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_LEDCTL E1000_LEDCTL 8922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PBA E1000_PBA 8932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RXDCTL E1000_RXDCTL 8942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RADV E1000_RADV 8952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RSRPD E1000_RSRPD 8962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TXDMAC E1000_TXDMAC 8972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TXDCTL E1000_TXDCTL 8982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TADV E1000_TADV 8992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TSPMT E1000_TSPMT 9002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_CRCERRS E1000_CRCERRS 9012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_ALGNERRC E1000_ALGNERRC 9022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_SYMERRS E1000_SYMERRS 9032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RXERRC E1000_RXERRC 9042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MPC E1000_MPC 9052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_SCC E1000_SCC 9062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_ECOL E1000_ECOL 9072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MCC E1000_MCC 9082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_LATECOL E1000_LATECOL 9092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_COLC E1000_COLC 9102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_DC E1000_DC 9112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TNCRS E1000_TNCRS 9122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_SEC E1000_SEC 9132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_CEXTERR E1000_CEXTERR 9142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RLEC E1000_RLEC 9152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_XONRXC E1000_XONRXC 9162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_XONTXC E1000_XONTXC 9172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_XOFFRXC E1000_XOFFRXC 9182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_XOFFTXC E1000_XOFFTXC 9192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FCRUC E1000_FCRUC 9202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PRC64 E1000_PRC64 9212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PRC127 E1000_PRC127 9222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PRC255 E1000_PRC255 9232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PRC511 E1000_PRC511 9242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PRC1023 E1000_PRC1023 9252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PRC1522 E1000_PRC1522 9262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_GPRC E1000_GPRC 9272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_BPRC E1000_BPRC 9282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MPRC E1000_MPRC 9292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_GPTC E1000_GPTC 9302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_GORCL E1000_GORCL 9312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_GORCH E1000_GORCH 9322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_GOTCL E1000_GOTCL 9332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_GOTCH E1000_GOTCH 9342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RNBC E1000_RNBC 9352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RUC E1000_RUC 9362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RFC E1000_RFC 9372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_ROC E1000_ROC 9382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RJC E1000_RJC 9392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MGTPRC E1000_MGTPRC 9402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MGTPDC E1000_MGTPDC 9412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MGTPTC E1000_MGTPTC 9422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TORL E1000_TORL 9432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TORH E1000_TORH 9442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TOTL E1000_TOTL 9452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TOTH E1000_TOTH 9462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TPR E1000_TPR 9472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TPT E1000_TPT 9482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PTC64 E1000_PTC64 9492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PTC127 E1000_PTC127 9502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PTC255 E1000_PTC255 9512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PTC511 E1000_PTC511 9522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PTC1023 E1000_PTC1023 9532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_PTC1522 E1000_PTC1522 9542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MPTC E1000_MPTC 9552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_BPTC E1000_BPTC 9562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TSCTC E1000_TSCTC 9572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_TSCTFC E1000_TSCTFC 9582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_RXCSUM E1000_RXCSUM 9592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_WUC E1000_WUC 9602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_WUFC E1000_WUFC 9612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_WUS E1000_WUS 9622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_MANC E1000_MANC 9632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_IPAV E1000_IPAV 9642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_IP4AT E1000_IP4AT 9652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_IP6AT E1000_IP6AT 9662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_WUPL E1000_WUPL 9672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_WUPM E1000_WUPM 9682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FFLT E1000_FFLT 9692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FFMT E1000_FFMT 9702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_82542_FFVT E1000_FFVT 9712439e4bfSJean-Christophe PLAGNIOL-VILLARD 9722439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Statistics counters collected by the MAC */ 9732439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw_stats { 9742439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t crcerrs; 9752439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t algnerrc; 9762439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t symerrs; 9772439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t rxerrc; 9782439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mpc; 9792439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t scc; 9802439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ecol; 9812439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mcc; 9822439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t latecol; 9832439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t colc; 9842439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t dc; 9852439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t tncrs; 9862439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t sec; 9872439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t cexterr; 9882439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t rlec; 9892439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t xonrxc; 9902439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t xontxc; 9912439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t xoffrxc; 9922439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t xofftxc; 9932439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t fcruc; 9942439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t prc64; 9952439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t prc127; 9962439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t prc255; 9972439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t prc511; 9982439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t prc1023; 9992439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t prc1522; 10002439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t gprc; 10012439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t bprc; 10022439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mprc; 10032439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t gptc; 10042439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t gorcl; 10052439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t gorch; 10062439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t gotcl; 10072439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t gotch; 10082439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t rnbc; 10092439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ruc; 10102439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t rfc; 10112439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t roc; 10122439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t rjc; 10132439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mgprc; 10142439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mgpdc; 10152439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mgptc; 10162439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t torl; 10172439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t torh; 10182439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t totl; 10192439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t toth; 10202439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t tpr; 10212439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t tpt; 10222439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ptc64; 10232439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ptc127; 10242439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ptc255; 10252439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ptc511; 10262439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ptc1023; 10272439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t ptc1522; 10282439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t mptc; 10292439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t bptc; 10302439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t tsctc; 10312439e4bfSJean-Christophe PLAGNIOL-VILLARD uint64_t tsctfc; 10322439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 10332439e4bfSJean-Christophe PLAGNIOL-VILLARD 10348712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1035aa070789SRoy Zang struct e1000_eeprom_info { 1036aa070789SRoy Zang e1000_eeprom_type type; 1037aa070789SRoy Zang uint16_t word_size; 1038aa070789SRoy Zang uint16_t opcode_bits; 1039aa070789SRoy Zang uint16_t address_bits; 1040aa070789SRoy Zang uint16_t delay_usec; 1041aa070789SRoy Zang uint16_t page_size; 1042472d5460SYork Sun bool use_eerd; 1043472d5460SYork Sun bool use_eewr; 1044aa070789SRoy Zang }; 10458712adfdSRojhalat Ibrahim #endif 1046aa070789SRoy Zang 1047aa070789SRoy Zang typedef enum { 1048aa070789SRoy Zang e1000_smart_speed_default = 0, 1049aa070789SRoy Zang e1000_smart_speed_on, 1050aa070789SRoy Zang e1000_smart_speed_off 1051aa070789SRoy Zang } e1000_smart_speed; 1052aa070789SRoy Zang 1053aa070789SRoy Zang typedef enum { 1054aa070789SRoy Zang e1000_dsp_config_disabled = 0, 1055aa070789SRoy Zang e1000_dsp_config_enabled, 1056aa070789SRoy Zang e1000_dsp_config_activated, 1057aa070789SRoy Zang e1000_dsp_config_undefined = 0xFF 1058aa070789SRoy Zang } e1000_dsp_config; 1059aa070789SRoy Zang 1060aa070789SRoy Zang typedef enum { 1061aa070789SRoy Zang e1000_ms_hw_default = 0, 1062aa070789SRoy Zang e1000_ms_force_master, 1063aa070789SRoy Zang e1000_ms_force_slave, 1064aa070789SRoy Zang e1000_ms_auto 1065aa070789SRoy Zang } e1000_ms_type; 1066aa070789SRoy Zang 1067aa070789SRoy Zang typedef enum { 1068aa070789SRoy Zang e1000_ffe_config_enabled = 0, 1069aa070789SRoy Zang e1000_ffe_config_active, 1070aa070789SRoy Zang e1000_ffe_config_blocked 1071aa070789SRoy Zang } e1000_ffe_config; 1072aa070789SRoy Zang 1073aa070789SRoy Zang 10742439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Structure containing variables used by the shared code (e1000_hw.c) */ 10752439e4bfSJean-Christophe PLAGNIOL-VILLARD struct e1000_hw { 10765c5e707aSSimon Glass const char *name; 1077ce5207e1SKyle Moffett struct list_head list_node; 1078c6d80a15SSimon Glass #ifndef CONFIG_DM_ETH 1079d60626f8SKyle Moffett struct eth_device *nic; 1080c6d80a15SSimon Glass #endif 1081ce5207e1SKyle Moffett #ifdef CONFIG_E1000_SPI 1082ce5207e1SKyle Moffett struct spi_slave spi; 1083ce5207e1SKyle Moffett #endif 1084d60626f8SKyle Moffett unsigned int cardnum; 1085d60626f8SKyle Moffett 108681dab9afSBin Meng #ifdef CONFIG_DM_ETH 108781dab9afSBin Meng struct udevice *pdev; 108881dab9afSBin Meng #else 10892439e4bfSJean-Christophe PLAGNIOL-VILLARD pci_dev_t pdev; 109081dab9afSBin Meng #endif 10912439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t *hw_addr; 10922439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_mac_type mac_type; 1093ac3315c2SAndre Schwarz e1000_phy_type phy_type; 1094ac3315c2SAndre Schwarz uint32_t phy_init_script; 1095aa070789SRoy Zang uint32_t txd_cmd; 10962439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_media_type media_type; 10972439e4bfSJean-Christophe PLAGNIOL-VILLARD e1000_fc_type fc; 1098aa070789SRoy Zang e1000_bus_type bus_type; 1099aa070789SRoy Zang uint32_t asf_firmware_present; 11008712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1101aa070789SRoy Zang uint32_t eeprom_semaphore_present; 11028712adfdSRojhalat Ibrahim #endif 1103aa070789SRoy Zang uint32_t swfw_sync_present; 1104aa070789SRoy Zang uint32_t swfwhw_semaphore_present; 11058712adfdSRojhalat Ibrahim #ifndef CONFIG_E1000_NO_NVM 1106aa070789SRoy Zang struct e1000_eeprom_info eeprom; 11078712adfdSRojhalat Ibrahim #endif 1108aa070789SRoy Zang e1000_ms_type master_slave; 1109aa070789SRoy Zang e1000_ms_type original_master_slave; 1110aa070789SRoy Zang e1000_ffe_config ffe_config_state; 11112439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t phy_id; 1112aa070789SRoy Zang uint32_t phy_revision; 11132439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t phy_addr; 11142439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t original_fc; 11152439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t txcw; 11162439e4bfSJean-Christophe PLAGNIOL-VILLARD uint32_t autoneg_failed; 11172439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t autoneg_advertised; 11182439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t pci_cmd_word; 11192439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t fc_high_water; 11202439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t fc_low_water; 11212439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t fc_pause_time; 11222439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t device_id; 11232439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t vendor_id; 11242439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t subsystem_id; 11252439e4bfSJean-Christophe PLAGNIOL-VILLARD uint16_t subsystem_vendor_id; 11262439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t revision_id; 11272439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t autoneg; 11282439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t mdix; 11292439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t forced_speed_duplex; 11302439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t wait_autoneg_complete; 11312439e4bfSJean-Christophe PLAGNIOL-VILLARD uint8_t dma_fairness; 1132472d5460SYork Sun bool disable_polarity_correction; 1133472d5460SYork Sun bool speed_downgraded; 1134472d5460SYork Sun bool get_link_status; 1135472d5460SYork Sun bool tbi_compatibility_en; 1136472d5460SYork Sun bool tbi_compatibility_on; 1137472d5460SYork Sun bool fc_strict_ieee; 1138472d5460SYork Sun bool fc_send_xon; 1139472d5460SYork Sun bool report_tx_early; 1140472d5460SYork Sun bool phy_reset_disable; 1141472d5460SYork Sun bool initialize_hw_bits_disable; 1142aa070789SRoy Zang e1000_smart_speed smart_speed; 1143aa070789SRoy Zang e1000_dsp_config dsp_config_state; 11442439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 11452439e4bfSJean-Christophe PLAGNIOL-VILLARD 11462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 11472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1148aa070789SRoy Zang #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM 1149aa070789SRoy Zang read/write registers */ 1150aa070789SRoy Zang #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1151aa070789SRoy Zang #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start 1152aa070789SRoy Zang operation */ 1153aa070789SRoy Zang #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1154aa070789SRoy Zang #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write 1155aa070789SRoy Zang complete */ 1156aa070789SRoy Zang #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ 1157aa070789SRoy Zang #define EEPROM_RESERVED_WORD 0xFFFF 11582439e4bfSJean-Christophe PLAGNIOL-VILLARD 11592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Register Bit Masks */ 11602439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Device Control */ 11612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 11622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 11632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 11642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 11652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 11662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 11672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 11682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 11692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 11702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 11712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 11722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 11732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 11742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 11752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 11762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 11772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 11782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 11792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 11802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 11812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 11822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 11832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 11842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 11852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_RST 0x04000000 /* Global reset */ 11862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 11872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 11882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 11892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 11902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 11912439e4bfSJean-Christophe PLAGNIOL-VILLARD 11922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Device Status */ 11932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 11942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 11952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 11962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 11972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 11982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 11992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 12002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_SPEED_MASK 0x000000C0 12012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 12022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 12032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 12042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 12052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 12062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 12072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 12082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 12092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 121095186063SMarek Vasut #define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */ 12112439e4bfSJean-Christophe PLAGNIOL-VILLARD 12122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Constants used to intrepret the masked PCI-X bus speed. */ 12132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 12142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 12152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 12162439e4bfSJean-Christophe PLAGNIOL-VILLARD 12172439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EEPROM/Flash Control */ 12182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 12192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 12202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 12212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 12222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_FWE_MASK 0x00000030 12232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 12242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 12252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_FWE_SHIFT 4 12262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 12272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 12282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 12292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1230aa070789SRoy Zang #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1231aa070789SRoy Zang * (0-small, 1-large) */ 1232aa070789SRoy Zang 1233aa070789SRoy Zang #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1234aa070789SRoy Zang #ifndef E1000_EEPROM_GRANT_ATTEMPTS 1235aa070789SRoy Zang #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1236aa070789SRoy Zang #endif 1237aa070789SRoy Zang #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1238aa070789SRoy Zang #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1239aa070789SRoy Zang #define E1000_EECD_SIZE_EX_SHIFT 11 1240aa070789SRoy Zang #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1241aa070789SRoy Zang #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1242aa070789SRoy Zang #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1243aa070789SRoy Zang #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1244f1bcad22SHannu Lounento #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 1245f1bcad22SHannu Lounento #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 1246f1bcad22SHannu Lounento #define E1000_FLUDONE_ATTEMPTS 20000 1247aa070789SRoy Zang #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1248aa070789SRoy Zang #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1249aa070789SRoy Zang #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1250aa070789SRoy Zang #define E1000_EECD_SECVAL_SHIFT 22 1251aa070789SRoy Zang #define E1000_STM_OPCODE 0xDB00 1252aa070789SRoy Zang #define E1000_HICR_FW_RESET 0xC0 1253aa070789SRoy Zang 1254aa070789SRoy Zang #define E1000_SHADOW_RAM_WORDS 2048 1255aa070789SRoy Zang #define E1000_ICH_NVM_SIG_WORD 0x13 1256aa070789SRoy Zang #define E1000_ICH_NVM_SIG_MASK 0xC0 12572439e4bfSJean-Christophe PLAGNIOL-VILLARD 12582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EEPROM Read */ 12592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD_START 0x00000001 /* Start Read */ 12602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD_DONE 0x00000010 /* Read Done */ 12612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD_ADDR_SHIFT 8 12622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 12632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD_DATA_SHIFT 16 12642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 12652439e4bfSJean-Christophe PLAGNIOL-VILLARD 1266aa070789SRoy Zang /* EEPROM Commands - Microwire */ 1267aa070789SRoy Zang #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 1268aa070789SRoy Zang #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 1269aa070789SRoy Zang #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 1270aa070789SRoy Zang #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 1271aa070789SRoy Zang #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 1272aa070789SRoy Zang 1273aa070789SRoy Zang /* EEPROM Commands - SPI */ 1274aa070789SRoy Zang #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1275aa070789SRoy Zang #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 1276aa070789SRoy Zang #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 1277aa070789SRoy Zang #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1278aa070789SRoy Zang #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 1279aa070789SRoy Zang #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 1280aa070789SRoy Zang #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 1281aa070789SRoy Zang #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 1282aa070789SRoy Zang #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 1283aa070789SRoy Zang #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 1284aa070789SRoy Zang #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 1285aa070789SRoy Zang 1286aa070789SRoy Zang /* EEPROM Size definitions */ 1287aa070789SRoy Zang #define EEPROM_WORD_SIZE_SHIFT 6 1288aa070789SRoy Zang #define EEPROM_SIZE_SHIFT 10 1289aa070789SRoy Zang #define EEPROM_SIZE_MASK 0x1C00 1290aa070789SRoy Zang 1291aa070789SRoy Zang /* EEPROM Word Offsets */ 1292aa070789SRoy Zang #define EEPROM_COMPAT 0x0003 1293aa070789SRoy Zang #define EEPROM_ID_LED_SETTINGS 0x0004 1294aa070789SRoy Zang #define EEPROM_VERSION 0x0005 1295aa070789SRoy Zang #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude 1296aa070789SRoy Zang adjustment. */ 1297aa070789SRoy Zang #define EEPROM_PHY_CLASS_WORD 0x0007 1298aa070789SRoy Zang #define EEPROM_INIT_CONTROL1_REG 0x000A 1299aa070789SRoy Zang #define EEPROM_INIT_CONTROL2_REG 0x000F 1300aa070789SRoy Zang #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 1301aa070789SRoy Zang #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 1302aa070789SRoy Zang #define EEPROM_INIT_3GIO_3 0x001A 1303aa070789SRoy Zang #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 1304aa070789SRoy Zang #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 1305aa070789SRoy Zang #define EEPROM_CFG 0x0012 1306aa070789SRoy Zang #define EEPROM_FLASH_VERSION 0x0032 1307aa070789SRoy Zang #define EEPROM_CHECKSUM_REG 0x003F 1308aa070789SRoy Zang 1309aa070789SRoy Zang #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 1310aa070789SRoy Zang #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 1311aa070789SRoy Zang 13122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Extended Device Control */ 13132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 13142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 13152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 13162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 13172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1318aa070789SRoy Zang #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable 1319aa070789SRoy Zang Pin 4 */ 1320aa070789SRoy Zang #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable 1321aa070789SRoy Zang Pin 5 */ 13222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 13232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 13242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ 13252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 13262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ 13272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 13282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 13292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 13302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ 13312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 13322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ 13332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 13342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 13352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 13362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1337aa070789SRoy Zang #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 13382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 13392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 13402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 13412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 13422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 13432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 13442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 13452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 13462439e4bfSJean-Christophe PLAGNIOL-VILLARD 13472439e4bfSJean-Christophe PLAGNIOL-VILLARD /* MDI Control */ 13482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_DATA_MASK 0x0000FFFF 13492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_REG_MASK 0x001F0000 13502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_REG_SHIFT 16 13512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_PHY_MASK 0x03E00000 13522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_PHY_SHIFT 21 13532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_OP_WRITE 0x04000000 13542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_OP_READ 0x08000000 13552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_READY 0x10000000 13562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_INT_EN 0x20000000 13572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDIC_ERROR 0x40000000 13582439e4bfSJean-Christophe PLAGNIOL-VILLARD 1359aa070789SRoy Zang #define E1000_PHY_CTRL_SPD_EN 0x00000001 1360aa070789SRoy Zang #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 1361aa070789SRoy Zang #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 1362aa070789SRoy Zang #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 1363aa070789SRoy Zang #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 1364aa070789SRoy Zang #define E1000_PHY_CTRL_B2B_EN 0x00000080 13652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* LED Control */ 13662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 13672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED0_MODE_SHIFT 0 13682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED0_IVRT 0x00000040 13692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED0_BLINK 0x00000080 13702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 13712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED1_MODE_SHIFT 8 13722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED1_IVRT 0x00004000 13732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED1_BLINK 0x00008000 13742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 13752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED2_MODE_SHIFT 16 13762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED2_IVRT 0x00400000 13772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED2_BLINK 0x00800000 13782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 13792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED3_MODE_SHIFT 24 13802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED3_IVRT 0x40000000 13812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_LED3_BLINK 0x80000000 13822439e4bfSJean-Christophe PLAGNIOL-VILLARD 13832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 13842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 13852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_UP 0x2 13862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_ACTIVITY 0x3 13872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 13882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_10 0x5 13892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_100 0x6 13902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LINK_1000 0x7 13912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 13922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 13932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_COLLISION 0xA 13942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 13952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 13962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_PAUSED 0xD 13972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LED_ON 0xE 13982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_LEDCTL_MODE_LED_OFF 0xF 13992439e4bfSJean-Christophe PLAGNIOL-VILLARD 14002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Address */ 14012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 14022439e4bfSJean-Christophe PLAGNIOL-VILLARD 14032439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Cause Read */ 14042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 14052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 14062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 14072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 14082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 14092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 14102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 14112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 14122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 14132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 14142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 14152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 14162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 14172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_TXD_LOW 0x00008000 14182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICR_SRPD 0x00010000 14192439e4bfSJean-Christophe PLAGNIOL-VILLARD 14202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Cause Set */ 14212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 14222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 14232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 14242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 14252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 14262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 14272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 14282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 14292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 14302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 14312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 14322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 14332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 14342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 14352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_ICS_SRPD E1000_ICR_SRPD 14362439e4bfSJean-Christophe PLAGNIOL-VILLARD 14372439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Mask Set */ 14382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 14392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 14402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 14412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 14422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 14432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 14442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 14452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 14462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 14472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 14482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 14492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 14502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 14512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 14522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMS_SRPD E1000_ICR_SRPD 14532439e4bfSJean-Christophe PLAGNIOL-VILLARD 14542439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Mask Clear */ 14552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 14562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 14572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 14582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 14592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 14602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 14612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 14622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 14632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 14642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 14652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 14662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 14672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 14682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 14692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_IMC_SRPD E1000_ICR_SRPD 14702439e4bfSJean-Christophe PLAGNIOL-VILLARD 14712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Control */ 14722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_RST 0x00000001 /* Software reset */ 14732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_EN 0x00000002 /* enable */ 14742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 14752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 14762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 14772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 14782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 14792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 14802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 14812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 14822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 14832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 14842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 14852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 14862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 14872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 14882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 14892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 14902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 14912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 14922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 14932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 14942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 14952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 14962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 14972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 14982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 14992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 15002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 15012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 15022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 15032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 15042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 15052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 15062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 15072439e4bfSJean-Christophe PLAGNIOL-VILLARD 1508aa070789SRoy Zang /* SW_W_SYNC definitions */ 1509aa070789SRoy Zang #define E1000_SWFW_EEP_SM 0x0001 1510aa070789SRoy Zang #define E1000_SWFW_PHY0_SM 0x0002 1511aa070789SRoy Zang #define E1000_SWFW_PHY1_SM 0x0004 1512aa070789SRoy Zang #define E1000_SWFW_MAC_CSR_SM 0x0008 1513aa070789SRoy Zang 15142439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Descriptor */ 15152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 15162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 15172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 15182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 15192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 15202439e4bfSJean-Christophe PLAGNIOL-VILLARD 15212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow Control */ 15222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 15232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 15242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 15252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 15262439e4bfSJean-Christophe PLAGNIOL-VILLARD 15272439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Descriptor Control */ 15282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 15292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 15302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 15312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1532776e66e8SRuchika Gupta #define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 15332439e4bfSJean-Christophe PLAGNIOL-VILLARD 15342439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Descriptor Control */ 1535aa070789SRoy Zang #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1536aa070789SRoy Zang #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1537aa070789SRoy Zang #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 15382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 15392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 15402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1541aa070789SRoy Zang #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 1542aa070789SRoy Zang still to be processed. */ 15432439e4bfSJean-Christophe PLAGNIOL-VILLARD 15442439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Configuration Word */ 15452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 15462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 15472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 15482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 15492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 15502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 15512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 15522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 15532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 15542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 15552439e4bfSJean-Christophe PLAGNIOL-VILLARD 15562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Configuration Word */ 15572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 15582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 15592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 15602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 15612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_C 0x20000000 /* Receive config */ 15622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 15632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 15642439e4bfSJean-Christophe PLAGNIOL-VILLARD 15652439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Control */ 15662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_RST 0x00000001 /* software reset */ 15672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_EN 0x00000002 /* enable tx */ 15682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 15692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 15702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 15712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 15722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 15732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 15742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 15752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1576aa070789SRoy Zang #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 15772439e4bfSJean-Christophe PLAGNIOL-VILLARD 15782439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Checksum Control */ 15792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 15802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 15812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 15822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 15832439e4bfSJean-Christophe PLAGNIOL-VILLARD 15842439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Definitions for power management and wakeup registers */ 15852439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wake Up Control */ 15862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUC_APME 0x00000001 /* APM Enable */ 15872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 15882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 15892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 15902439e4bfSJean-Christophe PLAGNIOL-VILLARD 15912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wake Up Filter Control */ 15922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 15932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 15942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 15952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 15962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 15972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 15982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 15992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 16002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 16012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 16022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 16032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 16042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 16052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 16062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 16072439e4bfSJean-Christophe PLAGNIOL-VILLARD 16082439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wake Up Status */ 16092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 16102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 16112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 16122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 16132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 16142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 16152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 16162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 16172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 16182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 16192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 16202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 16212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 16222439e4bfSJean-Christophe PLAGNIOL-VILLARD 16232439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Management Control */ 16242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 16252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 16262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 16272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 16282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 16292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 16302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 16312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 16322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 16332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 16342439e4bfSJean-Christophe PLAGNIOL-VILLARD * Filtering */ 16352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 16362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 16372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 16382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 16392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 16402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 16412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 16422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 16432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 16442439e4bfSJean-Christophe PLAGNIOL-VILLARD 16452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 16462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 16472439e4bfSJean-Christophe PLAGNIOL-VILLARD 16482439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Wake Up Packet Length */ 16492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 16502439e4bfSJean-Christophe PLAGNIOL-VILLARD 16512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_MDALIGN 4096 16522439e4bfSJean-Christophe PLAGNIOL-VILLARD 16532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EEPROM Commands */ 16542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ 16552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ 16562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ 16572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ 16582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ 16592439e4bfSJean-Christophe PLAGNIOL-VILLARD 16602439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Word definitions for ID LED Settings */ 16612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_RESERVED_0000 0x0000 16622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_RESERVED_FFFF 0xFFFF 16632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 16642439e4bfSJean-Christophe PLAGNIOL-VILLARD (ID_LED_OFF1_OFF2 << 8) | \ 16652439e4bfSJean-Christophe PLAGNIOL-VILLARD (ID_LED_DEF1_DEF2 << 4) | \ 16662439e4bfSJean-Christophe PLAGNIOL-VILLARD (ID_LED_DEF1_DEF2)) 16672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_DEF1_DEF2 0x1 16682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_DEF1_ON2 0x2 16692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_DEF1_OFF2 0x3 16702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_ON1_DEF2 0x4 16712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_ON1_ON2 0x5 16722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_ON1_OFF2 0x6 16732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_OFF1_DEF2 0x7 16742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_OFF1_ON2 0x8 16752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ID_LED_OFF1_OFF2 0x9 16762439e4bfSJean-Christophe PLAGNIOL-VILLARD 16772439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Mask bits for fields in Word 0x03 of the EEPROM */ 16782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_COMPAT_SERVER 0x0400 16792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_COMPAT_CLIENT 0x0200 16802439e4bfSJean-Christophe PLAGNIOL-VILLARD 16812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Mask bits for fields in Word 0x0a of the EEPROM */ 16822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0A_ILOS 0x0010 16832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0A_SWDPIO 0x01E0 16842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0A_LRST 0x0200 16852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0A_FD 0x0400 16862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0A_66MHZ 0x0800 16872439e4bfSJean-Christophe PLAGNIOL-VILLARD 16882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Mask bits for fields in Word 0x0f of the EEPROM */ 16892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0F_PAUSE_MASK 0x3000 16902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0F_PAUSE 0x1000 16912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0F_ASM_DIR 0x2000 16922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0F_ANE 0x0800 16932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 16942439e4bfSJean-Christophe PLAGNIOL-VILLARD 16952439e4bfSJean-Christophe PLAGNIOL-VILLARD /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 16962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_SUM 0xBABA 16972439e4bfSJean-Christophe PLAGNIOL-VILLARD 16982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EEPROM Map defines (WORD OFFSETS)*/ 16992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_NODE_ADDRESS_BYTE_0 0 17002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EEPROM_PBA_BYTE_1 8 17012439e4bfSJean-Christophe PLAGNIOL-VILLARD 17022439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EEPROM Map Sizes (Byte Counts) */ 17032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PBA_SIZE 4 17042439e4bfSJean-Christophe PLAGNIOL-VILLARD 17052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Collision related configuration parameters */ 1706aa070789SRoy Zang #define E1000_COLLISION_THRESHOLD 0xF 17072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CT_SHIFT 4 1708aa070789SRoy Zang #define E1000_COLLISION_DISTANCE 63 1709aa070789SRoy Zang #define E1000_COLLISION_DISTANCE_82542 64 17102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 17112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 17122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_GB_HDX_COLLISION_DISTANCE 512 17132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_COLD_SHIFT 12 17142439e4bfSJean-Christophe PLAGNIOL-VILLARD 17152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of Transmit and Receive Descriptors must be a multiple of 8 */ 17162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define REQ_TX_DESCRIPTOR_MULTIPLE 8 17172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define REQ_RX_DESCRIPTOR_MULTIPLE 8 17182439e4bfSJean-Christophe PLAGNIOL-VILLARD 17192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Default values for the transmit IPG register */ 17202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82542_TIPG_IPGT 10 17212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82543_TIPG_IPGT_FIBER 9 17222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82543_TIPG_IPGT_COPPER 8 17232439e4bfSJean-Christophe PLAGNIOL-VILLARD 17242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIPG_IPGT_MASK 0x000003FF 17252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIPG_IPGR1_MASK 0x000FFC00 17262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIPG_IPGR2_MASK 0x3FF00000 17272439e4bfSJean-Christophe PLAGNIOL-VILLARD 17282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82542_TIPG_IPGR1 2 17292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82543_TIPG_IPGR1 8 17302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIPG_IPGR1_SHIFT 10 17312439e4bfSJean-Christophe PLAGNIOL-VILLARD 17322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82542_TIPG_IPGR2 10 17332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEFAULT_82543_TIPG_IPGR2 6 1734aa070789SRoy Zang #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 17352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TIPG_IPGR2_SHIFT 20 17362439e4bfSJean-Christophe PLAGNIOL-VILLARD 17372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TXDMAC_DPP 0x00000001 17382439e4bfSJean-Christophe PLAGNIOL-VILLARD 17392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Adaptive IFS defines */ 17402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TX_THRESHOLD_START 8 17412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TX_THRESHOLD_INCREMENT 10 17422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TX_THRESHOLD_DECREMENT 1 17432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TX_THRESHOLD_STOP 190 17442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TX_THRESHOLD_DISABLE 0 17452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TX_THRESHOLD_TIMER_MS 10000 17462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MIN_NUM_XMITS 1000 17472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IFS_MAX 80 17482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IFS_STEP 10 17492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IFS_MIN 40 17502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IFS_RATIO 4 17512439e4bfSJean-Christophe PLAGNIOL-VILLARD 17522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PBA constants */ 17532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 17542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PBA_24K 0x0018 1755aa070789SRoy Zang #define E1000_PBA_38K 0x0026 17562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PBA_40K 0x0028 17572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 17582439e4bfSJean-Christophe PLAGNIOL-VILLARD 17592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow Control Constants */ 17602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 17612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 17622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FLOW_CONTROL_TYPE 0x8808 17632439e4bfSJean-Christophe PLAGNIOL-VILLARD 17642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The historical defaults for the flow control values are given below. */ 17652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 17662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 17672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 17682439e4bfSJean-Christophe PLAGNIOL-VILLARD 17692439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow Control High-Watermark: 43464 bytes */ 17702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FC_HIGH_THRESH 0xA9C8 17712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow Control Low-Watermark: 43456 bytes */ 17722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FC_LOW_THRESH 0xA9C0 17732439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Flow Control Pause Time: 858 usec */ 17742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_FC_PAUSE_TIME 0x0680 17752439e4bfSJean-Christophe PLAGNIOL-VILLARD 17762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PCIX Config space */ 17772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_COMMAND_REGISTER 0xE6 17782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_STATUS_REGISTER_LO 0xE8 17792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_STATUS_REGISTER_HI 0xEA 17802439e4bfSJean-Christophe PLAGNIOL-VILLARD 17812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_COMMAND_MMRBC_MASK 0x000C 17822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_COMMAND_MMRBC_SHIFT 0x2 17832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 17842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 17852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_STATUS_HI_MMRBC_4K 0x3 17862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PCIX_STATUS_HI_MMRBC_2K 0x2 17872439e4bfSJean-Christophe PLAGNIOL-VILLARD 17882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of bits that we need to shift right to move the "pause" 17892439e4bfSJean-Christophe PLAGNIOL-VILLARD * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field 17902439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the TXCW register 17912439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 17922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PAUSE_SHIFT 5 17932439e4bfSJean-Christophe PLAGNIOL-VILLARD 17942439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of bits that we need to shift left to move the "SWDPIO" 17952439e4bfSJean-Christophe PLAGNIOL-VILLARD * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field 17962439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the CTRL register 17972439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 17982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SWDPIO_SHIFT 17 17992439e4bfSJean-Christophe PLAGNIOL-VILLARD 18002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of bits that we need to shift left to move the "SWDPIO_EXT" 18012439e4bfSJean-Christophe PLAGNIOL-VILLARD * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The 18022439e4bfSJean-Christophe PLAGNIOL-VILLARD * Extended CTRL register. 18032439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the CTRL register 18042439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 18052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SWDPIO__EXT_SHIFT 4 18062439e4bfSJean-Christophe PLAGNIOL-VILLARD 18072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of bits that we need to shift left to move the "ILOS" 18082439e4bfSJean-Christophe PLAGNIOL-VILLARD * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field 18092439e4bfSJean-Christophe PLAGNIOL-VILLARD * in the CTRL register 18102439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 18112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ILOS_SHIFT 3 18122439e4bfSJean-Christophe PLAGNIOL-VILLARD 18132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RECEIVE_BUFFER_ALIGN_SIZE (256) 18142439e4bfSJean-Christophe PLAGNIOL-VILLARD 18152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The number of milliseconds we wait for auto-negotiation to complete */ 18162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LINK_UP_TIMEOUT 500 18172439e4bfSJean-Christophe PLAGNIOL-VILLARD 18182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 18192439e4bfSJean-Christophe PLAGNIOL-VILLARD 18202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* The carrier extension symbol, as received by the NIC. */ 18212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CARRIER_EXTENSION 0x0F 18222439e4bfSJean-Christophe PLAGNIOL-VILLARD 18232439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TBI_ACCEPT macro definition: 18242439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18252439e4bfSJean-Christophe PLAGNIOL-VILLARD * This macro requires: 18262439e4bfSJean-Christophe PLAGNIOL-VILLARD * adapter = a pointer to struct e1000_hw 18272439e4bfSJean-Christophe PLAGNIOL-VILLARD * status = the 8 bit status field of the RX descriptor with EOP set 18282439e4bfSJean-Christophe PLAGNIOL-VILLARD * error = the 8 bit error field of the RX descriptor with EOP set 18292439e4bfSJean-Christophe PLAGNIOL-VILLARD * length = the sum of all the length fields of the RX descriptors that 18302439e4bfSJean-Christophe PLAGNIOL-VILLARD * make up the current frame 18312439e4bfSJean-Christophe PLAGNIOL-VILLARD * last_byte = the last byte of the frame DMAed by the hardware 18322439e4bfSJean-Christophe PLAGNIOL-VILLARD * max_frame_length = the maximum frame length we want to accept. 18332439e4bfSJean-Christophe PLAGNIOL-VILLARD * min_frame_length = the minimum frame length we want to accept. 18342439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18352439e4bfSJean-Christophe PLAGNIOL-VILLARD * This macro is a conditional that should be used in the interrupt 18362439e4bfSJean-Christophe PLAGNIOL-VILLARD * handler's Rx processing routine when RxErrors have been detected. 18372439e4bfSJean-Christophe PLAGNIOL-VILLARD * 18382439e4bfSJean-Christophe PLAGNIOL-VILLARD * Typical use: 18392439e4bfSJean-Christophe PLAGNIOL-VILLARD * ... 18402439e4bfSJean-Christophe PLAGNIOL-VILLARD * if (TBI_ACCEPT) { 1841472d5460SYork Sun * accept_frame = true; 18422439e4bfSJean-Christophe PLAGNIOL-VILLARD * e1000_tbi_adjust_stats(adapter, MacAddress); 18432439e4bfSJean-Christophe PLAGNIOL-VILLARD * frame_length--; 18442439e4bfSJean-Christophe PLAGNIOL-VILLARD * } else { 1845472d5460SYork Sun * accept_frame = false; 18462439e4bfSJean-Christophe PLAGNIOL-VILLARD * } 18472439e4bfSJean-Christophe PLAGNIOL-VILLARD * ... 18482439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 18492439e4bfSJean-Christophe PLAGNIOL-VILLARD 18502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ 18512439e4bfSJean-Christophe PLAGNIOL-VILLARD ((adapter)->tbi_compatibility_on && \ 18522439e4bfSJean-Christophe PLAGNIOL-VILLARD (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 18532439e4bfSJean-Christophe PLAGNIOL-VILLARD ((last_byte) == CARRIER_EXTENSION) && \ 18542439e4bfSJean-Christophe PLAGNIOL-VILLARD (((status) & E1000_RXD_STAT_VP) ? \ 18552439e4bfSJean-Christophe PLAGNIOL-VILLARD (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ 18562439e4bfSJean-Christophe PLAGNIOL-VILLARD ((length) <= ((adapter)->max_frame_size + 1))) : \ 18572439e4bfSJean-Christophe PLAGNIOL-VILLARD (((length) > (adapter)->min_frame_size) && \ 18582439e4bfSJean-Christophe PLAGNIOL-VILLARD ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 18592439e4bfSJean-Christophe PLAGNIOL-VILLARD 18602439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Structures, enums, and macros for the PHY */ 18612439e4bfSJean-Christophe PLAGNIOL-VILLARD 18622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Bit definitions for the Management Data IO (MDIO) and Management Data 18632439e4bfSJean-Christophe PLAGNIOL-VILLARD * Clock (MDC) pins in the Device Control Register. 18642439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 18652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 18662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 18672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 18682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 18692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 18702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 18712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 18722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 18732439e4bfSJean-Christophe PLAGNIOL-VILLARD 18742439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY 1000 MII Register/Bit Definitions */ 18752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Registers defined by IEEE */ 18762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CTRL 0x00 /* Control Register */ 18772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STATUS 0x01 /* Status Regiser */ 18782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 18792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 18802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 18812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 18822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 18832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 18842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 18852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 18862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 18872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 18882439e4bfSJean-Christophe PLAGNIOL-VILLARD 18892439e4bfSJean-Christophe PLAGNIOL-VILLARD /* M88E1000 Specific Registers */ 18902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 18912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 18922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 18932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 18942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 18952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 18962439e4bfSJean-Christophe PLAGNIOL-VILLARD 1897aa070789SRoy Zang #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 1898aa070789SRoy Zang #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 1899aa070789SRoy Zang 19002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 19012439e4bfSJean-Christophe PLAGNIOL-VILLARD 1902aa070789SRoy Zang /* M88EC018 Rev 2 specific DownShift settings */ 1903aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1904aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 1905aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 1906aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 1907aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 1908aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1909aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 1910aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 1911aa070789SRoy Zang #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 1912aa070789SRoy Zang 1913ac3315c2SAndre Schwarz /* IGP01E1000 specifics */ 1914ac3315c2SAndre Schwarz #define IGP01E1000_IEEE_REGS_PAGE 0x0000 1915ac3315c2SAndre Schwarz #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 1916ac3315c2SAndre Schwarz #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 1917ac3315c2SAndre Schwarz 1918ac3315c2SAndre Schwarz /* IGP01E1000 Specific Registers */ 1919ac3315c2SAndre Schwarz #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 1920ac3315c2SAndre Schwarz #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 1921ac3315c2SAndre Schwarz #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 1922ac3315c2SAndre Schwarz #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 1923ac3315c2SAndre Schwarz #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 1924ac3315c2SAndre Schwarz #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 1925ac3315c2SAndre Schwarz #define IGP02E1000_PHY_POWER_MGMT 0x19 1926ac3315c2SAndre Schwarz #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 1927ac3315c2SAndre Schwarz 1928aa070789SRoy Zang /* IGP01E1000 AGC Registers - stores the cable length values*/ 1929aa070789SRoy Zang #define IGP01E1000_PHY_AGC_A 0x1172 1930aa070789SRoy Zang #define IGP01E1000_PHY_AGC_B 0x1272 1931aa070789SRoy Zang #define IGP01E1000_PHY_AGC_C 0x1472 1932aa070789SRoy Zang #define IGP01E1000_PHY_AGC_D 0x1872 1933aa070789SRoy Zang 1934aa070789SRoy Zang /* IGP01E1000 Specific Port Config Register - R/W */ 1935aa070789SRoy Zang #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 1936aa070789SRoy Zang #define IGP01E1000_PSCFR_PRE_EN 0x0020 1937aa070789SRoy Zang #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 1938aa070789SRoy Zang #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 1939aa070789SRoy Zang #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 1940aa070789SRoy Zang #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 1941aa070789SRoy Zang /* IGP02E1000 AGC Registers for cable length values */ 1942aa070789SRoy Zang #define IGP02E1000_PHY_AGC_A 0x11B1 1943aa070789SRoy Zang #define IGP02E1000_PHY_AGC_B 0x12B1 1944aa070789SRoy Zang #define IGP02E1000_PHY_AGC_C 0x14B1 1945aa070789SRoy Zang #define IGP02E1000_PHY_AGC_D 0x18B1 1946aa070789SRoy Zang 1947aa070789SRoy Zang #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 1948aa070789SRoy Zang #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in 1949aa070789SRoy Zang non-D0a modes */ 1950aa070789SRoy Zang #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in 1951aa070789SRoy Zang D0a mode */ 1952aa070789SRoy Zang 1953aa070789SRoy Zang /* IGP01E1000 DSP Reset Register */ 1954aa070789SRoy Zang #define IGP01E1000_PHY_DSP_RESET 0x1F33 1955aa070789SRoy Zang #define IGP01E1000_PHY_DSP_SET 0x1F71 1956aa070789SRoy Zang #define IGP01E1000_PHY_DSP_FFE 0x1F35 1957aa070789SRoy Zang 1958aa070789SRoy Zang #define IGP01E1000_PHY_CHANNEL_NUM 4 1959aa070789SRoy Zang #define IGP02E1000_PHY_CHANNEL_NUM 4 1960aa070789SRoy Zang 1961aa070789SRoy Zang #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 1962aa070789SRoy Zang #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 1963aa070789SRoy Zang #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 1964aa070789SRoy Zang #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 1965aa070789SRoy Zang 1966aa070789SRoy Zang #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 1967aa070789SRoy Zang #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 1968aa070789SRoy Zang 1969aa070789SRoy Zang #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 1970aa070789SRoy Zang #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 1971aa070789SRoy Zang #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 1972aa070789SRoy Zang #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 1973aa070789SRoy Zang 1974aa070789SRoy Zang #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 1975aa070789SRoy Zang /* IGP01E1000 PCS Initialization register - stores the polarity status when 1976aa070789SRoy Zang * speed = 1000 Mbps. */ 1977aa070789SRoy Zang #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 1978aa070789SRoy Zang #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 1979aa070789SRoy Zang 1980aa070789SRoy Zang #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 1981aa070789SRoy Zang 1982aa070789SRoy Zang /* IGP01E1000 GMII FIFO Register */ 1983aa070789SRoy Zang #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 1984aa070789SRoy Zang * on Link-Up */ 1985aa070789SRoy Zang #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 1986aa070789SRoy Zang 1987aa070789SRoy Zang /* IGP01E1000 Analog Register */ 1988aa070789SRoy Zang #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 1989aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 1990aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 1991aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 1992aa070789SRoy Zang 1993aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 1994aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 1995aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 1996aa070789SRoy Zang #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 1997aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 1998aa070789SRoy Zang 1999aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 2000aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 2001aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 2002aa070789SRoy Zang #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 2003aa070789SRoy Zang 2004aa070789SRoy Zang /* IGP01E1000 Specific Port Control Register - R/W */ 2005aa070789SRoy Zang #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 2006aa070789SRoy Zang #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 2007aa070789SRoy Zang #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2008aa070789SRoy Zang #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2009aa070789SRoy Zang #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2010aa070789SRoy Zang #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2011aa070789SRoy Zang /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 2012aa070789SRoy Zang #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ 2013aa070789SRoy Zang #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal 2014aa070789SRoy Zang Disabled */ 2015aa070789SRoy Zang #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ 2016aa070789SRoy Zang #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter 2017aa070789SRoy Zang Disabled */ 2018aa070789SRoy Zang #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 2019aa070789SRoy Zang #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI 2020aa070789SRoy Zang configuration */ 2021aa070789SRoy Zang #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX 2022aa070789SRoy Zang configuration */ 2023aa070789SRoy Zang #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic 2024aa070789SRoy Zang crossover */ 2025aa070789SRoy Zang #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended 2026aa070789SRoy Zang Distance */ 2027aa070789SRoy Zang #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 2028aa070789SRoy Zang #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ 2029aa070789SRoy Zang #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only 2030aa070789SRoy Zang (Energy Detect) */ 2031aa070789SRoy Zang #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ 2032aa070789SRoy Zang #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ 2033aa070789SRoy Zang #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ 2034aa070789SRoy Zang #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 2035aa070789SRoy Zang #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 2036aa070789SRoy Zang 2037aa070789SRoy Zang /* PHY Specific Status Register (Page 0, Register 17) */ 2038aa070789SRoy Zang #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ 2039aa070789SRoy Zang #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ 2040aa070789SRoy Zang #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ 2041aa070789SRoy Zang #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ 2042aa070789SRoy Zang #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ 2043aa070789SRoy Zang #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ 2044aa070789SRoy Zang #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ 2045aa070789SRoy Zang #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ 2046aa070789SRoy Zang #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ 2047aa070789SRoy Zang #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ 2048aa070789SRoy Zang #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ 2049aa070789SRoy Zang #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ 2050aa070789SRoy Zang #define GG82563_PSSR_SPEED_MASK 0xC000 2051aa070789SRoy Zang #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ 2052aa070789SRoy Zang #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ 2053aa070789SRoy Zang #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ 2054aa070789SRoy Zang 2055aa070789SRoy Zang /* PHY Specific Status Register 2 (Page 0, Register 19) */ 2056aa070789SRoy Zang #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ 2057aa070789SRoy Zang #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ 2058aa070789SRoy Zang #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ 2059aa070789SRoy Zang #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ 2060aa070789SRoy Zang #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ 2061472d5460SYork Sun #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */ 2062aa070789SRoy Zang #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ 2063aa070789SRoy Zang #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ 2064aa070789SRoy Zang #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ 2065aa070789SRoy Zang #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ 2066aa070789SRoy Zang #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ 2067aa070789SRoy Zang #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ 2068aa070789SRoy Zang #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ 2069aa070789SRoy Zang 2070aa070789SRoy Zang /* PHY Specific Control Register 2 (Page 0, Register 26) */ 2071aa070789SRoy Zang #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative 2072aa070789SRoy Zang Polarity */ 2073aa070789SRoy Zang #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C 2074aa070789SRoy Zang #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal 2075aa070789SRoy Zang Operation */ 2076aa070789SRoy Zang #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns 2077aa070789SRoy Zang Sequence */ 2078aa070789SRoy Zang #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns 2079aa070789SRoy Zang Sequence */ 2080aa070789SRoy Zang #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse 2081aa070789SRoy Zang Auto-Negotiation */ 2082aa070789SRoy Zang #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 2083aa070789SRoy Zang 1000BASE-T */ 2084aa070789SRoy Zang #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 2085aa070789SRoy Zang #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ 2086aa070789SRoy Zang #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ 2087aa070789SRoy Zang 2088aa070789SRoy Zang /* MAC Specific Control Register (Page 2, Register 21) */ 2089aa070789SRoy Zang /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 2090aa070789SRoy Zang #define GG82563_MSCR_TX_CLK_MASK 0x0007 2091aa070789SRoy Zang #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 2092aa070789SRoy Zang #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 2093aa070789SRoy Zang #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 2094aa070789SRoy Zang #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 2095aa070789SRoy Zang 2096aa070789SRoy Zang #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 2097aa070789SRoy Zang 2098aa070789SRoy Zang /* DSP Distance Register (Page 5, Register 26) */ 2099aa070789SRoy Zang #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; 2100aa070789SRoy Zang 1 = 50-80M; 2101aa070789SRoy Zang 2 = 80-110M; 2102aa070789SRoy Zang 3 = 110-140M; 2103aa070789SRoy Zang 4 = >140M */ 2104aa070789SRoy Zang 2105aa070789SRoy Zang /* Kumeran Mode Control Register (Page 193, Register 16) */ 2106aa070789SRoy Zang #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 2107aa070789SRoy Zang 0=Kumeran Inband LEDs */ 2108aa070789SRoy Zang #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ 2109aa070789SRoy Zang #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 2110aa070789SRoy Zang #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 2111aa070789SRoy Zang #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 2112aa070789SRoy Zang 0=0.8MHz */ 2113aa070789SRoy Zang #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 2114aa070789SRoy Zang 2115aa070789SRoy Zang /* Power Management Control Register (Page 193, Register 20) */ 2116aa070789SRoy Zang #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES 2117aa070789SRoy Zang Electrical Idle */ 2118aa070789SRoy Zang #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ 2119aa070789SRoy Zang #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ 2120aa070789SRoy Zang #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse 2121aa070789SRoy Zang Auto-Negotiation */ 2122aa070789SRoy Zang #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps 2123aa070789SRoy Zang Auto-Neg in non D0 */ 2124aa070789SRoy Zang #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps 2125aa070789SRoy Zang Auto-Neg Always */ 2126aa070789SRoy Zang #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a 2127aa070789SRoy Zang Reverse Auto-Negotiation */ 2128aa070789SRoy Zang #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ 2129aa070789SRoy Zang #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 2130aa070789SRoy Zang #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ 2131aa070789SRoy Zang #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ 2132aa070789SRoy Zang #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ 2133aa070789SRoy Zang #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ 2134aa070789SRoy Zang 2135aa070789SRoy Zang /* In-Band Control Register (Page 194, Register 18) */ 2136aa070789SRoy Zang #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ 2137aa070789SRoy Zang 2138aa070789SRoy Zang 2139aa070789SRoy Zang /* Bits... 2140aa070789SRoy Zang * 15-5: page 2141aa070789SRoy Zang * 4-0: register offset 2142aa070789SRoy Zang */ 2143aa070789SRoy Zang #define GG82563_PAGE_SHIFT 5 2144aa070789SRoy Zang #define GG82563_REG(page, reg) \ 2145aa070789SRoy Zang (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2146aa070789SRoy Zang #define GG82563_MIN_ALT_REG 30 2147aa070789SRoy Zang 2148aa070789SRoy Zang /* GG82563 Specific Registers */ 2149aa070789SRoy Zang #define GG82563_PHY_SPEC_CTRL \ 2150aa070789SRoy Zang GG82563_REG(0, 16) /* PHY Specific Control */ 2151aa070789SRoy Zang #define GG82563_PHY_SPEC_STATUS \ 2152aa070789SRoy Zang GG82563_REG(0, 17) /* PHY Specific Status */ 2153aa070789SRoy Zang #define GG82563_PHY_INT_ENABLE \ 2154aa070789SRoy Zang GG82563_REG(0, 18) /* Interrupt Enable */ 2155aa070789SRoy Zang #define GG82563_PHY_SPEC_STATUS_2 \ 2156aa070789SRoy Zang GG82563_REG(0, 19) /* PHY Specific Status 2 */ 2157aa070789SRoy Zang #define GG82563_PHY_RX_ERR_CNTR \ 2158aa070789SRoy Zang GG82563_REG(0, 21) /* Receive Error Counter */ 2159aa070789SRoy Zang #define GG82563_PHY_PAGE_SELECT \ 2160aa070789SRoy Zang GG82563_REG(0, 22) /* Page Select */ 2161aa070789SRoy Zang #define GG82563_PHY_SPEC_CTRL_2 \ 2162aa070789SRoy Zang GG82563_REG(0, 26) /* PHY Specific Control 2 */ 2163aa070789SRoy Zang #define GG82563_PHY_PAGE_SELECT_ALT \ 2164aa070789SRoy Zang GG82563_REG(0, 29) /* Alternate Page Select */ 2165aa070789SRoy Zang #define GG82563_PHY_TEST_CLK_CTRL \ 2166aa070789SRoy Zang GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ 2167aa070789SRoy Zang 2168aa070789SRoy Zang #define GG82563_PHY_MAC_SPEC_CTRL \ 2169aa070789SRoy Zang GG82563_REG(2, 21) /* MAC Specific Control Register */ 2170aa070789SRoy Zang #define GG82563_PHY_MAC_SPEC_CTRL_2 \ 2171aa070789SRoy Zang GG82563_REG(2, 26) /* MAC Specific Control 2 */ 2172aa070789SRoy Zang 2173aa070789SRoy Zang #define GG82563_PHY_DSP_DISTANCE \ 2174aa070789SRoy Zang GG82563_REG(5, 26) /* DSP Distance */ 2175aa070789SRoy Zang 2176aa070789SRoy Zang /* Page 193 - Port Control Registers */ 2177aa070789SRoy Zang #define GG82563_PHY_KMRN_MODE_CTRL \ 2178aa070789SRoy Zang GG82563_REG(193, 16) /* Kumeran Mode Control */ 2179aa070789SRoy Zang #define GG82563_PHY_PORT_RESET \ 2180aa070789SRoy Zang GG82563_REG(193, 17) /* Port Reset */ 2181aa070789SRoy Zang #define GG82563_PHY_REVISION_ID \ 2182aa070789SRoy Zang GG82563_REG(193, 18) /* Revision ID */ 2183aa070789SRoy Zang #define GG82563_PHY_DEVICE_ID \ 2184aa070789SRoy Zang GG82563_REG(193, 19) /* Device ID */ 2185aa070789SRoy Zang #define GG82563_PHY_PWR_MGMT_CTRL \ 2186aa070789SRoy Zang GG82563_REG(193, 20) /* Power Management Control */ 2187aa070789SRoy Zang #define GG82563_PHY_RATE_ADAPT_CTRL \ 2188aa070789SRoy Zang GG82563_REG(193, 25) /* Rate Adaptation Control */ 2189aa070789SRoy Zang 2190aa070789SRoy Zang /* Page 194 - KMRN Registers */ 2191aa070789SRoy Zang #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 2192aa070789SRoy Zang GG82563_REG(194, 16) /* FIFO's Control/Status */ 2193aa070789SRoy Zang #define GG82563_PHY_KMRN_CTRL \ 2194aa070789SRoy Zang GG82563_REG(194, 17) /* Control */ 2195aa070789SRoy Zang #define GG82563_PHY_INBAND_CTRL \ 2196aa070789SRoy Zang GG82563_REG(194, 18) /* Inband Control */ 2197aa070789SRoy Zang #define GG82563_PHY_KMRN_DIAGNOSTIC \ 2198aa070789SRoy Zang GG82563_REG(194, 19) /* Diagnostic */ 2199aa070789SRoy Zang #define GG82563_PHY_ACK_TIMEOUTS \ 2200aa070789SRoy Zang GG82563_REG(194, 20) /* Acknowledge Timeouts */ 2201aa070789SRoy Zang #define GG82563_PHY_ADV_ABILITY \ 2202aa070789SRoy Zang GG82563_REG(194, 21) /* Advertised Ability */ 2203aa070789SRoy Zang #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 2204aa070789SRoy Zang GG82563_REG(194, 23) /* Link Partner Advertised Ability */ 2205aa070789SRoy Zang #define GG82563_PHY_ADV_NEXT_PAGE \ 2206aa070789SRoy Zang GG82563_REG(194, 24) /* Advertised Next Page */ 2207aa070789SRoy Zang #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 2208aa070789SRoy Zang GG82563_REG(194, 25) /* Link Partner Advertised Next page */ 2209aa070789SRoy Zang #define GG82563_PHY_KMRN_MISC \ 2210aa070789SRoy Zang GG82563_REG(194, 26) /* Misc. */ 2211aa070789SRoy Zang 22122439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Control Register */ 22132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 22142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 22152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 22162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 22172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 22182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 22192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 22202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 22212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 22222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 22232439e4bfSJean-Christophe PLAGNIOL-VILLARD 22242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Status Register */ 22252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 22262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 22272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 22282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 22292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 22302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 22312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 22322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 22332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 22342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 22352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 22362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 22372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 22382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 22392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 22402439e4bfSJean-Christophe PLAGNIOL-VILLARD 22412439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Autoneg Advertisement Register */ 22422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 22432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 22442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 22452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 22462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 22472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 22482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 22492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 22502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 22512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 22522439e4bfSJean-Christophe PLAGNIOL-VILLARD 22532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Link Partner Ability Register (Base Page) */ 22542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 22552439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 22562439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 22572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 22582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 22592439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 22602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 22612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 22622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 22632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 22642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 22652439e4bfSJean-Christophe PLAGNIOL-VILLARD 22662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Autoneg Expansion Register */ 22672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 22682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 22692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 22702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 22712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ 22722439e4bfSJean-Christophe PLAGNIOL-VILLARD 22732439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Next Page TX Register */ 22742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 22752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 22762439e4bfSJean-Christophe PLAGNIOL-VILLARD * of different NP 22772439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 22782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 22792439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 = cannot comply with msg 22802439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 22812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 22822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 22832439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 = sending last NP 22842439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 22852439e4bfSJean-Christophe PLAGNIOL-VILLARD 22862439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Link Partner Next Page Register */ 22872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 22882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 22892439e4bfSJean-Christophe PLAGNIOL-VILLARD * of different NP 22902439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 22912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 22922439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 = cannot comply with msg 22932439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 22942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 22952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 22962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 22972439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0 = sending last NP 22982439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 22992439e4bfSJean-Christophe PLAGNIOL-VILLARD 23002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1000BASE-T Control Register */ 23012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 23022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 23032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 23042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 23052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 0=DTE device */ 23062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 23072439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 0=Configure PHY as Slave */ 23082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 23092439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 0=Automatic Master/Slave config */ 23102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 23112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 23122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 23132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 23142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 23152439e4bfSJean-Christophe PLAGNIOL-VILLARD 23162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1000BASE-T Status Register */ 23172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 23182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 23192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 23202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 23212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 23222439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 23232439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 23242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 23252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 23262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 23272439e4bfSJean-Christophe PLAGNIOL-VILLARD 23282439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Extended Status Register */ 23292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 23302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 23312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 23322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 23332439e4bfSJean-Christophe PLAGNIOL-VILLARD 23342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 23352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 23362439e4bfSJean-Christophe PLAGNIOL-VILLARD 23372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 23382439e4bfSJean-Christophe PLAGNIOL-VILLARD /* (0=enable, 1=disable) */ 23392439e4bfSJean-Christophe PLAGNIOL-VILLARD 23402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* M88E1000 PHY Specific Control Register */ 23412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 23422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 23432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 23442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 23452439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0=CLK125 toggling 23462439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 23472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 23482439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Manual MDI configuration */ 23492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 23502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 23512439e4bfSJean-Christophe PLAGNIOL-VILLARD * 100BASE-TX/10BASE-T: 23522439e4bfSJean-Christophe PLAGNIOL-VILLARD * MDI Mode 23532439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 23542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 23552439e4bfSJean-Christophe PLAGNIOL-VILLARD * all speeds. 23562439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 23572439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 23582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1=Enable Extended 10BASE-T distance 23592439e4bfSJean-Christophe PLAGNIOL-VILLARD * (Lower 10BASE-T RX Threshold) 23602439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0=Normal 10BASE-T RX Threshold */ 23612439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 23622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 1=5-Bit interface in 100BASE-TX 23632439e4bfSJean-Christophe PLAGNIOL-VILLARD * 0=MII interface in 100BASE-TX */ 23642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 23652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 23662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 23672439e4bfSJean-Christophe PLAGNIOL-VILLARD 23682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 23692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 23702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 23712439e4bfSJean-Christophe PLAGNIOL-VILLARD 23722439e4bfSJean-Christophe PLAGNIOL-VILLARD /* M88E1000 PHY Specific Status Register */ 23732439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 23742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 23752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 23762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 23772439e4bfSJean-Christophe PLAGNIOL-VILLARD * 3=110-140M;4=>140M */ 23782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 23792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 23802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 23812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 23822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 23832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 23842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 23852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 23862439e4bfSJean-Christophe PLAGNIOL-VILLARD 23872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 23882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_MDIX_SHIFT 6 23892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 23902439e4bfSJean-Christophe PLAGNIOL-VILLARD 23912439e4bfSJean-Christophe PLAGNIOL-VILLARD /* M88E1000 Extended PHY Specific Control Register */ 23922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 23932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 23942439e4bfSJean-Christophe PLAGNIOL-VILLARD * Will assert lost lock and bring 23952439e4bfSJean-Christophe PLAGNIOL-VILLARD * link down if idle not seen 23962439e4bfSJean-Christophe PLAGNIOL-VILLARD * within 1ms in 1000BASE-T 23972439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 23982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Number of times we will attempt to autonegotiate before downshifting if we 23992439e4bfSJean-Christophe PLAGNIOL-VILLARD * are the master */ 24002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 24012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 24022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 24032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 24042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 24052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Number of times we will attempt to autonegotiate before downshifting if we 24062439e4bfSJean-Christophe PLAGNIOL-VILLARD * are the slave */ 24072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 24082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 24092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 24102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 24112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 24122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 24132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 24142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 24152439e4bfSJean-Christophe PLAGNIOL-VILLARD 24162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Bit definitions for valid PHY IDs. */ 24172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_E_PHY_ID 0x01410C50 24182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_I_PHY_ID 0x01410C30 24192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1011_I_PHY_ID 0x01410C20 24202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 24212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 2422ac3315c2SAndre Schwarz #define IGP01E1000_I_PHY_ID 0x02A80380 2423aa070789SRoy Zang #define M88E1011_I_REV_4 0x04 2424aa070789SRoy Zang #define M88E1111_I_PHY_ID 0x01410CC0 2425aa070789SRoy Zang #define L1LXT971A_PHY_ID 0x001378E0 2426aa070789SRoy Zang #define GG82563_E_PHY_ID 0x01410CA0 24272439e4bfSJean-Christophe PLAGNIOL-VILLARD 24282c2668f9SRoy Zang #define BME1000_E_PHY_ID 0x01410CB0 24292c2668f9SRoy Zang 243095186063SMarek Vasut #define I210_I_PHY_ID 0x01410C00 243195186063SMarek Vasut 24322439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Miscellaneous PHY bit definitions. */ 24332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_PREAMBLE 0xFFFFFFFF 24342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_SOF 0x01 24352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_OP_READ 0x02 24362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_OP_WRITE 0x01 24372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_TURNAROUND 0x02 24382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_PREAMBLE_SIZE 32 24392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_SPEED_1000 0x0040 24402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_SPEED_100 0x2000 24412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_CR_SPEED_10 0x0000 24422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define E1000_PHY_ADDRESS 0x01 2443faa765d4SStefan Roese #define PHY_AUTO_NEG_TIME 80 /* 8.0 Seconds */ 24442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 24452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_REVISION_MASK 0xFFFFFFF0 24462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 24472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define REG4_SPEED_MASK 0x01E0 24482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define REG9_SPEED_MASK 0x0300 24492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADVERTISE_10_HALF 0x0001 24502439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADVERTISE_10_FULL 0x0002 24512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADVERTISE_100_HALF 0x0004 24522439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADVERTISE_100_FULL 0x0008 24532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADVERTISE_1000_HALF 0x0010 24542439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADVERTISE_1000_FULL 0x0020 24552439e4bfSJean-Christophe PLAGNIOL-VILLARD 2456aa070789SRoy Zang #define ICH_FLASH_GFPREG 0x0000 2457aa070789SRoy Zang #define ICH_FLASH_HSFSTS 0x0004 2458aa070789SRoy Zang #define ICH_FLASH_HSFCTL 0x0006 2459aa070789SRoy Zang #define ICH_FLASH_FADDR 0x0008 2460aa070789SRoy Zang #define ICH_FLASH_FDATA0 0x0010 2461aa070789SRoy Zang #define ICH_FLASH_FRACC 0x0050 2462aa070789SRoy Zang #define ICH_FLASH_FREG0 0x0054 2463aa070789SRoy Zang #define ICH_FLASH_FREG1 0x0058 2464aa070789SRoy Zang #define ICH_FLASH_FREG2 0x005C 2465aa070789SRoy Zang #define ICH_FLASH_FREG3 0x0060 2466aa070789SRoy Zang #define ICH_FLASH_FPR0 0x0074 2467aa070789SRoy Zang #define ICH_FLASH_FPR1 0x0078 2468aa070789SRoy Zang #define ICH_FLASH_SSFSTS 0x0090 2469aa070789SRoy Zang #define ICH_FLASH_SSFCTL 0x0092 2470aa070789SRoy Zang #define ICH_FLASH_PREOP 0x0094 2471aa070789SRoy Zang #define ICH_FLASH_OPTYPE 0x0096 2472aa070789SRoy Zang #define ICH_FLASH_OPMENU 0x0098 2473aa070789SRoy Zang 2474aa070789SRoy Zang #define ICH_FLASH_REG_MAPSIZE 0x00A0 2475aa070789SRoy Zang #define ICH_FLASH_SECTOR_SIZE 4096 2476aa070789SRoy Zang #define ICH_GFPREG_BASE_MASK 0x1FFF 2477aa070789SRoy Zang #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 2478aa070789SRoy Zang 2479aa070789SRoy Zang #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 2480aa070789SRoy Zang 2481aa070789SRoy Zang /* SPI EEPROM Status Register */ 2482aa070789SRoy Zang #define EEPROM_STATUS_RDY_SPI 0x01 2483aa070789SRoy Zang #define EEPROM_STATUS_WEN_SPI 0x02 2484aa070789SRoy Zang #define EEPROM_STATUS_BP0_SPI 0x04 2485aa070789SRoy Zang #define EEPROM_STATUS_BP1_SPI 0x08 2486aa070789SRoy Zang #define EEPROM_STATUS_WPEN_SPI 0x80 2487aa070789SRoy Zang 2488aa070789SRoy Zang /* SW Semaphore Register */ 2489aa070789SRoy Zang #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2490aa070789SRoy Zang #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2491aa070789SRoy Zang #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2492aa070789SRoy Zang #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2493aa070789SRoy Zang 2494aa070789SRoy Zang /* FW Semaphore Register */ 2495aa070789SRoy Zang #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2496aa070789SRoy Zang #define E1000_FWSM_MODE_SHIFT 1 2497aa070789SRoy Zang #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2498aa070789SRoy Zang 2499aa070789SRoy Zang #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2500aa070789SRoy Zang #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2501aa070789SRoy Zang #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2502aa070789SRoy Zang #define E1000_FWSM_SKUEL_SHIFT 29 2503aa070789SRoy Zang #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2504aa070789SRoy Zang #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2505aa070789SRoy Zang #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2506aa070789SRoy Zang #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2507aa070789SRoy Zang 2508aa070789SRoy Zang #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 2509aa070789SRoy Zang #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 2510aa070789SRoy Zang #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 2511aa070789SRoy Zang #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 2512aa070789SRoy Zang #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 2513aa070789SRoy Zang #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 2514aa070789SRoy Zang #define E1000_SWSM 0x05B50 /* SW Semaphore */ 2515aa070789SRoy Zang #define E1000_FWSM 0x05B54 /* FW Semaphore */ 2516aa070789SRoy Zang #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 2517aa070789SRoy Zang #define E1000_HICR 0x08F00 /* Host Inteface Control */ 2518aa070789SRoy Zang 2519aa070789SRoy Zang #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 2520aa070789SRoy Zang #define IGP_ACTIVITY_LED_ENABLE 0x0300 2521aa070789SRoy Zang #define IGP_LED3_MODE 0x07000000 2522aa070789SRoy Zang 2523aa070789SRoy Zang /* Mask bit for PHY class in Word 7 of the EEPROM */ 2524aa070789SRoy Zang #define EEPROM_PHY_CLASS_A 0x8000 2525aa070789SRoy Zang #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 2526aa070789SRoy Zang #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 2527aa070789SRoy Zang #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 2528aa070789SRoy Zang 2529aa070789SRoy Zang #define E1000_KUMCTRLSTA_MASK 0x0000FFFF 2530aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET 0x001F0000 2531aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 2532aa070789SRoy Zang #define E1000_KUMCTRLSTA_REN 0x00200000 2533aa070789SRoy Zang 2534aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 2535aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 2536aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 2537aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 2538aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 2539aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 2540aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 2541aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 2542aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 2543aa070789SRoy Zang 2544aa070789SRoy Zang /* FIFO Control */ 2545aa070789SRoy Zang #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 2546aa070789SRoy Zang #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 2547aa070789SRoy Zang 2548aa070789SRoy Zang /* In-Band Control */ 2549aa070789SRoy Zang #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 2550aa070789SRoy Zang #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 2551aa070789SRoy Zang 2552aa070789SRoy Zang /* Half-Duplex Control */ 2553aa070789SRoy Zang #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 2554aa070789SRoy Zang #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 2555aa070789SRoy Zang 2556aa070789SRoy Zang #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E 2557aa070789SRoy Zang 2558aa070789SRoy Zang #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 2559aa070789SRoy Zang #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 2560aa070789SRoy Zang 2561aa070789SRoy Zang #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 2562aa070789SRoy Zang #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 2563aa070789SRoy Zang #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 2564aa070789SRoy Zang 2565aa070789SRoy Zang #define E1000_MNG_ICH_IAMT_MODE 0x2 2566aa070789SRoy Zang #define E1000_MNG_IAMT_MODE 0x3 2567aa070789SRoy Zang #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2568aa070789SRoy Zang #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 2569aa070789SRoy Zang /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2570aa070789SRoy Zang #define PHY_CFG_TIMEOUT 100 2571aa070789SRoy Zang #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 2572aa070789SRoy Zang #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 2573aa070789SRoy Zang #define AUTO_ALL_MODES 0 2574aa070789SRoy Zang 2575aa070789SRoy Zang #ifndef E1000_MASTER_SLAVE 2576aa070789SRoy Zang /* Switch to override PHY master/slave setting */ 2577aa070789SRoy Zang #define E1000_MASTER_SLAVE e1000_ms_hw_default 2578aa070789SRoy Zang #endif 2579aa070789SRoy Zang /* Extended Transmit Control */ 2580aa070789SRoy Zang #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 2581aa070789SRoy Zang #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 2582aa070789SRoy Zang 2583aa070789SRoy Zang #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 2584aa070789SRoy Zang 2585aa070789SRoy Zang #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL 2586aa070789SRoy Zang 2587aa070789SRoy Zang #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2588aa070789SRoy Zang #define E1000_MC_TBL_SIZE_ICH8LAN 32 2589aa070789SRoy Zang 2590aa070789SRoy Zang #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers 2591aa070789SRoy Zang after IMS clear */ 25922439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* _E1000_HW_H_ */ 2593