1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2ff6af28fSMasahiro Yamada /*
3ff6af28fSMasahiro Yamada * Copyright (C) 2016 Socionext Inc.
4ff6af28fSMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5ff6af28fSMasahiro Yamada */
6ff6af28fSMasahiro Yamada
7f02cebdfSMasahiro Yamada #include <linux/bitfield.h>
8cd7a0d21SMasahiro Yamada #include <linux/bits.h>
9ff6af28fSMasahiro Yamada #include <linux/iopoll.h>
10ff6af28fSMasahiro Yamada #include <linux/module.h>
11ff6af28fSMasahiro Yamada #include <linux/mmc/host.h>
12963836adSUlf Hansson #include <linux/mmc/mmc.h>
13a89c472dSPiotr Sroka #include <linux/of.h>
14c62da8a8SRob Herring #include <linux/platform_device.h>
15aad53d4eSBrad Larson #include <linux/reset.h>
16ff6af28fSMasahiro Yamada
17ff6af28fSMasahiro Yamada #include "sdhci-pltfm.h"
18ff6af28fSMasahiro Yamada
19ff6af28fSMasahiro Yamada /* HRS - Host Register Set (specific to Cadence) */
20ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
21ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS04_ACK BIT(26)
22ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS04_RD BIT(25)
23ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS04_WR BIT(24)
24f02cebdfSMasahiro Yamada #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
25f02cebdfSMasahiro Yamada #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
26f02cebdfSMasahiro Yamada #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
27ff6af28fSMasahiro Yamada
28ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
29ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
30f02cebdfSMasahiro Yamada #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
31f02cebdfSMasahiro Yamada #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
32ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06_MODE_SD 0x0
33ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
34ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
35ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
36ff6af28fSMasahiro Yamada #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
37d12990f9SPiotr Sroka #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
38ff6af28fSMasahiro Yamada
39ff6af28fSMasahiro Yamada /* SRS - Slot Register Set (SDHCI-compatible) */
40ff6af28fSMasahiro Yamada #define SDHCI_CDNS_SRS_BASE 0x200
41ff6af28fSMasahiro Yamada
42ff6af28fSMasahiro Yamada /* PHY */
43ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
44ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
45ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
46ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
47ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
48ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
49ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
50ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
51ff6af28fSMasahiro Yamada #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
52a89c472dSPiotr Sroka #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
53a89c472dSPiotr Sroka #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
54a89c472dSPiotr Sroka #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
55ff6af28fSMasahiro Yamada
56ff6af28fSMasahiro Yamada /*
57ff6af28fSMasahiro Yamada * The tuned val register is 6 bit-wide, but not the whole of the range is
58ff6af28fSMasahiro Yamada * available. The range 0-42 seems to be available (then 43 wraps around to 0)
59ff6af28fSMasahiro Yamada * but I am not quite sure if it is official. Use only 0 to 39 for safety.
60ff6af28fSMasahiro Yamada */
61ff6af28fSMasahiro Yamada #define SDHCI_CDNS_MAX_TUNING_LOOP 40
62ff6af28fSMasahiro Yamada
63a232a8f2SMasahiro Yamada struct sdhci_cdns_phy_param {
64a232a8f2SMasahiro Yamada u8 addr;
65a232a8f2SMasahiro Yamada u8 data;
66a232a8f2SMasahiro Yamada };
67a232a8f2SMasahiro Yamada
68ff6af28fSMasahiro Yamada struct sdhci_cdns_priv {
69ff6af28fSMasahiro Yamada void __iomem *hrs_addr;
70b5dbcf1fSBrad Larson void __iomem *ctl_addr; /* write control */
71b5dbcf1fSBrad Larson spinlock_t wrlock; /* write lock */
72d12990f9SPiotr Sroka bool enhanced_strobe;
73d3e32f84SBrad Larson void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
74aad53d4eSBrad Larson struct reset_control *rst_hw;
75a232a8f2SMasahiro Yamada unsigned int nr_phy_params;
761a91a36aSGustavo A. R. Silva struct sdhci_cdns_phy_param phy_params[];
77ff6af28fSMasahiro Yamada };
78ff6af28fSMasahiro Yamada
79a89c472dSPiotr Sroka struct sdhci_cdns_phy_cfg {
80a89c472dSPiotr Sroka const char *property;
81a89c472dSPiotr Sroka u8 addr;
82a89c472dSPiotr Sroka };
83a89c472dSPiotr Sroka
84e095b78eSBrad Larson struct sdhci_cdns_drv_data {
85e095b78eSBrad Larson int (*init)(struct platform_device *pdev);
86e095b78eSBrad Larson const struct sdhci_pltfm_data pltfm_data;
87e095b78eSBrad Larson };
88e095b78eSBrad Larson
89a89c472dSPiotr Sroka static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
90a89c472dSPiotr Sroka { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91a89c472dSPiotr Sroka { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
92a89c472dSPiotr Sroka { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
93a89c472dSPiotr Sroka { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
94a89c472dSPiotr Sroka { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
95a89c472dSPiotr Sroka { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
96a89c472dSPiotr Sroka { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
97a89c472dSPiotr Sroka { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
98a89c472dSPiotr Sroka { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
99a89c472dSPiotr Sroka { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
100a89c472dSPiotr Sroka { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
101a89c472dSPiotr Sroka };
102a89c472dSPiotr Sroka
cdns_writel(struct sdhci_cdns_priv * priv,u32 val,void __iomem * reg)103d3e32f84SBrad Larson static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val,
104d3e32f84SBrad Larson void __iomem *reg)
105d3e32f84SBrad Larson {
106d3e32f84SBrad Larson writel(val, reg);
107d3e32f84SBrad Larson }
108d3e32f84SBrad Larson
sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv * priv,u8 addr,u8 data)109a0f82432SPiotr Sroka static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
110ff6af28fSMasahiro Yamada u8 addr, u8 data)
111ff6af28fSMasahiro Yamada {
112ff6af28fSMasahiro Yamada void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
113ff6af28fSMasahiro Yamada u32 tmp;
114a0f82432SPiotr Sroka int ret;
115ff6af28fSMasahiro Yamada
116f6bc8186SVladimir Kondratiev ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
117f6bc8186SVladimir Kondratiev 0, 10);
118f6bc8186SVladimir Kondratiev if (ret)
119f6bc8186SVladimir Kondratiev return ret;
120f6bc8186SVladimir Kondratiev
121f02cebdfSMasahiro Yamada tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
122f02cebdfSMasahiro Yamada FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
123d3e32f84SBrad Larson priv->priv_writel(priv, tmp, reg);
124ff6af28fSMasahiro Yamada
125ff6af28fSMasahiro Yamada tmp |= SDHCI_CDNS_HRS04_WR;
126d3e32f84SBrad Larson priv->priv_writel(priv, tmp, reg);
127ff6af28fSMasahiro Yamada
128a0f82432SPiotr Sroka ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
129a0f82432SPiotr Sroka if (ret)
130a0f82432SPiotr Sroka return ret;
131a0f82432SPiotr Sroka
132ff6af28fSMasahiro Yamada tmp &= ~SDHCI_CDNS_HRS04_WR;
133d3e32f84SBrad Larson priv->priv_writel(priv, tmp, reg);
134a0f82432SPiotr Sroka
135f6bc8186SVladimir Kondratiev ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
136f6bc8186SVladimir Kondratiev 0, 10);
137f6bc8186SVladimir Kondratiev
138f6bc8186SVladimir Kondratiev return ret;
139ff6af28fSMasahiro Yamada }
140ff6af28fSMasahiro Yamada
sdhci_cdns_phy_param_count(struct device_node * np)141a232a8f2SMasahiro Yamada static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
142a232a8f2SMasahiro Yamada {
143a232a8f2SMasahiro Yamada unsigned int count = 0;
144a232a8f2SMasahiro Yamada int i;
145a232a8f2SMasahiro Yamada
146a232a8f2SMasahiro Yamada for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
147a232a8f2SMasahiro Yamada if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
148a232a8f2SMasahiro Yamada count++;
149a232a8f2SMasahiro Yamada
150a232a8f2SMasahiro Yamada return count;
151a232a8f2SMasahiro Yamada }
152a232a8f2SMasahiro Yamada
sdhci_cdns_phy_param_parse(struct device_node * np,struct sdhci_cdns_priv * priv)153a232a8f2SMasahiro Yamada static void sdhci_cdns_phy_param_parse(struct device_node *np,
154a89c472dSPiotr Sroka struct sdhci_cdns_priv *priv)
155ff6af28fSMasahiro Yamada {
156a232a8f2SMasahiro Yamada struct sdhci_cdns_phy_param *p = priv->phy_params;
157a89c472dSPiotr Sroka u32 val;
158a89c472dSPiotr Sroka int ret, i;
159a89c472dSPiotr Sroka
160a89c472dSPiotr Sroka for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
161a89c472dSPiotr Sroka ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
162a89c472dSPiotr Sroka &val);
163a89c472dSPiotr Sroka if (ret)
164a89c472dSPiotr Sroka continue;
165a89c472dSPiotr Sroka
166a232a8f2SMasahiro Yamada p->addr = sdhci_cdns_phy_cfgs[i].addr;
167a232a8f2SMasahiro Yamada p->data = val;
168a232a8f2SMasahiro Yamada p++;
169a232a8f2SMasahiro Yamada }
170a232a8f2SMasahiro Yamada }
171a232a8f2SMasahiro Yamada
sdhci_cdns_phy_init(struct sdhci_cdns_priv * priv)172a232a8f2SMasahiro Yamada static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
173a232a8f2SMasahiro Yamada {
174a232a8f2SMasahiro Yamada int ret, i;
175a232a8f2SMasahiro Yamada
176a232a8f2SMasahiro Yamada for (i = 0; i < priv->nr_phy_params; i++) {
177a232a8f2SMasahiro Yamada ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
178a232a8f2SMasahiro Yamada priv->phy_params[i].data);
179a89c472dSPiotr Sroka if (ret)
180a89c472dSPiotr Sroka return ret;
181a89c472dSPiotr Sroka }
182a89c472dSPiotr Sroka
183a89c472dSPiotr Sroka return 0;
184ff6af28fSMasahiro Yamada }
185ff6af28fSMasahiro Yamada
sdhci_cdns_priv(struct sdhci_host * host)1861d45a3f4SMasahiro Yamada static void *sdhci_cdns_priv(struct sdhci_host *host)
187ff6af28fSMasahiro Yamada {
188ff6af28fSMasahiro Yamada struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
189ff6af28fSMasahiro Yamada
190ff6af28fSMasahiro Yamada return sdhci_pltfm_priv(pltfm_host);
191ff6af28fSMasahiro Yamada }
192ff6af28fSMasahiro Yamada
sdhci_cdns_get_timeout_clock(struct sdhci_host * host)193ff6af28fSMasahiro Yamada static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
194ff6af28fSMasahiro Yamada {
195ff6af28fSMasahiro Yamada /*
196ff6af28fSMasahiro Yamada * Cadence's spec says the Timeout Clock Frequency is the same as the
1978cc35289SShawn Lin * Base Clock Frequency.
198ff6af28fSMasahiro Yamada */
1998cc35289SShawn Lin return host->max_clk;
200ff6af28fSMasahiro Yamada }
201ff6af28fSMasahiro Yamada
sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv * priv,u32 mode)202d12990f9SPiotr Sroka static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
203d12990f9SPiotr Sroka {
204d12990f9SPiotr Sroka u32 tmp;
205d12990f9SPiotr Sroka
206d12990f9SPiotr Sroka /* The speed mode for eMMC is selected by HRS06 register */
207d12990f9SPiotr Sroka tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
208f02cebdfSMasahiro Yamada tmp &= ~SDHCI_CDNS_HRS06_MODE;
209f02cebdfSMasahiro Yamada tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
210d3e32f84SBrad Larson priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
211d12990f9SPiotr Sroka }
212d12990f9SPiotr Sroka
sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv * priv)213d12990f9SPiotr Sroka static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
214d12990f9SPiotr Sroka {
215d12990f9SPiotr Sroka u32 tmp;
216d12990f9SPiotr Sroka
217d12990f9SPiotr Sroka tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
218f02cebdfSMasahiro Yamada return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
219d12990f9SPiotr Sroka }
220d12990f9SPiotr Sroka
sdhci_cdns_set_tune_val(struct sdhci_host * host,unsigned int val)221adc40a51SMasahiro Yamada static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
222adc40a51SMasahiro Yamada {
223adc40a51SMasahiro Yamada struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
224adc40a51SMasahiro Yamada void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
225adc40a51SMasahiro Yamada u32 tmp;
226adc40a51SMasahiro Yamada int i, ret;
227adc40a51SMasahiro Yamada
228adc40a51SMasahiro Yamada if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
229adc40a51SMasahiro Yamada return -EINVAL;
230adc40a51SMasahiro Yamada
231adc40a51SMasahiro Yamada tmp = readl(reg);
232adc40a51SMasahiro Yamada tmp &= ~SDHCI_CDNS_HRS06_TUNE;
233adc40a51SMasahiro Yamada tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
234adc40a51SMasahiro Yamada
235adc40a51SMasahiro Yamada /*
236adc40a51SMasahiro Yamada * Workaround for IP errata:
237adc40a51SMasahiro Yamada * The IP6116 SD/eMMC PHY design has a timing issue on receive data
238adc40a51SMasahiro Yamada * path. Send tune request twice.
239adc40a51SMasahiro Yamada */
240adc40a51SMasahiro Yamada for (i = 0; i < 2; i++) {
241adc40a51SMasahiro Yamada tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
242d3e32f84SBrad Larson priv->priv_writel(priv, tmp, reg);
243adc40a51SMasahiro Yamada
244adc40a51SMasahiro Yamada ret = readl_poll_timeout(reg, tmp,
245adc40a51SMasahiro Yamada !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
246adc40a51SMasahiro Yamada 0, 1);
247adc40a51SMasahiro Yamada if (ret)
248adc40a51SMasahiro Yamada return ret;
249adc40a51SMasahiro Yamada }
250adc40a51SMasahiro Yamada
251adc40a51SMasahiro Yamada return 0;
252adc40a51SMasahiro Yamada }
253adc40a51SMasahiro Yamada
254adc40a51SMasahiro Yamada /*
255adc40a51SMasahiro Yamada * In SD mode, software must not use the hardware tuning and instead perform
256adc40a51SMasahiro Yamada * an almost identical procedure to eMMC.
257adc40a51SMasahiro Yamada */
sdhci_cdns_execute_tuning(struct sdhci_host * host,u32 opcode)258adc40a51SMasahiro Yamada static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
259adc40a51SMasahiro Yamada {
260adc40a51SMasahiro Yamada int cur_streak = 0;
261adc40a51SMasahiro Yamada int max_streak = 0;
262adc40a51SMasahiro Yamada int end_of_streak = 0;
263adc40a51SMasahiro Yamada int i;
264adc40a51SMasahiro Yamada
265adc40a51SMasahiro Yamada /*
266adc40a51SMasahiro Yamada * Do not execute tuning for UHS_SDR50 or UHS_DDR50.
267adc40a51SMasahiro Yamada * The delay is set by probe, based on the DT properties.
268adc40a51SMasahiro Yamada */
269adc40a51SMasahiro Yamada if (host->timing != MMC_TIMING_MMC_HS200 &&
270adc40a51SMasahiro Yamada host->timing != MMC_TIMING_UHS_SDR104)
271adc40a51SMasahiro Yamada return 0;
272adc40a51SMasahiro Yamada
273adc40a51SMasahiro Yamada for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
274adc40a51SMasahiro Yamada if (sdhci_cdns_set_tune_val(host, i) ||
275adc40a51SMasahiro Yamada mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
276adc40a51SMasahiro Yamada cur_streak = 0;
277adc40a51SMasahiro Yamada } else { /* good */
278adc40a51SMasahiro Yamada cur_streak++;
279adc40a51SMasahiro Yamada if (cur_streak > max_streak) {
280adc40a51SMasahiro Yamada max_streak = cur_streak;
281adc40a51SMasahiro Yamada end_of_streak = i;
282adc40a51SMasahiro Yamada }
283adc40a51SMasahiro Yamada }
284adc40a51SMasahiro Yamada }
285adc40a51SMasahiro Yamada
286adc40a51SMasahiro Yamada if (!max_streak) {
287adc40a51SMasahiro Yamada dev_err(mmc_dev(host->mmc), "no tuning point found\n");
288adc40a51SMasahiro Yamada return -EIO;
289adc40a51SMasahiro Yamada }
290adc40a51SMasahiro Yamada
291adc40a51SMasahiro Yamada return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
292adc40a51SMasahiro Yamada }
293adc40a51SMasahiro Yamada
sdhci_cdns_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)294ff6af28fSMasahiro Yamada static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
295ff6af28fSMasahiro Yamada unsigned int timing)
296ff6af28fSMasahiro Yamada {
297ff6af28fSMasahiro Yamada struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
298d12990f9SPiotr Sroka u32 mode;
299ff6af28fSMasahiro Yamada
300ff6af28fSMasahiro Yamada switch (timing) {
301ff6af28fSMasahiro Yamada case MMC_TIMING_MMC_HS:
302ff6af28fSMasahiro Yamada mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
303ff6af28fSMasahiro Yamada break;
304ff6af28fSMasahiro Yamada case MMC_TIMING_MMC_DDR52:
305ff6af28fSMasahiro Yamada mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
306ff6af28fSMasahiro Yamada break;
307ff6af28fSMasahiro Yamada case MMC_TIMING_MMC_HS200:
308ff6af28fSMasahiro Yamada mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
309ff6af28fSMasahiro Yamada break;
310ff6af28fSMasahiro Yamada case MMC_TIMING_MMC_HS400:
311d12990f9SPiotr Sroka if (priv->enhanced_strobe)
312d12990f9SPiotr Sroka mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
313d12990f9SPiotr Sroka else
314ff6af28fSMasahiro Yamada mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
315ff6af28fSMasahiro Yamada break;
316ff6af28fSMasahiro Yamada default:
317ff6af28fSMasahiro Yamada mode = SDHCI_CDNS_HRS06_MODE_SD;
318ff6af28fSMasahiro Yamada break;
319ff6af28fSMasahiro Yamada }
320ff6af28fSMasahiro Yamada
321d12990f9SPiotr Sroka sdhci_cdns_set_emmc_mode(priv, mode);
322ff6af28fSMasahiro Yamada
323ff6af28fSMasahiro Yamada /* For SD, fall back to the default handler */
324ff6af28fSMasahiro Yamada if (mode == SDHCI_CDNS_HRS06_MODE_SD)
325ff6af28fSMasahiro Yamada sdhci_set_uhs_signaling(host, timing);
326ff6af28fSMasahiro Yamada }
327ff6af28fSMasahiro Yamada
328b5dbcf1fSBrad Larson /* Elba control register bits [6:3] are byte-lane enables */
329b5dbcf1fSBrad Larson #define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3)
330b5dbcf1fSBrad Larson
331b5dbcf1fSBrad Larson /*
332b5dbcf1fSBrad Larson * The Pensando Elba SoC explicitly controls byte-lane enabling on writes
333b5dbcf1fSBrad Larson * which includes writes to the HRS registers. The write lock (wrlock)
334b5dbcf1fSBrad Larson * is used to ensure byte-lane enable, using write control (ctl_addr),
335b5dbcf1fSBrad Larson * occurs before the data write.
336b5dbcf1fSBrad Larson */
elba_priv_writel(struct sdhci_cdns_priv * priv,u32 val,void __iomem * reg)337b5dbcf1fSBrad Larson static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val,
338b5dbcf1fSBrad Larson void __iomem *reg)
339b5dbcf1fSBrad Larson {
340b5dbcf1fSBrad Larson unsigned long flags;
341b5dbcf1fSBrad Larson
342b5dbcf1fSBrad Larson spin_lock_irqsave(&priv->wrlock, flags);
343b5dbcf1fSBrad Larson writel(GENMASK(7, 3), priv->ctl_addr);
344b5dbcf1fSBrad Larson writel(val, reg);
345b5dbcf1fSBrad Larson spin_unlock_irqrestore(&priv->wrlock, flags);
346b5dbcf1fSBrad Larson }
347b5dbcf1fSBrad Larson
elba_write_l(struct sdhci_host * host,u32 val,int reg)348b5dbcf1fSBrad Larson static void elba_write_l(struct sdhci_host *host, u32 val, int reg)
349b5dbcf1fSBrad Larson {
350b5dbcf1fSBrad Larson elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg);
351b5dbcf1fSBrad Larson }
352b5dbcf1fSBrad Larson
elba_write_w(struct sdhci_host * host,u16 val,int reg)353b5dbcf1fSBrad Larson static void elba_write_w(struct sdhci_host *host, u16 val, int reg)
354b5dbcf1fSBrad Larson {
355b5dbcf1fSBrad Larson struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
356b5dbcf1fSBrad Larson u32 shift = reg & GENMASK(1, 0);
357b5dbcf1fSBrad Larson unsigned long flags;
358b5dbcf1fSBrad Larson u32 byte_enables;
359b5dbcf1fSBrad Larson
360b5dbcf1fSBrad Larson byte_enables = GENMASK(1, 0) << shift;
361b5dbcf1fSBrad Larson spin_lock_irqsave(&priv->wrlock, flags);
362b5dbcf1fSBrad Larson writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
363b5dbcf1fSBrad Larson writew(val, host->ioaddr + reg);
364b5dbcf1fSBrad Larson spin_unlock_irqrestore(&priv->wrlock, flags);
365b5dbcf1fSBrad Larson }
366b5dbcf1fSBrad Larson
elba_write_b(struct sdhci_host * host,u8 val,int reg)367b5dbcf1fSBrad Larson static void elba_write_b(struct sdhci_host *host, u8 val, int reg)
368b5dbcf1fSBrad Larson {
369b5dbcf1fSBrad Larson struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
370b5dbcf1fSBrad Larson u32 shift = reg & GENMASK(1, 0);
371b5dbcf1fSBrad Larson unsigned long flags;
372b5dbcf1fSBrad Larson u32 byte_enables;
373b5dbcf1fSBrad Larson
374b5dbcf1fSBrad Larson byte_enables = BIT(0) << shift;
375b5dbcf1fSBrad Larson spin_lock_irqsave(&priv->wrlock, flags);
376b5dbcf1fSBrad Larson writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
377b5dbcf1fSBrad Larson writeb(val, host->ioaddr + reg);
378b5dbcf1fSBrad Larson spin_unlock_irqrestore(&priv->wrlock, flags);
379b5dbcf1fSBrad Larson }
380b5dbcf1fSBrad Larson
381b5dbcf1fSBrad Larson static const struct sdhci_ops sdhci_elba_ops = {
382b5dbcf1fSBrad Larson .write_l = elba_write_l,
383b5dbcf1fSBrad Larson .write_w = elba_write_w,
384b5dbcf1fSBrad Larson .write_b = elba_write_b,
385b5dbcf1fSBrad Larson .set_clock = sdhci_set_clock,
386b5dbcf1fSBrad Larson .get_timeout_clock = sdhci_cdns_get_timeout_clock,
387b5dbcf1fSBrad Larson .set_bus_width = sdhci_set_bus_width,
388b5dbcf1fSBrad Larson .reset = sdhci_reset,
389b5dbcf1fSBrad Larson .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
390b5dbcf1fSBrad Larson };
391b5dbcf1fSBrad Larson
elba_drv_init(struct platform_device * pdev)392b5dbcf1fSBrad Larson static int elba_drv_init(struct platform_device *pdev)
393b5dbcf1fSBrad Larson {
394b5dbcf1fSBrad Larson struct sdhci_host *host = platform_get_drvdata(pdev);
395b5dbcf1fSBrad Larson struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
396b5dbcf1fSBrad Larson void __iomem *ioaddr;
397b5dbcf1fSBrad Larson
398b5dbcf1fSBrad Larson host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA;
399b5dbcf1fSBrad Larson spin_lock_init(&priv->wrlock);
400b5dbcf1fSBrad Larson
401b5dbcf1fSBrad Larson /* Byte-lane control register */
402b5dbcf1fSBrad Larson ioaddr = devm_platform_ioremap_resource(pdev, 1);
403b5dbcf1fSBrad Larson if (IS_ERR(ioaddr))
404b5dbcf1fSBrad Larson return PTR_ERR(ioaddr);
405b5dbcf1fSBrad Larson
406b5dbcf1fSBrad Larson priv->ctl_addr = ioaddr;
407b5dbcf1fSBrad Larson priv->priv_writel = elba_priv_writel;
408b5dbcf1fSBrad Larson writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
409b5dbcf1fSBrad Larson
410b5dbcf1fSBrad Larson return 0;
411b5dbcf1fSBrad Larson }
412b5dbcf1fSBrad Larson
413ff6af28fSMasahiro Yamada static const struct sdhci_ops sdhci_cdns_ops = {
414ff6af28fSMasahiro Yamada .set_clock = sdhci_set_clock,
415ff6af28fSMasahiro Yamada .get_timeout_clock = sdhci_cdns_get_timeout_clock,
416ff6af28fSMasahiro Yamada .set_bus_width = sdhci_set_bus_width,
417ff6af28fSMasahiro Yamada .reset = sdhci_reset,
418adc40a51SMasahiro Yamada .platform_execute_tuning = sdhci_cdns_execute_tuning,
419ff6af28fSMasahiro Yamada .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
420ff6af28fSMasahiro Yamada };
421ff6af28fSMasahiro Yamada
422e095b78eSBrad Larson static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
423e095b78eSBrad Larson .pltfm_data = {
42418b587b4SMasahiro Yamada .ops = &sdhci_cdns_ops,
42518b587b4SMasahiro Yamada .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
426e095b78eSBrad Larson },
42718b587b4SMasahiro Yamada };
42818b587b4SMasahiro Yamada
429b5dbcf1fSBrad Larson static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = {
430b5dbcf1fSBrad Larson .init = elba_drv_init,
431b5dbcf1fSBrad Larson .pltfm_data = {
432b5dbcf1fSBrad Larson .ops = &sdhci_elba_ops,
433b5dbcf1fSBrad Larson },
434b5dbcf1fSBrad Larson };
435b5dbcf1fSBrad Larson
436e095b78eSBrad Larson static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = {
437e095b78eSBrad Larson .pltfm_data = {
438ff6af28fSMasahiro Yamada .ops = &sdhci_cdns_ops,
439e095b78eSBrad Larson },
440ff6af28fSMasahiro Yamada };
441ff6af28fSMasahiro Yamada
sdhci_cdns_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)442d12990f9SPiotr Sroka static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
443d12990f9SPiotr Sroka struct mmc_ios *ios)
444d12990f9SPiotr Sroka {
445d12990f9SPiotr Sroka struct sdhci_host *host = mmc_priv(mmc);
446d12990f9SPiotr Sroka struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
447d12990f9SPiotr Sroka u32 mode;
448d12990f9SPiotr Sroka
449d12990f9SPiotr Sroka priv->enhanced_strobe = ios->enhanced_strobe;
450d12990f9SPiotr Sroka
451d12990f9SPiotr Sroka mode = sdhci_cdns_get_emmc_mode(priv);
452d12990f9SPiotr Sroka
453d12990f9SPiotr Sroka if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
454d12990f9SPiotr Sroka sdhci_cdns_set_emmc_mode(priv,
455d12990f9SPiotr Sroka SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
456d12990f9SPiotr Sroka
457d12990f9SPiotr Sroka if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
458d12990f9SPiotr Sroka sdhci_cdns_set_emmc_mode(priv,
459d12990f9SPiotr Sroka SDHCI_CDNS_HRS06_MODE_MMC_HS400);
460d12990f9SPiotr Sroka }
461d12990f9SPiotr Sroka
sdhci_cdns_mmc_hw_reset(struct mmc_host * mmc)462aad53d4eSBrad Larson static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc)
463aad53d4eSBrad Larson {
464aad53d4eSBrad Larson struct sdhci_host *host = mmc_priv(mmc);
465aad53d4eSBrad Larson struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
466aad53d4eSBrad Larson
467aad53d4eSBrad Larson dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n");
468aad53d4eSBrad Larson
469aad53d4eSBrad Larson reset_control_assert(priv->rst_hw);
470aad53d4eSBrad Larson /* For eMMC, minimum is 1us but give it 3us for good measure */
471aad53d4eSBrad Larson udelay(3);
472aad53d4eSBrad Larson
473aad53d4eSBrad Larson reset_control_deassert(priv->rst_hw);
474aad53d4eSBrad Larson /* For eMMC, minimum is 200us but give it 300us for good measure */
475aad53d4eSBrad Larson usleep_range(300, 1000);
476aad53d4eSBrad Larson }
477aad53d4eSBrad Larson
sdhci_cdns_probe(struct platform_device * pdev)478ff6af28fSMasahiro Yamada static int sdhci_cdns_probe(struct platform_device *pdev)
479ff6af28fSMasahiro Yamada {
480ff6af28fSMasahiro Yamada struct sdhci_host *host;
481e095b78eSBrad Larson const struct sdhci_cdns_drv_data *data;
482ff6af28fSMasahiro Yamada struct sdhci_pltfm_host *pltfm_host;
483ff6af28fSMasahiro Yamada struct sdhci_cdns_priv *priv;
484ff6af28fSMasahiro Yamada struct clk *clk;
485a232a8f2SMasahiro Yamada unsigned int nr_phy_params;
486ff6af28fSMasahiro Yamada int ret;
487a89c472dSPiotr Sroka struct device *dev = &pdev->dev;
48812a632e6SMasahiro Yamada static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
489ff6af28fSMasahiro Yamada
490*6996beabSAdrian Hunter clk = devm_clk_get_enabled(dev, NULL);
491ff6af28fSMasahiro Yamada if (IS_ERR(clk))
492ff6af28fSMasahiro Yamada return PTR_ERR(clk);
493ff6af28fSMasahiro Yamada
49418b587b4SMasahiro Yamada data = of_device_get_match_data(dev);
49518b587b4SMasahiro Yamada if (!data)
496e095b78eSBrad Larson data = &sdhci_cdns_drv_data;
49718b587b4SMasahiro Yamada
498a232a8f2SMasahiro Yamada nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
499e095b78eSBrad Larson host = sdhci_pltfm_init(pdev, &data->pltfm_data,
500159a8b46SGustavo A. R. Silva struct_size(priv, phy_params, nr_phy_params));
501*6996beabSAdrian Hunter if (IS_ERR(host))
502*6996beabSAdrian Hunter return PTR_ERR(host);
503ff6af28fSMasahiro Yamada
504ff6af28fSMasahiro Yamada pltfm_host = sdhci_priv(host);
505ff6af28fSMasahiro Yamada pltfm_host->clk = clk;
506ff6af28fSMasahiro Yamada
507a232a8f2SMasahiro Yamada priv = sdhci_pltfm_priv(pltfm_host);
508a232a8f2SMasahiro Yamada priv->nr_phy_params = nr_phy_params;
509ff6af28fSMasahiro Yamada priv->hrs_addr = host->ioaddr;
510d12990f9SPiotr Sroka priv->enhanced_strobe = false;
511d3e32f84SBrad Larson priv->priv_writel = cdns_writel;
512ff6af28fSMasahiro Yamada host->ioaddr += SDHCI_CDNS_SRS_BASE;
513d12990f9SPiotr Sroka host->mmc_host_ops.hs400_enhanced_strobe =
514d12990f9SPiotr Sroka sdhci_cdns_hs400_enhanced_strobe;
515e095b78eSBrad Larson if (data->init) {
516e095b78eSBrad Larson ret = data->init(pdev);
517e095b78eSBrad Larson if (ret)
518e095b78eSBrad Larson goto free;
519e095b78eSBrad Larson }
520e73a3896SMasahiro Yamada sdhci_enable_v4_mode(host);
52112a632e6SMasahiro Yamada __sdhci_read_caps(host, &version, NULL, NULL);
522ff6af28fSMasahiro Yamada
523861183f1SPiotr Sroka sdhci_get_of_property(pdev);
524861183f1SPiotr Sroka
525ff6af28fSMasahiro Yamada ret = mmc_of_parse(host->mmc);
526ff6af28fSMasahiro Yamada if (ret)
527ff6af28fSMasahiro Yamada goto free;
528ff6af28fSMasahiro Yamada
529a232a8f2SMasahiro Yamada sdhci_cdns_phy_param_parse(dev->of_node, priv);
530a232a8f2SMasahiro Yamada
531a232a8f2SMasahiro Yamada ret = sdhci_cdns_phy_init(priv);
532a89c472dSPiotr Sroka if (ret)
533a89c472dSPiotr Sroka goto free;
534ff6af28fSMasahiro Yamada
535aad53d4eSBrad Larson if (host->mmc->caps & MMC_CAP_HW_RESET) {
536aad53d4eSBrad Larson priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL);
537e5bce3c1SChristophe JAILLET if (IS_ERR(priv->rst_hw)) {
538e5bce3c1SChristophe JAILLET ret = dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw),
539aad53d4eSBrad Larson "reset controller error\n");
540e5bce3c1SChristophe JAILLET goto free;
541e5bce3c1SChristophe JAILLET }
542aad53d4eSBrad Larson if (priv->rst_hw)
543aad53d4eSBrad Larson host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset;
544aad53d4eSBrad Larson }
545aad53d4eSBrad Larson
546ff6af28fSMasahiro Yamada ret = sdhci_add_host(host);
547ff6af28fSMasahiro Yamada if (ret)
548ff6af28fSMasahiro Yamada goto free;
549ff6af28fSMasahiro Yamada
550ff6af28fSMasahiro Yamada return 0;
551ff6af28fSMasahiro Yamada free:
552ff6af28fSMasahiro Yamada sdhci_pltfm_free(pdev);
553ff6af28fSMasahiro Yamada return ret;
554ff6af28fSMasahiro Yamada }
555ff6af28fSMasahiro Yamada
556a232a8f2SMasahiro Yamada #ifdef CONFIG_PM_SLEEP
sdhci_cdns_resume(struct device * dev)557a232a8f2SMasahiro Yamada static int sdhci_cdns_resume(struct device *dev)
558a232a8f2SMasahiro Yamada {
559a232a8f2SMasahiro Yamada struct sdhci_host *host = dev_get_drvdata(dev);
560a232a8f2SMasahiro Yamada struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
561a232a8f2SMasahiro Yamada struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
562a232a8f2SMasahiro Yamada int ret;
563a232a8f2SMasahiro Yamada
564a232a8f2SMasahiro Yamada ret = clk_prepare_enable(pltfm_host->clk);
565a232a8f2SMasahiro Yamada if (ret)
566a232a8f2SMasahiro Yamada return ret;
567a232a8f2SMasahiro Yamada
568a232a8f2SMasahiro Yamada ret = sdhci_cdns_phy_init(priv);
569a232a8f2SMasahiro Yamada if (ret)
570a232a8f2SMasahiro Yamada goto disable_clk;
571a232a8f2SMasahiro Yamada
572a232a8f2SMasahiro Yamada ret = sdhci_resume_host(host);
573a232a8f2SMasahiro Yamada if (ret)
574a232a8f2SMasahiro Yamada goto disable_clk;
575a232a8f2SMasahiro Yamada
576a232a8f2SMasahiro Yamada return 0;
577a232a8f2SMasahiro Yamada
578a232a8f2SMasahiro Yamada disable_clk:
579a232a8f2SMasahiro Yamada clk_disable_unprepare(pltfm_host->clk);
580a232a8f2SMasahiro Yamada
581a232a8f2SMasahiro Yamada return ret;
582a232a8f2SMasahiro Yamada }
583a232a8f2SMasahiro Yamada #endif
584a232a8f2SMasahiro Yamada
585a232a8f2SMasahiro Yamada static const struct dev_pm_ops sdhci_cdns_pm_ops = {
58683a7b32aSMasahiro Yamada SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
587a232a8f2SMasahiro Yamada };
588a232a8f2SMasahiro Yamada
589ff6af28fSMasahiro Yamada static const struct of_device_id sdhci_cdns_match[] = {
59018b587b4SMasahiro Yamada {
59118b587b4SMasahiro Yamada .compatible = "socionext,uniphier-sd4hc",
592e095b78eSBrad Larson .data = &sdhci_cdns_uniphier_drv_data,
59318b587b4SMasahiro Yamada },
594b5dbcf1fSBrad Larson {
595b5dbcf1fSBrad Larson .compatible = "amd,pensando-elba-sd4hc",
596b5dbcf1fSBrad Larson .data = &sdhci_elba_drv_data,
597b5dbcf1fSBrad Larson },
598ff6af28fSMasahiro Yamada { .compatible = "cdns,sd4hc" },
599ff6af28fSMasahiro Yamada { /* sentinel */ }
600ff6af28fSMasahiro Yamada };
601ff6af28fSMasahiro Yamada MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
602ff6af28fSMasahiro Yamada
603ff6af28fSMasahiro Yamada static struct platform_driver sdhci_cdns_driver = {
604ff6af28fSMasahiro Yamada .driver = {
605ff6af28fSMasahiro Yamada .name = "sdhci-cdns",
6067320915cSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
607a232a8f2SMasahiro Yamada .pm = &sdhci_cdns_pm_ops,
608ff6af28fSMasahiro Yamada .of_match_table = sdhci_cdns_match,
609ff6af28fSMasahiro Yamada },
610ff6af28fSMasahiro Yamada .probe = sdhci_cdns_probe,
611*6996beabSAdrian Hunter .remove_new = sdhci_pltfm_remove,
612ff6af28fSMasahiro Yamada };
613ff6af28fSMasahiro Yamada module_platform_driver(sdhci_cdns_driver);
614ff6af28fSMasahiro Yamada
615ff6af28fSMasahiro Yamada MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
616ff6af28fSMasahiro Yamada MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
617ff6af28fSMasahiro Yamada MODULE_LICENSE("GPL");
618