Lines Matching +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy
4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
123 #define E1000_STATUS 0x00008 /* Device Status - RO */
124 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
125 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
126 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
127 #define E1000_FLA 0x0001C /* Flash Access - RW */
128 #define E1000_MDIC 0x00020 /* MDI Control - RW */
129 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
130 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
131 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
132 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
133 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
134 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
135 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
136 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
137 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
139 #define E1000_RCTL 0x00100 /* RX Control - RW */
140 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
141 #define E1000_TCTL 0x00400 /* TX Control - RW */
142 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
143 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
144 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
152 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
154 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
155 #define E1000_RDFH 0x02410 /* Receive Data FIFO Head Register - RW */
157 #define E1000_RDFT 0x02418 /* Receive Data FIFO Tail Register - RW */
159 #define E1000_RDFHS 0x02420 /* Receive Data FIFO Head Saved Register - RW */
160 #define E1000_RDFTS 0x02428 /* Receive Data FIFO Tail Saved Register - RW */
161 #define E1000_RDFPC 0x02430 /* Receive Data FIFO Packet Count - RW */
162 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
164 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
166 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
167 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
168 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
169 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
170 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
171 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
172 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
173 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
174 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
175 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
176 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
177 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
178 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
179 #define E1000_DC 0x04030 /* Defer Count - R/clr */
180 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
181 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
182 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
183 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
184 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
185 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
186 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
187 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
188 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
189 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
190 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
191 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
192 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
193 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
194 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
195 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
196 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
197 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
198 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
199 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
200 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
201 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
202 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
203 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
204 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
205 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
206 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
207 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
208 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
209 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
210 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
211 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
212 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
213 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
214 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
215 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
216 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
217 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
218 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
219 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
220 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
221 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
222 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
223 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
227 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
233 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
234 #define E1000_RA 0x05400 /* Receive Address - RW Array */
236 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
238 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
239 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
240 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
241 #define E1000_MANC 0x05820 /* Management Control - RW */
242 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
243 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
244 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
245 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
246 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
247 #define E1000_MFVAL 0x05824 /* Manageability Filters Valid - RW */
248 #define E1000_MDEF 0x05890 /* Manageability Decision Filters - RW Array */
249 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
250 #define E1000_FTFT 0x09400 /* Flexible TCO Filter Table - RW Array */
252 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
253 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
255 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
256 #define E1000_FUNCTAG 0x05B08 /* Function-Tag Register */
257 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
258 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
259 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
260 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
268 #define E1000_PBACLR 0x05B68 /* MSI-X PBA Clear */
270 #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
271 #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
272 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
273 #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
274 #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
275 #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
276 #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
277 #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */
278 #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */
279 #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
280 #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
281 #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
282 #define E1000_TIMADJL 0x0B60C /* Time Adjustment Offset register Low - RW */
283 #define E1000_TIMADJH 0x0B610 /* Time Adjustment Offset register High - RW */
286 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
287 #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
288 #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
290 #define E1000_RETA_IDX(hash) ((hash) & (BIT(7) - 1))
525 #define E1000_EERW_ADDR_MASK ((1L << 14) - 1)
527 #define E1000_EERW_DATA_MASK ((1L << 16) - 1)
538 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
540 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
550 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
558 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
567 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
568 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
569 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
570 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
577 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
586 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
603 * (0-small, 1-large) */
604 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
640 /* Rx Interrupt Delay Timer */
643 /* Tx Interrupt Delay Timer */
646 /* Delay increments in nanoseconds for delayed interrupts registers */
649 /* Delay increments in nanoseconds for interrupt throttling registers */
652 /* EEPROM Commands - Microwire */
680 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
707 /* 3GIO Control Register - GCR (0x05B00; RW) */
718 /* MSI-X PBA Clear register */
719 #define E1000_PBACLR_VALID_MASK (BIT(5) - 1)
729 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
752 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
753 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
756 /* Legacy Receive Descriptor */
794 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
796 /* Receive Descriptor - Packet Split */
820 /* length of buffers 1-3 */
845 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
920 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
921 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
922 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
933 /*for ARP packets - in 82574 */
938 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
963 /* I/O-Mapped Access to Internal Registers, Memories, and Flash */