17c008829SNicholas Kazlauskas /*
27c008829SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc.
37c008829SNicholas Kazlauskas *
47c008829SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a
57c008829SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"),
67c008829SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation
77c008829SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87c008829SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the
97c008829SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions:
107c008829SNicholas Kazlauskas *
117c008829SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in
127c008829SNicholas Kazlauskas * all copies or substantial portions of the Software.
137c008829SNicholas Kazlauskas *
147c008829SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
157c008829SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
167c008829SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
177c008829SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
187c008829SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
197c008829SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
207c008829SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE.
217c008829SNicholas Kazlauskas *
227c008829SNicholas Kazlauskas * Authors: AMD
237c008829SNicholas Kazlauskas *
247c008829SNicholas Kazlauskas */
257c008829SNicholas Kazlauskas
265624c345SAnthony Koo #ifndef DMUB_CMD_H
275624c345SAnthony Koo #define DMUB_CMD_H
287c008829SNicholas Kazlauskas
298b19a4e3SAnthony Koo #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
308b19a4e3SAnthony Koo #include "dmub_fw_types.h"
318b19a4e3SAnthony Koo #include "include_legacy/atomfirmware.h"
328b19a4e3SAnthony Koo
338b19a4e3SAnthony Koo #if defined(_TEST_HARNESS)
348b19a4e3SAnthony Koo #include <string.h>
358b19a4e3SAnthony Koo #endif
368b19a4e3SAnthony Koo #else
378b19a4e3SAnthony Koo
3884034ad4SAnthony Koo #include <asm/byteorder.h>
3984034ad4SAnthony Koo #include <linux/types.h>
4084034ad4SAnthony Koo #include <linux/string.h>
4184034ad4SAnthony Koo #include <linux/delay.h>
4284034ad4SAnthony Koo
437c008829SNicholas Kazlauskas #include "atomfirmware.h"
4422aa5614SYongqiang Sun
458b19a4e3SAnthony Koo #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
468b19a4e3SAnthony Koo
4784034ad4SAnthony Koo //<DMUB_TYPES>==================================================================
4884034ad4SAnthony Koo /* Basic type definitions. */
4984034ad4SAnthony Koo
508b19a4e3SAnthony Koo #define __forceinline inline
518b19a4e3SAnthony Koo
521a595f28SAnthony Koo /**
531a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled gradually
541a595f28SAnthony Koo * by slowly reversing all backlight programming and pixel compensation.
551a595f28SAnthony Koo */
5684034ad4SAnthony Koo #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
571a595f28SAnthony Koo
581a595f28SAnthony Koo /**
591a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately
601a595f28SAnthony Koo * and undo all backlight programming and pixel compensation.
611a595f28SAnthony Koo */
6284034ad4SAnthony Koo #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
631a595f28SAnthony Koo
641a595f28SAnthony Koo /**
651a595f28SAnthony Koo * Flag from driver to indicate that ABM should be disabled immediately
661a595f28SAnthony Koo * and keep the current backlight programming and pixel compensation.
671a595f28SAnthony Koo */
68d9beecfcSAnthony Koo #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
691a595f28SAnthony Koo
701a595f28SAnthony Koo /**
711a595f28SAnthony Koo * Flag from driver to set the current ABM pipe index or ABM operating level.
721a595f28SAnthony Koo */
7384034ad4SAnthony Koo #define SET_ABM_PIPE_NORMAL 1
7484034ad4SAnthony Koo
751a595f28SAnthony Koo /**
761a595f28SAnthony Koo * Number of ambient light levels in ABM algorithm.
771a595f28SAnthony Koo */
781a595f28SAnthony Koo #define NUM_AMBI_LEVEL 5
791a595f28SAnthony Koo
801a595f28SAnthony Koo /**
811a595f28SAnthony Koo * Number of operating/aggression levels in ABM algorithm.
821a595f28SAnthony Koo */
831a595f28SAnthony Koo #define NUM_AGGR_LEVEL 4
841a595f28SAnthony Koo
851a595f28SAnthony Koo /**
861a595f28SAnthony Koo * Number of segments in the gamma curve.
871a595f28SAnthony Koo */
881a595f28SAnthony Koo #define NUM_POWER_FN_SEGS 8
891a595f28SAnthony Koo
901a595f28SAnthony Koo /**
911a595f28SAnthony Koo * Number of segments in the backlight curve.
921a595f28SAnthony Koo */
931a595f28SAnthony Koo #define NUM_BL_CURVE_SEGS 16
941a595f28SAnthony Koo
9585f4bc0cSAlvin Lee /* Maximum number of SubVP streams */
9685f4bc0cSAlvin Lee #define DMUB_MAX_SUBVP_STREAMS 2
9785f4bc0cSAlvin Lee
98d3981ee7SAnthony Koo /* Define max FPO streams as 4 for now. Current implementation today
99d3981ee7SAnthony Koo * only supports 1, but could be more in the future. Reduce array
100d3981ee7SAnthony Koo * size to ensure the command size remains less than 64 bytes if
101d3981ee7SAnthony Koo * adding new fields.
102d3981ee7SAnthony Koo */
103d3981ee7SAnthony Koo #define DMUB_MAX_FPO_STREAMS 4
104d3981ee7SAnthony Koo
10584034ad4SAnthony Koo /* Maximum number of streams on any ASIC. */
10684034ad4SAnthony Koo #define DMUB_MAX_STREAMS 6
10784034ad4SAnthony Koo
10884034ad4SAnthony Koo /* Maximum number of planes on any ASIC. */
10984034ad4SAnthony Koo #define DMUB_MAX_PLANES 6
11084034ad4SAnthony Koo
11170732504SYongqiang Sun /* Trace buffer offset for entry */
11270732504SYongqiang Sun #define TRACE_BUFFER_ENTRY_OFFSET 16
11370732504SYongqiang Sun
114592a6318SAnthony Koo /**
11583eb5385SDavid Zhang * Maximum number of dirty rects supported by FW.
11683eb5385SDavid Zhang */
11783eb5385SDavid Zhang #define DMUB_MAX_DIRTY_RECTS 3
11883eb5385SDavid Zhang
11983eb5385SDavid Zhang /**
120f56c837aSMikita Lipski *
121f56c837aSMikita Lipski * PSR control version legacy
122f56c837aSMikita Lipski */
123f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
124f56c837aSMikita Lipski /**
125f56c837aSMikita Lipski * PSR control version with multi edp support
126f56c837aSMikita Lipski */
127f56c837aSMikita Lipski #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
128f56c837aSMikita Lipski
129f56c837aSMikita Lipski
130f56c837aSMikita Lipski /**
13163de4f04SJake Wang * ABM control version legacy
132e922057bSJake Wang */
13363de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
134e922057bSJake Wang
135e922057bSJake Wang /**
13663de4f04SJake Wang * ABM control version with multi edp support
137e922057bSJake Wang */
13863de4f04SJake Wang #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
139e922057bSJake Wang
140e922057bSJake Wang /**
141592a6318SAnthony Koo * Physical framebuffer address location, 64-bit.
142592a6318SAnthony Koo */
14384034ad4SAnthony Koo #ifndef PHYSICAL_ADDRESS_LOC
14484034ad4SAnthony Koo #define PHYSICAL_ADDRESS_LOC union large_integer
14584034ad4SAnthony Koo #endif
14684034ad4SAnthony Koo
147e721611bSAnthony Koo /**
148e721611bSAnthony Koo * OS/FW agnostic memcpy
149e721611bSAnthony Koo */
150e721611bSAnthony Koo #ifndef dmub_memcpy
151e721611bSAnthony Koo #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
152e721611bSAnthony Koo #endif
153e721611bSAnthony Koo
154e721611bSAnthony Koo /**
155e721611bSAnthony Koo * OS/FW agnostic memset
156e721611bSAnthony Koo */
157e721611bSAnthony Koo #ifndef dmub_memset
158e721611bSAnthony Koo #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
159e721611bSAnthony Koo #endif
160e721611bSAnthony Koo
161e721611bSAnthony Koo #if defined(__cplusplus)
162e721611bSAnthony Koo extern "C" {
163e721611bSAnthony Koo #endif
164e721611bSAnthony Koo
165e721611bSAnthony Koo /**
166e721611bSAnthony Koo * OS/FW agnostic udelay
167e721611bSAnthony Koo */
168e721611bSAnthony Koo #ifndef dmub_udelay
169e721611bSAnthony Koo #define dmub_udelay(microseconds) udelay(microseconds)
170e721611bSAnthony Koo #endif
171e721611bSAnthony Koo
172e721611bSAnthony Koo #pragma pack(push, 1)
173da915efaSReza Amini #define ABM_NUM_OF_ACE_SEGMENTS 5
174da915efaSReza Amini
175da915efaSReza Amini union abm_flags {
176da915efaSReza Amini struct {
177da915efaSReza Amini /**
178519e3637SReza Amini * @abm_enabled: Indicates if ABM is enabled.
179da915efaSReza Amini */
180da915efaSReza Amini unsigned int abm_enabled : 1;
181da915efaSReza Amini
182da915efaSReza Amini /**
183519e3637SReza Amini * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
184da915efaSReza Amini */
185da915efaSReza Amini unsigned int disable_abm_requested : 1;
186da915efaSReza Amini
187da915efaSReza Amini /**
188519e3637SReza Amini * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled
189519e3637SReza Amini * immediately.
190da915efaSReza Amini */
191da915efaSReza Amini unsigned int disable_abm_immediately : 1;
192da915efaSReza Amini
193da915efaSReza Amini /**
194519e3637SReza Amini * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
195da915efaSReza Amini * to be disabled immediately and keep gain.
196da915efaSReza Amini */
197da915efaSReza Amini unsigned int disable_abm_immediate_keep_gain : 1;
198da915efaSReza Amini
199da915efaSReza Amini /**
200519e3637SReza Amini * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
201da915efaSReza Amini */
202da915efaSReza Amini unsigned int fractional_pwm : 1;
203da915efaSReza Amini
204da915efaSReza Amini /**
205519e3637SReza Amini * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
206da915efaSReza Amini * of user backlight level.
207da915efaSReza Amini */
208da915efaSReza Amini unsigned int abm_gradual_bl_change : 1;
209da915efaSReza Amini } bitfields;
210da915efaSReza Amini
211519e3637SReza Amini unsigned int u32All;
212da915efaSReza Amini };
213da915efaSReza Amini
214da915efaSReza Amini struct abm_save_restore {
215da915efaSReza Amini /**
216da915efaSReza Amini * @flags: Misc. ABM flags.
217da915efaSReza Amini */
218da915efaSReza Amini union abm_flags flags;
219da915efaSReza Amini
220da915efaSReza Amini /**
221da915efaSReza Amini * @pause: true: pause ABM and get state
222519e3637SReza Amini * false: unpause ABM after setting state
223da915efaSReza Amini */
224da915efaSReza Amini uint32_t pause;
225da915efaSReza Amini
226da915efaSReza Amini /**
227da915efaSReza Amini * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
228da915efaSReza Amini */
229da915efaSReza Amini uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
230da915efaSReza Amini
231da915efaSReza Amini /**
232da915efaSReza Amini * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
233da915efaSReza Amini */
234da915efaSReza Amini uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
235da915efaSReza Amini
236da915efaSReza Amini /**
237da915efaSReza Amini * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
238da915efaSReza Amini */
239da915efaSReza Amini uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
240da915efaSReza Amini
241da915efaSReza Amini
242da915efaSReza Amini /**
243da915efaSReza Amini * @knee_threshold: Current x-position of ACE knee (u0.16).
244da915efaSReza Amini */
245da915efaSReza Amini uint32_t knee_threshold;
246da915efaSReza Amini /**
247da915efaSReza Amini * @current_gain: Current backlight reduction (u16.16).
248da915efaSReza Amini */
249da915efaSReza Amini uint32_t current_gain;
250da915efaSReza Amini /**
251da915efaSReza Amini * @curr_bl_level: Current actual backlight level converging to target backlight level.
252da915efaSReza Amini */
253da915efaSReza Amini uint16_t curr_bl_level;
254da915efaSReza Amini
255da915efaSReza Amini /**
256da915efaSReza Amini * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
257da915efaSReza Amini */
258da915efaSReza Amini uint16_t curr_user_bl_level;
259da915efaSReza Amini
260da915efaSReza Amini };
261da915efaSReza Amini
262592a6318SAnthony Koo /**
263592a6318SAnthony Koo * union dmub_addr - DMUB physical/virtual 64-bit address.
264592a6318SAnthony Koo */
26584034ad4SAnthony Koo union dmub_addr {
26684034ad4SAnthony Koo struct {
267592a6318SAnthony Koo uint32_t low_part; /**< Lower 32 bits */
268592a6318SAnthony Koo uint32_t high_part; /**< Upper 32 bits */
269592a6318SAnthony Koo } u; /*<< Low/high bit access */
270592a6318SAnthony Koo uint64_t quad_part; /*<< 64 bit address */
27184034ad4SAnthony Koo };
2726e60cba6SJonathan Gray #pragma pack(pop)
27384034ad4SAnthony Koo
2741a595f28SAnthony Koo /**
27583eb5385SDavid Zhang * Dirty rect definition.
27683eb5385SDavid Zhang */
27783eb5385SDavid Zhang struct dmub_rect {
27883eb5385SDavid Zhang /**
27983eb5385SDavid Zhang * Dirty rect x offset.
28083eb5385SDavid Zhang */
28183eb5385SDavid Zhang uint32_t x;
28283eb5385SDavid Zhang
28383eb5385SDavid Zhang /**
28483eb5385SDavid Zhang * Dirty rect y offset.
28583eb5385SDavid Zhang */
28683eb5385SDavid Zhang uint32_t y;
28783eb5385SDavid Zhang
28883eb5385SDavid Zhang /**
28983eb5385SDavid Zhang * Dirty rect width.
29083eb5385SDavid Zhang */
29183eb5385SDavid Zhang uint32_t width;
29283eb5385SDavid Zhang
29383eb5385SDavid Zhang /**
29483eb5385SDavid Zhang * Dirty rect height.
29583eb5385SDavid Zhang */
29683eb5385SDavid Zhang uint32_t height;
29783eb5385SDavid Zhang };
29883eb5385SDavid Zhang
29983eb5385SDavid Zhang /**
3001a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour.
3011a595f28SAnthony Koo */
30284034ad4SAnthony Koo union dmub_psr_debug_flags {
3031a595f28SAnthony Koo /**
3041a595f28SAnthony Koo * Debug flags.
3051a595f28SAnthony Koo */
30684034ad4SAnthony Koo struct {
3071a595f28SAnthony Koo /**
3081a595f28SAnthony Koo * Enable visual confirm in FW.
3091a595f28SAnthony Koo */
310447f3d0fSAnthony Koo uint32_t visual_confirm : 1;
31183eb5385SDavid Zhang
31283eb5385SDavid Zhang /**
31383eb5385SDavid Zhang * Force all selective updates to bw full frame updates.
31483eb5385SDavid Zhang */
31583eb5385SDavid Zhang uint32_t force_full_frame_update : 1;
31683eb5385SDavid Zhang
3171a595f28SAnthony Koo /**
3181a595f28SAnthony Koo * Use HW Lock Mgr object to do HW locking in FW.
3191a595f28SAnthony Koo */
320447f3d0fSAnthony Koo uint32_t use_hw_lock_mgr : 1;
3211a595f28SAnthony Koo
3221a595f28SAnthony Koo /**
323548f2125SRobin Chen * Use TPS3 signal when restore main link.
3241a595f28SAnthony Koo */
325548f2125SRobin Chen uint32_t force_wakeup_by_tps3 : 1;
326cf472dbdSAnthony Koo
327cf472dbdSAnthony Koo /**
328cf472dbdSAnthony Koo * Back to back flip, therefore cannot power down PHY
329cf472dbdSAnthony Koo */
330cf472dbdSAnthony Koo uint32_t back_to_back_flip : 1;
331cf472dbdSAnthony Koo
33284034ad4SAnthony Koo } bitfields;
33384034ad4SAnthony Koo
3341a595f28SAnthony Koo /**
3351a595f28SAnthony Koo * Union for debug flags.
3361a595f28SAnthony Koo */
337447f3d0fSAnthony Koo uint32_t u32All;
33884034ad4SAnthony Koo };
33984034ad4SAnthony Koo
3401a595f28SAnthony Koo /**
341e0138644SBhawanpreet Lakha * Flags that can be set by driver to change some Replay behaviour.
342e0138644SBhawanpreet Lakha */
343e0138644SBhawanpreet Lakha union replay_debug_flags {
344e0138644SBhawanpreet Lakha struct {
345e0138644SBhawanpreet Lakha /**
346e0138644SBhawanpreet Lakha * Enable visual confirm in FW.
347e0138644SBhawanpreet Lakha */
348e0138644SBhawanpreet Lakha uint32_t visual_confirm : 1;
349e0138644SBhawanpreet Lakha
350e0138644SBhawanpreet Lakha /**
351e0138644SBhawanpreet Lakha * @skip_crc: Set if need to skip CRC.
352e0138644SBhawanpreet Lakha */
353e0138644SBhawanpreet Lakha uint32_t skip_crc : 1;
354e0138644SBhawanpreet Lakha
355e0138644SBhawanpreet Lakha /**
356e0138644SBhawanpreet Lakha * @force_link_power_on: Force disable ALPM control
357e0138644SBhawanpreet Lakha */
358e0138644SBhawanpreet Lakha uint32_t force_link_power_on : 1;
359e0138644SBhawanpreet Lakha
360e0138644SBhawanpreet Lakha /**
361e0138644SBhawanpreet Lakha * @force_phy_power_on: Force phy power on
362e0138644SBhawanpreet Lakha */
363e0138644SBhawanpreet Lakha uint32_t force_phy_power_on : 1;
364e0138644SBhawanpreet Lakha
365e0138644SBhawanpreet Lakha /**
366e0138644SBhawanpreet Lakha * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
367e0138644SBhawanpreet Lakha */
368e0138644SBhawanpreet Lakha uint32_t timing_resync_disabled : 1;
369e0138644SBhawanpreet Lakha
370e0138644SBhawanpreet Lakha /**
371e0138644SBhawanpreet Lakha * @skip_crtc_disabled: CRTC disable skipped
372e0138644SBhawanpreet Lakha */
373e0138644SBhawanpreet Lakha uint32_t skip_crtc_disabled : 1;
374e0138644SBhawanpreet Lakha
375e0138644SBhawanpreet Lakha /**
376e0138644SBhawanpreet Lakha * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
377e0138644SBhawanpreet Lakha */
378e0138644SBhawanpreet Lakha uint32_t force_defer_one_frame_update : 1;
379e0138644SBhawanpreet Lakha /**
380e0138644SBhawanpreet Lakha * @disable_delay_alpm_on: Force disable delay alpm on
381e0138644SBhawanpreet Lakha */
382e0138644SBhawanpreet Lakha uint32_t disable_delay_alpm_on : 1;
383e0138644SBhawanpreet Lakha /**
384e0138644SBhawanpreet Lakha * @disable_desync_error_check: Force disable desync error check
385e0138644SBhawanpreet Lakha */
386e0138644SBhawanpreet Lakha uint32_t disable_desync_error_check : 1;
387e0138644SBhawanpreet Lakha /**
388e0138644SBhawanpreet Lakha * @disable_desync_error_check: Force disable desync error check
389e0138644SBhawanpreet Lakha */
390e0138644SBhawanpreet Lakha uint32_t disable_dmub_save_restore : 1;
391e0138644SBhawanpreet Lakha
392e0138644SBhawanpreet Lakha uint32_t reserved : 22;
393e0138644SBhawanpreet Lakha } bitfields;
394e0138644SBhawanpreet Lakha
395e0138644SBhawanpreet Lakha uint32_t u32All;
396e0138644SBhawanpreet Lakha };
397e0138644SBhawanpreet Lakha
398e0138644SBhawanpreet Lakha union replay_hw_flags {
399e0138644SBhawanpreet Lakha struct {
400e0138644SBhawanpreet Lakha /**
401e0138644SBhawanpreet Lakha * @allow_alpm_fw_standby_mode: To indicate whether the
402e0138644SBhawanpreet Lakha * ALPM FW standby mode is allowed
403e0138644SBhawanpreet Lakha */
404e0138644SBhawanpreet Lakha uint32_t allow_alpm_fw_standby_mode : 1;
405e0138644SBhawanpreet Lakha
406e0138644SBhawanpreet Lakha /*
407e0138644SBhawanpreet Lakha * @dsc_enable_status: DSC enable status in driver
408e0138644SBhawanpreet Lakha */
409e0138644SBhawanpreet Lakha uint32_t dsc_enable_status : 1;
410e0138644SBhawanpreet Lakha
411e0138644SBhawanpreet Lakha /**
412e0138644SBhawanpreet Lakha * @fec_enable_status: receive fec enable/disable status from driver
413e0138644SBhawanpreet Lakha */
414e0138644SBhawanpreet Lakha uint32_t fec_enable_status : 1;
415e0138644SBhawanpreet Lakha
416e0138644SBhawanpreet Lakha /*
417e0138644SBhawanpreet Lakha * @smu_optimizations_en: SMU power optimization.
418e0138644SBhawanpreet Lakha * Only when active display is Replay capable and display enters Replay.
419e0138644SBhawanpreet Lakha * Trigger interrupt to SMU to powerup/down.
420e0138644SBhawanpreet Lakha */
421e0138644SBhawanpreet Lakha uint32_t smu_optimizations_en : 1;
422e0138644SBhawanpreet Lakha
423e0138644SBhawanpreet Lakha /**
424e0138644SBhawanpreet Lakha * @otg_powered_down: Flag to keep track of OTG power state.
425e0138644SBhawanpreet Lakha */
426e0138644SBhawanpreet Lakha uint32_t otg_powered_down : 1;
427e0138644SBhawanpreet Lakha
428e0138644SBhawanpreet Lakha /**
429e0138644SBhawanpreet Lakha * @phy_power_state: Indicates current phy power state
430e0138644SBhawanpreet Lakha */
431e0138644SBhawanpreet Lakha uint32_t phy_power_state : 1;
432e0138644SBhawanpreet Lakha
433e0138644SBhawanpreet Lakha /**
434e0138644SBhawanpreet Lakha * @link_power_state: Indicates current link power state
435e0138644SBhawanpreet Lakha */
436e0138644SBhawanpreet Lakha uint32_t link_power_state : 1;
437e0138644SBhawanpreet Lakha /**
438e0138644SBhawanpreet Lakha * Use TPS3 signal when restore main link.
439e0138644SBhawanpreet Lakha */
440e0138644SBhawanpreet Lakha uint32_t force_wakeup_by_tps3 : 1;
441e0138644SBhawanpreet Lakha } bitfields;
442e0138644SBhawanpreet Lakha
443e0138644SBhawanpreet Lakha uint32_t u32All;
444e0138644SBhawanpreet Lakha };
445e0138644SBhawanpreet Lakha
446e0138644SBhawanpreet Lakha /**
4470991f44cSAnthony Koo * DMUB visual confirm color
4481a595f28SAnthony Koo */
44934ba432cSAnthony Koo struct dmub_feature_caps {
4501a595f28SAnthony Koo /**
4511a595f28SAnthony Koo * Max PSR version supported by FW.
4521a595f28SAnthony Koo */
45334ba432cSAnthony Koo uint8_t psr;
45400fa7f03SRodrigo Siqueira uint8_t fw_assisted_mclk_switch;
455278d3de6SAlvin Lee uint8_t reserved[4];
45693aac179SAnthony Koo uint8_t subvp_psr_support;
457278d3de6SAlvin Lee uint8_t gecc_enable;
45834ba432cSAnthony Koo };
45934ba432cSAnthony Koo
460b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color {
461b09c1fffSLeo (Hanghong) Ma /**
462b09c1fffSLeo (Hanghong) Ma * Maximum 10 bits color value
463b09c1fffSLeo (Hanghong) Ma */
464b09c1fffSLeo (Hanghong) Ma uint16_t color_r_cr;
465b09c1fffSLeo (Hanghong) Ma uint16_t color_g_y;
466b09c1fffSLeo (Hanghong) Ma uint16_t color_b_cb;
467b09c1fffSLeo (Hanghong) Ma uint16_t panel_inst;
468b09c1fffSLeo (Hanghong) Ma };
469b09c1fffSLeo (Hanghong) Ma
47084034ad4SAnthony Koo #if defined(__cplusplus)
47184034ad4SAnthony Koo }
47284034ad4SAnthony Koo #endif
47384034ad4SAnthony Koo
47484034ad4SAnthony Koo //==============================================================================
47584034ad4SAnthony Koo //</DMUB_TYPES>=================================================================
47684034ad4SAnthony Koo //==============================================================================
47784034ad4SAnthony Koo //< DMUB_META>==================================================================
47884034ad4SAnthony Koo //==============================================================================
47984034ad4SAnthony Koo #pragma pack(push, 1)
48084034ad4SAnthony Koo
48184034ad4SAnthony Koo /* Magic value for identifying dmub_fw_meta_info */
48284034ad4SAnthony Koo #define DMUB_FW_META_MAGIC 0x444D5542
48384034ad4SAnthony Koo
48484034ad4SAnthony Koo /* Offset from the end of the file to the dmub_fw_meta_info */
48584034ad4SAnthony Koo #define DMUB_FW_META_OFFSET 0x24
48684034ad4SAnthony Koo
48784034ad4SAnthony Koo /**
48884034ad4SAnthony Koo * struct dmub_fw_meta_info - metadata associated with fw binary
48984034ad4SAnthony Koo *
49084034ad4SAnthony Koo * NOTE: This should be considered a stable API. Fields should
49184034ad4SAnthony Koo * not be repurposed or reordered. New fields should be
49284034ad4SAnthony Koo * added instead to extend the structure.
49384034ad4SAnthony Koo *
49484034ad4SAnthony Koo * @magic_value: magic value identifying DMUB firmware meta info
49584034ad4SAnthony Koo * @fw_region_size: size of the firmware state region
49684034ad4SAnthony Koo * @trace_buffer_size: size of the tracebuffer region
49784034ad4SAnthony Koo * @fw_version: the firmware version information
498b2265774SAnthony Koo * @dal_fw: 1 if the firmware is DAL
49984034ad4SAnthony Koo */
50084034ad4SAnthony Koo struct dmub_fw_meta_info {
501592a6318SAnthony Koo uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
502592a6318SAnthony Koo uint32_t fw_region_size; /**< size of the firmware state region */
503592a6318SAnthony Koo uint32_t trace_buffer_size; /**< size of the tracebuffer region */
504592a6318SAnthony Koo uint32_t fw_version; /**< the firmware version information */
505592a6318SAnthony Koo uint8_t dal_fw; /**< 1 if the firmware is DAL */
506592a6318SAnthony Koo uint8_t reserved[3]; /**< padding bits */
50784034ad4SAnthony Koo };
50884034ad4SAnthony Koo
509592a6318SAnthony Koo /**
510592a6318SAnthony Koo * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
511592a6318SAnthony Koo */
51284034ad4SAnthony Koo union dmub_fw_meta {
513592a6318SAnthony Koo struct dmub_fw_meta_info info; /**< metadata info */
514592a6318SAnthony Koo uint8_t reserved[64]; /**< padding bits */
51584034ad4SAnthony Koo };
51684034ad4SAnthony Koo
51784034ad4SAnthony Koo #pragma pack(pop)
518788408b7SAnthony Koo
51984034ad4SAnthony Koo //==============================================================================
5206b66208fSYongqiang Sun //< DMUB Trace Buffer>================================================================
5216b66208fSYongqiang Sun //==============================================================================
522592a6318SAnthony Koo /**
523592a6318SAnthony Koo * dmub_trace_code_t - firmware trace code, 32-bits
524592a6318SAnthony Koo */
5256b66208fSYongqiang Sun typedef uint32_t dmub_trace_code_t;
5266b66208fSYongqiang Sun
527592a6318SAnthony Koo /**
528592a6318SAnthony Koo * struct dmcub_trace_buf_entry - Firmware trace entry
529592a6318SAnthony Koo */
5306b66208fSYongqiang Sun struct dmcub_trace_buf_entry {
531592a6318SAnthony Koo dmub_trace_code_t trace_code; /**< trace code for the event */
532592a6318SAnthony Koo uint32_t tick_count; /**< the tick count at time of trace */
533592a6318SAnthony Koo uint32_t param0; /**< trace defined parameter 0 */
534592a6318SAnthony Koo uint32_t param1; /**< trace defined parameter 1 */
5356b66208fSYongqiang Sun };
5366b66208fSYongqiang Sun
5376b66208fSYongqiang Sun //==============================================================================
538788408b7SAnthony Koo //< DMUB_STATUS>================================================================
539788408b7SAnthony Koo //==============================================================================
540788408b7SAnthony Koo
541788408b7SAnthony Koo /**
542788408b7SAnthony Koo * DMCUB scratch registers can be used to determine firmware status.
543788408b7SAnthony Koo * Current scratch register usage is as follows:
544788408b7SAnthony Koo *
545492dd8a8SAnthony Koo * SCRATCH0: FW Boot Status register
546021eaef8SAnthony Koo * SCRATCH5: LVTMA Status Register
547492dd8a8SAnthony Koo * SCRATCH15: FW Boot Options register
548788408b7SAnthony Koo */
549788408b7SAnthony Koo
550592a6318SAnthony Koo /**
551592a6318SAnthony Koo * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
552592a6318SAnthony Koo */
553492dd8a8SAnthony Koo union dmub_fw_boot_status {
554492dd8a8SAnthony Koo struct {
555592a6318SAnthony Koo uint32_t dal_fw : 1; /**< 1 if DAL FW */
556592a6318SAnthony Koo uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
557592a6318SAnthony Koo uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
558592a6318SAnthony Koo uint32_t restore_required : 1; /**< 1 if driver should call restore */
55901934c30SAnthony Koo uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
560e3416e87SRodrigo Siqueira uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
56101934c30SAnthony Koo uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
5629dce8c2aSAnthony Koo uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
563592a6318SAnthony Koo } bits; /**< status bits */
564592a6318SAnthony Koo uint32_t all; /**< 32-bit access to status bits */
565492dd8a8SAnthony Koo };
566492dd8a8SAnthony Koo
567592a6318SAnthony Koo /**
568592a6318SAnthony Koo * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
569592a6318SAnthony Koo */
570492dd8a8SAnthony Koo enum dmub_fw_boot_status_bit {
571592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
572592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
573592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
574592a6318SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
5751e0958bbSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
576053065a4SAurabindo Pillai DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
57701934c30SAnthony Koo DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
5789dce8c2aSAnthony Koo DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
579492dd8a8SAnthony Koo };
580492dd8a8SAnthony Koo
581021eaef8SAnthony Koo /* Register bit definition for SCRATCH5 */
582021eaef8SAnthony Koo union dmub_lvtma_status {
583021eaef8SAnthony Koo struct {
584021eaef8SAnthony Koo uint32_t psp_ok : 1;
585021eaef8SAnthony Koo uint32_t edp_on : 1;
586021eaef8SAnthony Koo uint32_t reserved : 30;
587021eaef8SAnthony Koo } bits;
588021eaef8SAnthony Koo uint32_t all;
589021eaef8SAnthony Koo };
590021eaef8SAnthony Koo
591021eaef8SAnthony Koo enum dmub_lvtma_status_bit {
592021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
593021eaef8SAnthony Koo DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
594021eaef8SAnthony Koo };
595021eaef8SAnthony Koo
5966d7d0a4bSAnthony Koo enum dmub_ips_disable_type {
5976d7d0a4bSAnthony Koo DMUB_IPS_DISABLE_IPS1 = 1,
5986d7d0a4bSAnthony Koo DMUB_IPS_DISABLE_IPS2 = 2,
5996d7d0a4bSAnthony Koo DMUB_IPS_DISABLE_IPS2_Z10 = 3,
6006d7d0a4bSAnthony Koo };
6016d7d0a4bSAnthony Koo
602592a6318SAnthony Koo /**
6031e0958bbSAnthony Koo * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
604592a6318SAnthony Koo */
605492dd8a8SAnthony Koo union dmub_fw_boot_options {
606492dd8a8SAnthony Koo struct {
607592a6318SAnthony Koo uint32_t pemu_env : 1; /**< 1 if PEMU */
608592a6318SAnthony Koo uint32_t fpga_env : 1; /**< 1 if FPGA */
609592a6318SAnthony Koo uint32_t optimized_init : 1; /**< 1 if optimized init */
610592a6318SAnthony Koo uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
611592a6318SAnthony Koo uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
612592a6318SAnthony Koo uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
613b04cb192SNicholas Kazlauskas uint32_t z10_disable: 1; /**< 1 to disable z10 */
614b0ce6272SMeenakshikumar Somasundaram uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
6151e0958bbSAnthony Koo uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
6163137f792SHansen uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
6173137f792SHansen uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
6183137f792SHansen /**< 1 if all root clock gating is enabled and low power memory is enabled*/
6193137f792SHansen uint32_t power_optimization: 1;
620b129c94eSAnthony Koo uint32_t diag_env: 1; /* 1 if diagnostic environment */
6215cef7e8eSAnthony Koo uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
622ea5a4db9SAnthony Koo uint32_t usb4_cm_version: 1; /**< 1 CM support */
6236f4f8ff5SMeenakshikumar Somasundaram uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
62473f73741SAnthony Koo uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */
625c79503dcSAnthony Koo uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
62627664177SAnthony Koo uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
6276d7d0a4bSAnthony Koo uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
6286d7d0a4bSAnthony Koo uint32_t ips_disable: 2; /* options to disable ips support*/
6296d7d0a4bSAnthony Koo uint32_t reserved : 10; /**< reserved */
630592a6318SAnthony Koo } bits; /**< boot bits */
631592a6318SAnthony Koo uint32_t all; /**< 32-bit access to bits */
632492dd8a8SAnthony Koo };
633492dd8a8SAnthony Koo
634492dd8a8SAnthony Koo enum dmub_fw_boot_options_bit {
635592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
636592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
637592a6318SAnthony Koo DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
638492dd8a8SAnthony Koo };
639492dd8a8SAnthony Koo
640788408b7SAnthony Koo //==============================================================================
641788408b7SAnthony Koo //</DMUB_STATUS>================================================================
64284034ad4SAnthony Koo //==============================================================================
64384034ad4SAnthony Koo //< DMUB_VBIOS>=================================================================
64484034ad4SAnthony Koo //==============================================================================
64584034ad4SAnthony Koo
64684034ad4SAnthony Koo /*
647592a6318SAnthony Koo * enum dmub_cmd_vbios_type - VBIOS commands.
648592a6318SAnthony Koo *
64984034ad4SAnthony Koo * Command IDs should be treated as stable ABI.
65084034ad4SAnthony Koo * Do not reuse or modify IDs.
65184034ad4SAnthony Koo */
65284034ad4SAnthony Koo enum dmub_cmd_vbios_type {
653592a6318SAnthony Koo /**
654592a6318SAnthony Koo * Configures the DIG encoder.
655592a6318SAnthony Koo */
65684034ad4SAnthony Koo DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
657592a6318SAnthony Koo /**
658592a6318SAnthony Koo * Controls the PHY.
659592a6318SAnthony Koo */
66084034ad4SAnthony Koo DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
661592a6318SAnthony Koo /**
662592a6318SAnthony Koo * Sets the pixel clock/symbol clock.
663592a6318SAnthony Koo */
66484034ad4SAnthony Koo DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
665592a6318SAnthony Koo /**
666592a6318SAnthony Koo * Enables or disables power gating.
667592a6318SAnthony Koo */
66884034ad4SAnthony Koo DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
66941f91315SNicholas Kazlauskas /**
67041f91315SNicholas Kazlauskas * Controls embedded panels.
67141f91315SNicholas Kazlauskas */
6722ac685bfSAnthony Koo DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
67341f91315SNicholas Kazlauskas /**
67441f91315SNicholas Kazlauskas * Query DP alt status on a transmitter.
67541f91315SNicholas Kazlauskas */
67641f91315SNicholas Kazlauskas DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
677e383b127SNicholas Kazlauskas /**
678e383b127SNicholas Kazlauskas * Controls domain power gating
679e383b127SNicholas Kazlauskas */
680e383b127SNicholas Kazlauskas DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
68184034ad4SAnthony Koo };
68284034ad4SAnthony Koo
68384034ad4SAnthony Koo //==============================================================================
68484034ad4SAnthony Koo //</DMUB_VBIOS>=================================================================
68584034ad4SAnthony Koo //==============================================================================
68684034ad4SAnthony Koo //< DMUB_GPINT>=================================================================
68784034ad4SAnthony Koo //==============================================================================
68884034ad4SAnthony Koo
68984034ad4SAnthony Koo /**
69084034ad4SAnthony Koo * The shifts and masks below may alternatively be used to format and read
69184034ad4SAnthony Koo * the command register bits.
69284034ad4SAnthony Koo */
69384034ad4SAnthony Koo
69484034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
69584034ad4SAnthony Koo #define DMUB_GPINT_DATA_PARAM_SHIFT 0
69684034ad4SAnthony Koo
69784034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
69884034ad4SAnthony Koo #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
69984034ad4SAnthony Koo
70084034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_MASK 0xF
70184034ad4SAnthony Koo #define DMUB_GPINT_DATA_STATUS_SHIFT 28
70284034ad4SAnthony Koo
70384034ad4SAnthony Koo /**
70484034ad4SAnthony Koo * Command responses.
70584034ad4SAnthony Koo */
70684034ad4SAnthony Koo
707592a6318SAnthony Koo /**
708592a6318SAnthony Koo * Return response for DMUB_GPINT__STOP_FW command.
709592a6318SAnthony Koo */
71084034ad4SAnthony Koo #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
71184034ad4SAnthony Koo
71284034ad4SAnthony Koo /**
713592a6318SAnthony Koo * union dmub_gpint_data_register - Format for sending a command via the GPINT.
71484034ad4SAnthony Koo */
71584034ad4SAnthony Koo union dmub_gpint_data_register {
71684034ad4SAnthony Koo struct {
717592a6318SAnthony Koo uint32_t param : 16; /**< 16-bit parameter */
718592a6318SAnthony Koo uint32_t command_code : 12; /**< GPINT command */
719592a6318SAnthony Koo uint32_t status : 4; /**< Command status bit */
720592a6318SAnthony Koo } bits; /**< GPINT bit access */
721592a6318SAnthony Koo uint32_t all; /**< GPINT 32-bit access */
72284034ad4SAnthony Koo };
72384034ad4SAnthony Koo
72484034ad4SAnthony Koo /*
725592a6318SAnthony Koo * enum dmub_gpint_command - GPINT command to DMCUB FW
726592a6318SAnthony Koo *
72784034ad4SAnthony Koo * Command IDs should be treated as stable ABI.
72884034ad4SAnthony Koo * Do not reuse or modify IDs.
72984034ad4SAnthony Koo */
73084034ad4SAnthony Koo enum dmub_gpint_command {
731592a6318SAnthony Koo /**
732592a6318SAnthony Koo * Invalid command, ignored.
733592a6318SAnthony Koo */
73484034ad4SAnthony Koo DMUB_GPINT__INVALID_COMMAND = 0,
735592a6318SAnthony Koo /**
736592a6318SAnthony Koo * DESC: Queries the firmware version.
737592a6318SAnthony Koo * RETURN: Firmware version.
738592a6318SAnthony Koo */
73984034ad4SAnthony Koo DMUB_GPINT__GET_FW_VERSION = 1,
740592a6318SAnthony Koo /**
741592a6318SAnthony Koo * DESC: Halts the firmware.
742592a6318SAnthony Koo * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
743592a6318SAnthony Koo */
74484034ad4SAnthony Koo DMUB_GPINT__STOP_FW = 2,
7451a595f28SAnthony Koo /**
7461a595f28SAnthony Koo * DESC: Get PSR state from FW.
7471a595f28SAnthony Koo * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
7481a595f28SAnthony Koo */
74984034ad4SAnthony Koo DMUB_GPINT__GET_PSR_STATE = 7,
75080eba958SAnthony Koo /**
75180eba958SAnthony Koo * DESC: Notifies DMCUB of the currently active streams.
75280eba958SAnthony Koo * ARGS: Stream mask, 1 bit per active stream index.
75380eba958SAnthony Koo */
75480eba958SAnthony Koo DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
7551a595f28SAnthony Koo /**
7561a595f28SAnthony Koo * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
7571a595f28SAnthony Koo * ARGS: We can measure residency from various points. The argument will specify the residency mode.
7581a595f28SAnthony Koo * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
7591a595f28SAnthony Koo * RETURN: PSR residency in milli-percent.
7601a595f28SAnthony Koo */
761672251b2SAnthony Koo DMUB_GPINT__PSR_RESIDENCY = 9,
76201934c30SAnthony Koo
76301934c30SAnthony Koo /**
764e0138644SBhawanpreet Lakha * DESC: Get REPLAY state from FW.
765e0138644SBhawanpreet Lakha * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
766e0138644SBhawanpreet Lakha */
767e0138644SBhawanpreet Lakha DMUB_GPINT__GET_REPLAY_STATE = 13,
768e0138644SBhawanpreet Lakha
769e0138644SBhawanpreet Lakha /**
770e0138644SBhawanpreet Lakha * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
771e0138644SBhawanpreet Lakha * ARGS: We can measure residency from various points. The argument will specify the residency mode.
772e0138644SBhawanpreet Lakha * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
773e0138644SBhawanpreet Lakha * RETURN: REPLAY residency in milli-percent.
774e0138644SBhawanpreet Lakha */
775e0138644SBhawanpreet Lakha DMUB_GPINT__REPLAY_RESIDENCY = 14,
776e0138644SBhawanpreet Lakha
777e0138644SBhawanpreet Lakha
778e0138644SBhawanpreet Lakha /**
77901934c30SAnthony Koo * DESC: Notifies DMCUB detection is done so detection required can be cleared.
78001934c30SAnthony Koo */
78101934c30SAnthony Koo DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
78271ba6b57SStylon Wang /**
78371ba6b57SStylon Wang * DESC: Updates the trace buffer lower 32-bit mask.
78471ba6b57SStylon Wang * ARGS: The new mask
78571ba6b57SStylon Wang * RETURN: Lower 32-bit mask.
78671ba6b57SStylon Wang */
78771ba6b57SStylon Wang DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
78871ba6b57SStylon Wang /**
78971ba6b57SStylon Wang * DESC: Updates the trace buffer lower 32-bit mask.
79071ba6b57SStylon Wang * ARGS: The new mask
79171ba6b57SStylon Wang * RETURN: Lower 32-bit mask.
79271ba6b57SStylon Wang */
79371ba6b57SStylon Wang DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
79471ba6b57SStylon Wang /**
79571ba6b57SStylon Wang * DESC: Updates the trace buffer mask bi0~bit15.
79671ba6b57SStylon Wang * ARGS: The new mask
79771ba6b57SStylon Wang * RETURN: Lower 32-bit mask.
79871ba6b57SStylon Wang */
79971ba6b57SStylon Wang DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
80084034ad4SAnthony Koo };
80184034ad4SAnthony Koo
8020b51e7e8SAnthony Koo /**
8030b51e7e8SAnthony Koo * INBOX0 generic command definition
8040b51e7e8SAnthony Koo */
8050b51e7e8SAnthony Koo union dmub_inbox0_cmd_common {
8060b51e7e8SAnthony Koo struct {
8070b51e7e8SAnthony Koo uint32_t command_code: 8; /**< INBOX0 command code */
8080b51e7e8SAnthony Koo uint32_t param: 24; /**< 24-bit parameter */
8090b51e7e8SAnthony Koo } bits;
8100b51e7e8SAnthony Koo uint32_t all;
8110b51e7e8SAnthony Koo };
8120b51e7e8SAnthony Koo
8130b51e7e8SAnthony Koo /**
8140b51e7e8SAnthony Koo * INBOX0 hw_lock command definition
8150b51e7e8SAnthony Koo */
8160b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw {
8170b51e7e8SAnthony Koo struct {
8180b51e7e8SAnthony Koo uint32_t command_code: 8;
8190b51e7e8SAnthony Koo
8200b51e7e8SAnthony Koo /* NOTE: Must be have enough bits to match: enum hw_lock_client */
8212412d339SAnthony Koo uint32_t hw_lock_client: 2;
8220b51e7e8SAnthony Koo
8230b51e7e8SAnthony Koo /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
8240b51e7e8SAnthony Koo uint32_t otg_inst: 3;
8250b51e7e8SAnthony Koo uint32_t opp_inst: 3;
8260b51e7e8SAnthony Koo uint32_t dig_inst: 3;
8270b51e7e8SAnthony Koo
8280b51e7e8SAnthony Koo /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
8290b51e7e8SAnthony Koo uint32_t lock_pipe: 1;
8300b51e7e8SAnthony Koo uint32_t lock_cursor: 1;
8310b51e7e8SAnthony Koo uint32_t lock_dig: 1;
8320b51e7e8SAnthony Koo uint32_t triple_buffer_lock: 1;
8330b51e7e8SAnthony Koo
8340b51e7e8SAnthony Koo uint32_t lock: 1; /**< Lock */
8350b51e7e8SAnthony Koo uint32_t should_release: 1; /**< Release */
8362412d339SAnthony Koo uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
8370b51e7e8SAnthony Koo } bits;
8380b51e7e8SAnthony Koo uint32_t all;
8390b51e7e8SAnthony Koo };
8400b51e7e8SAnthony Koo
8410b51e7e8SAnthony Koo union dmub_inbox0_data_register {
8420b51e7e8SAnthony Koo union dmub_inbox0_cmd_common inbox0_cmd_common;
8430b51e7e8SAnthony Koo union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
8440b51e7e8SAnthony Koo };
8450b51e7e8SAnthony Koo
8460b51e7e8SAnthony Koo enum dmub_inbox0_command {
8470b51e7e8SAnthony Koo /**
8480b51e7e8SAnthony Koo * DESC: Invalid command, ignored.
8490b51e7e8SAnthony Koo */
8500b51e7e8SAnthony Koo DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
8510b51e7e8SAnthony Koo /**
8520b51e7e8SAnthony Koo * DESC: Notification to acquire/release HW lock
8530b51e7e8SAnthony Koo * ARGS:
8540b51e7e8SAnthony Koo */
8550b51e7e8SAnthony Koo DMUB_INBOX0_CMD__HW_LOCK = 1,
8560b51e7e8SAnthony Koo };
85784034ad4SAnthony Koo //==============================================================================
85884034ad4SAnthony Koo //</DMUB_GPINT>=================================================================
85984034ad4SAnthony Koo //==============================================================================
86084034ad4SAnthony Koo //< DMUB_CMD>===================================================================
86184034ad4SAnthony Koo //==============================================================================
86284034ad4SAnthony Koo
863592a6318SAnthony Koo /**
864592a6318SAnthony Koo * Size in bytes of each DMUB command.
865592a6318SAnthony Koo */
8667c008829SNicholas Kazlauskas #define DMUB_RB_CMD_SIZE 64
867592a6318SAnthony Koo
868592a6318SAnthony Koo /**
869592a6318SAnthony Koo * Maximum number of items in the DMUB ringbuffer.
870592a6318SAnthony Koo */
8717c008829SNicholas Kazlauskas #define DMUB_RB_MAX_ENTRY 128
872592a6318SAnthony Koo
873592a6318SAnthony Koo /**
874592a6318SAnthony Koo * Ringbuffer size in bytes.
875592a6318SAnthony Koo */
8767c008829SNicholas Kazlauskas #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
877592a6318SAnthony Koo
878592a6318SAnthony Koo /**
879592a6318SAnthony Koo * REG_SET mask for reg offload.
880592a6318SAnthony Koo */
8817c008829SNicholas Kazlauskas #define REG_SET_MASK 0xFFFF
8827c008829SNicholas Kazlauskas
883d4bbcecbSNicholas Kazlauskas /*
884592a6318SAnthony Koo * enum dmub_cmd_type - DMUB inbox command.
885592a6318SAnthony Koo *
886d4bbcecbSNicholas Kazlauskas * Command IDs should be treated as stable ABI.
887d4bbcecbSNicholas Kazlauskas * Do not reuse or modify IDs.
888d4bbcecbSNicholas Kazlauskas */
889d4bbcecbSNicholas Kazlauskas enum dmub_cmd_type {
890592a6318SAnthony Koo /**
891592a6318SAnthony Koo * Invalid command.
892592a6318SAnthony Koo */
893d4bbcecbSNicholas Kazlauskas DMUB_CMD__NULL = 0,
894592a6318SAnthony Koo /**
895592a6318SAnthony Koo * Read modify write register sequence offload.
896592a6318SAnthony Koo */
897d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
898592a6318SAnthony Koo /**
899592a6318SAnthony Koo * Field update register sequence offload.
900592a6318SAnthony Koo */
901d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
902592a6318SAnthony Koo /**
903592a6318SAnthony Koo * Burst write sequence offload.
904592a6318SAnthony Koo */
905d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
906592a6318SAnthony Koo /**
907592a6318SAnthony Koo * Reg wait sequence offload.
908592a6318SAnthony Koo */
909d4bbcecbSNicholas Kazlauskas DMUB_CMD__REG_REG_WAIT = 4,
910592a6318SAnthony Koo /**
911592a6318SAnthony Koo * Workaround to avoid HUBP underflow during NV12 playback.
912592a6318SAnthony Koo */
913bae9c49bSYongqiang Sun DMUB_CMD__PLAT_54186_WA = 5,
9141a595f28SAnthony Koo /**
9151a595f28SAnthony Koo * Command type used to query FW feature caps.
9161a595f28SAnthony Koo */
91734ba432cSAnthony Koo DMUB_CMD__QUERY_FEATURE_CAPS = 6,
9181a595f28SAnthony Koo /**
919b09c1fffSLeo (Hanghong) Ma * Command type used to get visual confirm color.
920b09c1fffSLeo (Hanghong) Ma */
921b09c1fffSLeo (Hanghong) Ma DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
922b09c1fffSLeo (Hanghong) Ma /**
9231a595f28SAnthony Koo * Command type used for all PSR commands.
9241a595f28SAnthony Koo */
925d4bbcecbSNicholas Kazlauskas DMUB_CMD__PSR = 64,
926592a6318SAnthony Koo /**
927592a6318SAnthony Koo * Command type used for all MALL commands.
928592a6318SAnthony Koo */
92952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL = 65,
9301a595f28SAnthony Koo /**
9311a595f28SAnthony Koo * Command type used for all ABM commands.
9321a595f28SAnthony Koo */
933e6ea8c34SWyatt Wood DMUB_CMD__ABM = 66,
9341a595f28SAnthony Koo /**
93583eb5385SDavid Zhang * Command type used to update dirty rects in FW.
93683eb5385SDavid Zhang */
93783eb5385SDavid Zhang DMUB_CMD__UPDATE_DIRTY_RECT = 67,
93883eb5385SDavid Zhang /**
93983eb5385SDavid Zhang * Command type used to update cursor info in FW.
94083eb5385SDavid Zhang */
94183eb5385SDavid Zhang DMUB_CMD__UPDATE_CURSOR_INFO = 68,
94283eb5385SDavid Zhang /**
9431a595f28SAnthony Koo * Command type used for HW locking in FW.
9441a595f28SAnthony Koo */
945788408b7SAnthony Koo DMUB_CMD__HW_LOCK = 69,
9461a595f28SAnthony Koo /**
9471a595f28SAnthony Koo * Command type used to access DP AUX.
9481a595f28SAnthony Koo */
949d9beecfcSAnthony Koo DMUB_CMD__DP_AUX_ACCESS = 70,
9501a595f28SAnthony Koo /**
9511a595f28SAnthony Koo * Command type used for OUTBOX1 notification enable
9521a595f28SAnthony Koo */
953d9beecfcSAnthony Koo DMUB_CMD__OUTBOX1_ENABLE = 71,
9545cef7e8eSAnthony Koo
955b04cb192SNicholas Kazlauskas /**
956b04cb192SNicholas Kazlauskas * Command type used for all idle optimization commands.
957b04cb192SNicholas Kazlauskas */
958b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT = 72,
959b04cb192SNicholas Kazlauskas /**
960b04cb192SNicholas Kazlauskas * Command type used for all clock manager commands.
961b04cb192SNicholas Kazlauskas */
962b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR = 73,
963b04cb192SNicholas Kazlauskas /**
964b04cb192SNicholas Kazlauskas * Command type used for all panel control commands.
965b04cb192SNicholas Kazlauskas */
966b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL = 74,
967ac2e555eSAurabindo Pillai /**
968ac2e555eSAurabindo Pillai * Command type used for <TODO:description>
969ac2e555eSAurabindo Pillai */
970ac2e555eSAurabindo Pillai DMUB_CMD__CAB_FOR_SS = 75,
97185f4bc0cSAlvin Lee
97285f4bc0cSAlvin Lee DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
97385f4bc0cSAlvin Lee
974592a6318SAnthony Koo /**
97576724b76SJimmy Kizito * Command type used for interfacing with DPIA.
97676724b76SJimmy Kizito */
97776724b76SJimmy Kizito DMUB_CMD__DPIA = 77,
97876724b76SJimmy Kizito /**
979021eaef8SAnthony Koo * Command type used for EDID CEA parsing
980021eaef8SAnthony Koo */
981021eaef8SAnthony Koo DMUB_CMD__EDID_CEA = 79,
982021eaef8SAnthony Koo /**
983c595fb05SWenjing Liu * Command type used for getting usbc cable ID
984c595fb05SWenjing Liu */
985c595fb05SWenjing Liu DMUB_CMD_GET_USBC_CABLE_ID = 81,
986c595fb05SWenjing Liu /**
987ea5a4db9SAnthony Koo * Command type used to query HPD state.
988ea5a4db9SAnthony Koo */
989ea5a4db9SAnthony Koo DMUB_CMD__QUERY_HPD_STATE = 82,
990ea5a4db9SAnthony Koo /**
991592a6318SAnthony Koo * Command type used for all VBIOS interface commands.
992592a6318SAnthony Koo */
9931fb695d9SAnthony Koo
994c0459bddSAlan Liu /**
995e0138644SBhawanpreet Lakha * Command type used for all REPLAY commands.
996e0138644SBhawanpreet Lakha */
997e0138644SBhawanpreet Lakha DMUB_CMD__REPLAY = 83,
998e0138644SBhawanpreet Lakha
999e0138644SBhawanpreet Lakha /**
1000c0459bddSAlan Liu * Command type used for all SECURE_DISPLAY commands.
1001c0459bddSAlan Liu */
1002c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY = 85,
10036f4f8ff5SMeenakshikumar Somasundaram
10046f4f8ff5SMeenakshikumar Somasundaram /**
10056f4f8ff5SMeenakshikumar Somasundaram * Command type used to set DPIA HPD interrupt state
10066f4f8ff5SMeenakshikumar Somasundaram */
10076f4f8ff5SMeenakshikumar Somasundaram DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
10086f4f8ff5SMeenakshikumar Somasundaram
1009d4bbcecbSNicholas Kazlauskas DMUB_CMD__VBIOS = 128,
10107c008829SNicholas Kazlauskas };
10117c008829SNicholas Kazlauskas
1012592a6318SAnthony Koo /**
1013592a6318SAnthony Koo * enum dmub_out_cmd_type - DMUB outbox commands.
1014592a6318SAnthony Koo */
10153b37260bSAnthony Koo enum dmub_out_cmd_type {
1016592a6318SAnthony Koo /**
1017592a6318SAnthony Koo * Invalid outbox command, ignored.
1018592a6318SAnthony Koo */
10193b37260bSAnthony Koo DMUB_OUT_CMD__NULL = 0,
10201a595f28SAnthony Koo /**
10211a595f28SAnthony Koo * Command type used for DP AUX Reply data notification
10221a595f28SAnthony Koo */
1023d9beecfcSAnthony Koo DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1024892b74a6SMeenakshikumar Somasundaram /**
1025892b74a6SMeenakshikumar Somasundaram * Command type used for DP HPD event notification
1026892b74a6SMeenakshikumar Somasundaram */
1027892b74a6SMeenakshikumar Somasundaram DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
102871af9d46SMeenakshikumar Somasundaram /**
102971af9d46SMeenakshikumar Somasundaram * Command type used for SET_CONFIG Reply notification
103071af9d46SMeenakshikumar Somasundaram */
103171af9d46SMeenakshikumar Somasundaram DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
10328af54c61SMustapha Ghaddar /**
10338af54c61SMustapha Ghaddar * Command type used for USB4 DPIA notification
10348af54c61SMustapha Ghaddar */
10358af54c61SMustapha Ghaddar DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
10363b37260bSAnthony Koo };
10373b37260bSAnthony Koo
103876724b76SJimmy Kizito /* DMUB_CMD__DPIA command sub-types. */
103976724b76SJimmy Kizito enum dmub_cmd_dpia_type {
104076724b76SJimmy Kizito DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
104171af9d46SMeenakshikumar Somasundaram DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1042139a3311SMeenakshikumar Somasundaram DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
104376724b76SJimmy Kizito };
104476724b76SJimmy Kizito
10458af54c61SMustapha Ghaddar /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
10468af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type {
10478af54c61SMustapha Ghaddar DPIA_NOTIFY__BW_ALLOCATION = 0,
10488af54c61SMustapha Ghaddar };
10498af54c61SMustapha Ghaddar
10507c008829SNicholas Kazlauskas #pragma pack(push, 1)
10517c008829SNicholas Kazlauskas
1052592a6318SAnthony Koo /**
1053592a6318SAnthony Koo * struct dmub_cmd_header - Common command header fields.
1054592a6318SAnthony Koo */
10557c008829SNicholas Kazlauskas struct dmub_cmd_header {
1056592a6318SAnthony Koo unsigned int type : 8; /**< command type */
1057592a6318SAnthony Koo unsigned int sub_type : 8; /**< command sub type */
1058592a6318SAnthony Koo unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
10590b51e7e8SAnthony Koo unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
10600b51e7e8SAnthony Koo unsigned int reserved0 : 6; /**< reserved bits */
1061592a6318SAnthony Koo unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1062592a6318SAnthony Koo unsigned int reserved1 : 2; /**< reserved bits */
10637c008829SNicholas Kazlauskas };
10647c008829SNicholas Kazlauskas
10657c008829SNicholas Kazlauskas /*
1066592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write
10677c008829SNicholas Kazlauskas *
10687c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 5 sets of read modify writes,
10697c008829SNicholas Kazlauskas * each take 3 dwords.
10707c008829SNicholas Kazlauskas *
10717c008829SNicholas Kazlauskas * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
10727c008829SNicholas Kazlauskas *
10737c008829SNicholas Kazlauskas * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
10747c008829SNicholas Kazlauskas * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
10757c008829SNicholas Kazlauskas */
10767c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence {
1077592a6318SAnthony Koo uint32_t addr; /**< register address */
1078592a6318SAnthony Koo uint32_t modify_mask; /**< modify mask */
1079592a6318SAnthony Koo uint32_t modify_value; /**< modify value */
10807c008829SNicholas Kazlauskas };
10817c008829SNicholas Kazlauskas
1082592a6318SAnthony Koo /**
1083592a6318SAnthony Koo * Maximum number of ops in read modify write sequence.
1084592a6318SAnthony Koo */
10857c008829SNicholas Kazlauskas #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1086592a6318SAnthony Koo
1087592a6318SAnthony Koo /**
1088592a6318SAnthony Koo * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1089592a6318SAnthony Koo */
10907c008829SNicholas Kazlauskas struct dmub_rb_cmd_read_modify_write {
1091592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */
1092592a6318SAnthony Koo /**
1093592a6318SAnthony Koo * Read modify write sequence.
1094592a6318SAnthony Koo */
10957c008829SNicholas Kazlauskas struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
10967c008829SNicholas Kazlauskas };
10977c008829SNicholas Kazlauskas
10987c008829SNicholas Kazlauskas /*
10997c008829SNicholas Kazlauskas * Update a register with specified masks and values sequeunce
11007c008829SNicholas Kazlauskas *
11017c008829SNicholas Kazlauskas * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
11027c008829SNicholas Kazlauskas *
11037c008829SNicholas Kazlauskas * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
11047c008829SNicholas Kazlauskas *
11057c008829SNicholas Kazlauskas *
11067c008829SNicholas Kazlauskas * USE CASE:
11077c008829SNicholas Kazlauskas * 1. auto-increment register where additional read would update pointer and produce wrong result
11087c008829SNicholas Kazlauskas * 2. toggle a bit without read in the middle
11097c008829SNicholas Kazlauskas */
11107c008829SNicholas Kazlauskas
11117c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence {
1112592a6318SAnthony Koo uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1113592a6318SAnthony Koo uint32_t modify_value; /**< value to update with */
11147c008829SNicholas Kazlauskas };
11157c008829SNicholas Kazlauskas
1116592a6318SAnthony Koo /**
1117592a6318SAnthony Koo * Maximum number of ops in field update sequence.
1118592a6318SAnthony Koo */
11197c008829SNicholas Kazlauskas #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1120592a6318SAnthony Koo
1121592a6318SAnthony Koo /**
1122592a6318SAnthony Koo * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1123592a6318SAnthony Koo */
11247c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_field_update_sequence {
1125592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */
1126592a6318SAnthony Koo uint32_t addr; /**< register address */
1127592a6318SAnthony Koo /**
1128592a6318SAnthony Koo * Field update sequence.
1129592a6318SAnthony Koo */
11307c008829SNicholas Kazlauskas struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
11317c008829SNicholas Kazlauskas };
11327c008829SNicholas Kazlauskas
1133592a6318SAnthony Koo
1134592a6318SAnthony Koo /**
1135592a6318SAnthony Koo * Maximum number of burst write values.
1136592a6318SAnthony Koo */
1137592a6318SAnthony Koo #define DMUB_BURST_WRITE_VALUES__MAX 14
1138592a6318SAnthony Koo
11397c008829SNicholas Kazlauskas /*
1140592a6318SAnthony Koo * struct dmub_rb_cmd_burst_write - Burst write
11417c008829SNicholas Kazlauskas *
11427c008829SNicholas Kazlauskas * support use case such as writing out LUTs.
11437c008829SNicholas Kazlauskas *
11447c008829SNicholas Kazlauskas * 60 payload bytes can hold up to 14 values to write to given address
11457c008829SNicholas Kazlauskas *
11467c008829SNicholas Kazlauskas * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
11477c008829SNicholas Kazlauskas */
11487c008829SNicholas Kazlauskas struct dmub_rb_cmd_burst_write {
1149592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */
1150592a6318SAnthony Koo uint32_t addr; /**< register start address */
1151592a6318SAnthony Koo /**
1152592a6318SAnthony Koo * Burst write register values.
1153592a6318SAnthony Koo */
11547c008829SNicholas Kazlauskas uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
11557c008829SNicholas Kazlauskas };
11567c008829SNicholas Kazlauskas
1157592a6318SAnthony Koo /**
1158592a6318SAnthony Koo * struct dmub_rb_cmd_common - Common command header
1159592a6318SAnthony Koo */
11607c008829SNicholas Kazlauskas struct dmub_rb_cmd_common {
1161592a6318SAnthony Koo struct dmub_cmd_header header; /**< command header */
1162592a6318SAnthony Koo /**
1163592a6318SAnthony Koo * Padding to RB_CMD_SIZE
1164592a6318SAnthony Koo */
11657c008829SNicholas Kazlauskas uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
11667c008829SNicholas Kazlauskas };
11677c008829SNicholas Kazlauskas
1168592a6318SAnthony Koo /**
1169592a6318SAnthony Koo * struct dmub_cmd_reg_wait_data - Register wait data
1170592a6318SAnthony Koo */
11717c008829SNicholas Kazlauskas struct dmub_cmd_reg_wait_data {
1172592a6318SAnthony Koo uint32_t addr; /**< Register address */
1173592a6318SAnthony Koo uint32_t mask; /**< Mask for register bits */
1174592a6318SAnthony Koo uint32_t condition_field_value; /**< Value to wait for */
1175592a6318SAnthony Koo uint32_t time_out_us; /**< Time out for reg wait in microseconds */
11767c008829SNicholas Kazlauskas };
11777c008829SNicholas Kazlauskas
1178592a6318SAnthony Koo /**
1179592a6318SAnthony Koo * struct dmub_rb_cmd_reg_wait - Register wait command
1180592a6318SAnthony Koo */
11817c008829SNicholas Kazlauskas struct dmub_rb_cmd_reg_wait {
1182592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */
1183592a6318SAnthony Koo struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
11847c008829SNicholas Kazlauskas };
11857c008829SNicholas Kazlauskas
1186592a6318SAnthony Koo /**
1187592a6318SAnthony Koo * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1188592a6318SAnthony Koo *
1189592a6318SAnthony Koo * Reprograms surface parameters to avoid underflow.
1190592a6318SAnthony Koo */
1191bae9c49bSYongqiang Sun struct dmub_cmd_PLAT_54186_wa {
1192592a6318SAnthony Koo uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1193592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1194592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1195592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1196592a6318SAnthony Koo uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
119722aa5614SYongqiang Sun struct {
1198592a6318SAnthony Koo uint8_t hubp_inst : 4; /**< HUBP instance */
1199592a6318SAnthony Koo uint8_t tmz_surface : 1; /**< TMZ enable or disable */
1200592a6318SAnthony Koo uint8_t immediate :1; /**< Immediate flip */
1201592a6318SAnthony Koo uint8_t vmid : 4; /**< VMID */
1202592a6318SAnthony Koo uint8_t grph_stereo : 1; /**< 1 if stereo */
1203592a6318SAnthony Koo uint32_t reserved : 21; /**< Reserved */
1204592a6318SAnthony Koo } flip_params; /**< Pageflip parameters */
1205d2994b25SAyush Gupta uint32_t reserved[9]; /**< Reserved bits */
12068c019253SYongqiang Sun };
12078c019253SYongqiang Sun
1208592a6318SAnthony Koo /**
1209592a6318SAnthony Koo * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1210592a6318SAnthony Koo */
1211bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa {
1212592a6318SAnthony Koo struct dmub_cmd_header header; /**< Command header */
1213592a6318SAnthony Koo struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
12148c019253SYongqiang Sun };
12158c019253SYongqiang Sun
1216592a6318SAnthony Koo /**
1217592a6318SAnthony Koo * struct dmub_rb_cmd_mall - MALL command data.
1218592a6318SAnthony Koo */
121952f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall {
1220592a6318SAnthony Koo struct dmub_cmd_header header; /**< Common command header */
1221592a6318SAnthony Koo union dmub_addr cursor_copy_src; /**< Cursor copy address */
1222592a6318SAnthony Koo union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1223592a6318SAnthony Koo uint32_t tmr_delay; /**< Timer delay */
1224592a6318SAnthony Koo uint32_t tmr_scale; /**< Timer scale */
1225592a6318SAnthony Koo uint16_t cursor_width; /**< Cursor width in pixels */
1226592a6318SAnthony Koo uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1227592a6318SAnthony Koo uint16_t cursor_height; /**< Cursor height in pixels */
1228592a6318SAnthony Koo uint8_t cursor_bpp; /**< Cursor bits per pixel */
1229592a6318SAnthony Koo uint8_t debug_bits; /**< Debug bits */
1230ea7154d8SBhawanpreet Lakha
1231592a6318SAnthony Koo uint8_t reserved1; /**< Reserved bits */
1232592a6318SAnthony Koo uint8_t reserved2; /**< Reserved bits */
123352f2e83eSBhawanpreet Lakha };
123452f2e83eSBhawanpreet Lakha
1235b04cb192SNicholas Kazlauskas /**
1236053065a4SAurabindo Pillai * enum dmub_cmd_cab_type - CAB command data.
1237ac2e555eSAurabindo Pillai */
1238ac2e555eSAurabindo Pillai enum dmub_cmd_cab_type {
1239053065a4SAurabindo Pillai /**
1240053065a4SAurabindo Pillai * No idle optimizations (i.e. no CAB)
1241053065a4SAurabindo Pillai */
1242ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1243053065a4SAurabindo Pillai /**
1244053065a4SAurabindo Pillai * No DCN requests for memory
1245053065a4SAurabindo Pillai */
1246ac2e555eSAurabindo Pillai DMUB_CMD__CAB_NO_DCN_REQ = 1,
1247053065a4SAurabindo Pillai /**
1248053065a4SAurabindo Pillai * Fit surfaces in CAB (i.e. CAB enable)
1249053065a4SAurabindo Pillai */
1250ac2e555eSAurabindo Pillai DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1251ac2e555eSAurabindo Pillai };
1252ac2e555eSAurabindo Pillai
1253ac2e555eSAurabindo Pillai /**
1254053065a4SAurabindo Pillai * struct dmub_rb_cmd_cab - CAB command data.
1255ac2e555eSAurabindo Pillai */
1256ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss {
1257ac2e555eSAurabindo Pillai struct dmub_cmd_header header;
1258ac2e555eSAurabindo Pillai uint8_t cab_alloc_ways; /* total number of ways */
1259ac2e555eSAurabindo Pillai uint8_t debug_bits; /* debug bits */
1260ac2e555eSAurabindo Pillai };
126185f4bc0cSAlvin Lee
1262053065a4SAurabindo Pillai /**
1263053065a4SAurabindo Pillai * Enum for indicating which MCLK switch mode per pipe
1264053065a4SAurabindo Pillai */
126585f4bc0cSAlvin Lee enum mclk_switch_mode {
126685f4bc0cSAlvin Lee NONE = 0,
126785f4bc0cSAlvin Lee FPO = 1,
126885f4bc0cSAlvin Lee SUBVP = 2,
126985f4bc0cSAlvin Lee VBLANK = 3,
127085f4bc0cSAlvin Lee };
127185f4bc0cSAlvin Lee
127285f4bc0cSAlvin Lee /* Per pipe struct which stores the MCLK switch mode
127385f4bc0cSAlvin Lee * data to be sent to DMUB.
127485f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged
127585f4bc0cSAlvin Lee * the type name can be updated
127685f4bc0cSAlvin Lee */
127785f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
127885f4bc0cSAlvin Lee union {
127985f4bc0cSAlvin Lee struct {
128085f4bc0cSAlvin Lee uint32_t pix_clk_100hz;
128185f4bc0cSAlvin Lee uint16_t main_vblank_start;
128285f4bc0cSAlvin Lee uint16_t main_vblank_end;
128385f4bc0cSAlvin Lee uint16_t mall_region_lines;
128485f4bc0cSAlvin Lee uint16_t prefetch_lines;
128585f4bc0cSAlvin Lee uint16_t prefetch_to_mall_start_lines;
128685f4bc0cSAlvin Lee uint16_t processing_delay_lines;
128785f4bc0cSAlvin Lee uint16_t htotal; // required to calculate line time for multi-display cases
128885f4bc0cSAlvin Lee uint16_t vtotal;
128985f4bc0cSAlvin Lee uint8_t main_pipe_index;
129085f4bc0cSAlvin Lee uint8_t phantom_pipe_index;
12910acc5b06SAnthony Koo /* Since the microschedule is calculated in terms of OTG lines,
12920acc5b06SAnthony Koo * include any scaling factors to make sure when we get accurate
12930acc5b06SAnthony Koo * conversion when programming MALL_START_LINE (which is in terms
12940acc5b06SAnthony Koo * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
12950acc5b06SAnthony Koo * is 1/2 (numerator = 1, denominator = 2).
12960acc5b06SAnthony Koo */
12970acc5b06SAnthony Koo uint8_t scale_factor_numerator;
12980acc5b06SAnthony Koo uint8_t scale_factor_denominator;
129981f776b6SAnthony Koo uint8_t is_drr;
13001591a647SAnthony Koo uint8_t main_split_pipe_index;
13011591a647SAnthony Koo uint8_t phantom_split_pipe_index;
130285f4bc0cSAlvin Lee } subvp_data;
130385f4bc0cSAlvin Lee
130485f4bc0cSAlvin Lee struct {
130585f4bc0cSAlvin Lee uint32_t pix_clk_100hz;
130685f4bc0cSAlvin Lee uint16_t vblank_start;
130785f4bc0cSAlvin Lee uint16_t vblank_end;
130885f4bc0cSAlvin Lee uint16_t vstartup_start;
130985f4bc0cSAlvin Lee uint16_t vtotal;
131085f4bc0cSAlvin Lee uint16_t htotal;
131185f4bc0cSAlvin Lee uint8_t vblank_pipe_index;
1312ae7169a9SAlvin Lee uint8_t padding[1];
131385f4bc0cSAlvin Lee struct {
131485f4bc0cSAlvin Lee uint8_t drr_in_use;
131585f4bc0cSAlvin Lee uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
131685f4bc0cSAlvin Lee uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
131785f4bc0cSAlvin Lee uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
131885f4bc0cSAlvin Lee uint8_t use_ramping; // Use ramping or not
1319ae7169a9SAlvin Lee uint8_t drr_vblank_start_margin;
132085f4bc0cSAlvin Lee } drr_info; // DRR considered as part of SubVP + VBLANK case
132185f4bc0cSAlvin Lee } vblank_data;
132285f4bc0cSAlvin Lee } pipe_config;
132385f4bc0cSAlvin Lee
13240acc5b06SAnthony Koo /* - subvp_data in the union (pipe_config) takes up 27 bytes.
13250acc5b06SAnthony Koo * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
13260acc5b06SAnthony Koo * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
13270acc5b06SAnthony Koo */
13280acc5b06SAnthony Koo uint8_t mode; // enum mclk_switch_mode
132985f4bc0cSAlvin Lee };
133085f4bc0cSAlvin Lee
133185f4bc0cSAlvin Lee /**
133285f4bc0cSAlvin Lee * Config data for Sub-VP and FPO
133385f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged
133485f4bc0cSAlvin Lee * the type name can be updated
133585f4bc0cSAlvin Lee */
133685f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
133785f4bc0cSAlvin Lee uint16_t watermark_a_cache;
133885f4bc0cSAlvin Lee uint8_t vertical_int_margin_us;
133985f4bc0cSAlvin Lee uint8_t pstate_allow_width_us;
134085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
134185f4bc0cSAlvin Lee };
134285f4bc0cSAlvin Lee
134385f4bc0cSAlvin Lee /**
134485f4bc0cSAlvin Lee * DMUB rb command definition for Sub-VP and FPO
134585f4bc0cSAlvin Lee * Named "v2" for now -- once FPO and SUBVP are fully merged
134685f4bc0cSAlvin Lee * the type name can be updated
134785f4bc0cSAlvin Lee */
134885f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
134985f4bc0cSAlvin Lee struct dmub_cmd_header header;
135085f4bc0cSAlvin Lee struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
135185f4bc0cSAlvin Lee };
135285f4bc0cSAlvin Lee
1353ac2e555eSAurabindo Pillai /**
1354b04cb192SNicholas Kazlauskas * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1355b04cb192SNicholas Kazlauskas */
1356b04cb192SNicholas Kazlauskas enum dmub_cmd_idle_opt_type {
1357b04cb192SNicholas Kazlauskas /**
1358b04cb192SNicholas Kazlauskas * DCN hardware restore.
1359b04cb192SNicholas Kazlauskas */
1360b04cb192SNicholas Kazlauskas DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1361f586fea8SJake Wang
1362f586fea8SJake Wang /**
1363f586fea8SJake Wang * DCN hardware save.
1364f586fea8SJake Wang */
13659dce8c2aSAnthony Koo DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
13669dce8c2aSAnthony Koo
13679dce8c2aSAnthony Koo /**
13689dce8c2aSAnthony Koo * DCN hardware notify idle.
13699dce8c2aSAnthony Koo */
13709dce8c2aSAnthony Koo DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2
1371b04cb192SNicholas Kazlauskas };
1372b04cb192SNicholas Kazlauskas
1373b04cb192SNicholas Kazlauskas /**
1374b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1375b04cb192SNicholas Kazlauskas */
1376b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore {
1377b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */
1378b04cb192SNicholas Kazlauskas };
1379b04cb192SNicholas Kazlauskas
1380b04cb192SNicholas Kazlauskas /**
13819dce8c2aSAnthony Koo * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
13829dce8c2aSAnthony Koo */
13839dce8c2aSAnthony Koo struct dmub_dcn_notify_idle_cntl_data {
13849dce8c2aSAnthony Koo uint8_t driver_idle;
13859dce8c2aSAnthony Koo uint8_t pad[1];
13869dce8c2aSAnthony Koo };
13879dce8c2aSAnthony Koo
13889dce8c2aSAnthony Koo /**
13899dce8c2aSAnthony Koo * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
13909dce8c2aSAnthony Koo */
13919dce8c2aSAnthony Koo struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
13929dce8c2aSAnthony Koo struct dmub_cmd_header header; /**< header */
13939dce8c2aSAnthony Koo struct dmub_dcn_notify_idle_cntl_data cntl_data;
13949dce8c2aSAnthony Koo };
13959dce8c2aSAnthony Koo
13969dce8c2aSAnthony Koo /**
1397b04cb192SNicholas Kazlauskas * struct dmub_clocks - Clock update notification.
1398b04cb192SNicholas Kazlauskas */
1399b04cb192SNicholas Kazlauskas struct dmub_clocks {
1400b04cb192SNicholas Kazlauskas uint32_t dispclk_khz; /**< dispclk kHz */
1401b04cb192SNicholas Kazlauskas uint32_t dppclk_khz; /**< dppclk kHz */
1402b04cb192SNicholas Kazlauskas uint32_t dcfclk_khz; /**< dcfclk kHz */
1403b04cb192SNicholas Kazlauskas uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1404b04cb192SNicholas Kazlauskas };
1405b04cb192SNicholas Kazlauskas
1406b04cb192SNicholas Kazlauskas /**
1407b04cb192SNicholas Kazlauskas * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1408b04cb192SNicholas Kazlauskas */
1409b04cb192SNicholas Kazlauskas enum dmub_cmd_clk_mgr_type {
1410b04cb192SNicholas Kazlauskas /**
1411b04cb192SNicholas Kazlauskas * Notify DMCUB of clock update.
1412b04cb192SNicholas Kazlauskas */
1413b04cb192SNicholas Kazlauskas DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1414b04cb192SNicholas Kazlauskas };
1415b04cb192SNicholas Kazlauskas
1416b04cb192SNicholas Kazlauskas /**
1417b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1418b04cb192SNicholas Kazlauskas */
1419b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks {
1420b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */
1421b04cb192SNicholas Kazlauskas struct dmub_clocks clocks; /**< clock data */
1422b04cb192SNicholas Kazlauskas };
14238fe44c08SAlex Deucher
1424592a6318SAnthony Koo /**
1425592a6318SAnthony Koo * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1426592a6318SAnthony Koo */
14277c008829SNicholas Kazlauskas struct dmub_cmd_digx_encoder_control_data {
1428592a6318SAnthony Koo union dig_encoder_control_parameters_v1_5 dig; /**< payload */
14297c008829SNicholas Kazlauskas };
14307c008829SNicholas Kazlauskas
1431592a6318SAnthony Koo /**
1432592a6318SAnthony Koo * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1433592a6318SAnthony Koo */
14347c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control {
1435592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */
1436592a6318SAnthony Koo struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
14377c008829SNicholas Kazlauskas };
14387c008829SNicholas Kazlauskas
1439592a6318SAnthony Koo /**
1440592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1441592a6318SAnthony Koo */
14427c008829SNicholas Kazlauskas struct dmub_cmd_set_pixel_clock_data {
1443592a6318SAnthony Koo struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
14447c008829SNicholas Kazlauskas };
14457c008829SNicholas Kazlauskas
1446592a6318SAnthony Koo /**
1447592a6318SAnthony Koo * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1448592a6318SAnthony Koo */
14497c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock {
1450592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */
1451592a6318SAnthony Koo struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
14527c008829SNicholas Kazlauskas };
14537c008829SNicholas Kazlauskas
1454592a6318SAnthony Koo /**
1455592a6318SAnthony Koo * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1456592a6318SAnthony Koo */
14577c008829SNicholas Kazlauskas struct dmub_cmd_enable_disp_power_gating_data {
1458592a6318SAnthony Koo struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
14597c008829SNicholas Kazlauskas };
14607c008829SNicholas Kazlauskas
1461592a6318SAnthony Koo /**
1462592a6318SAnthony Koo * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1463592a6318SAnthony Koo */
14647c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating {
1465592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */
1466592a6318SAnthony Koo struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
14677c008829SNicholas Kazlauskas };
14687c008829SNicholas Kazlauskas
1469592a6318SAnthony Koo /**
1470592a6318SAnthony Koo * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1471592a6318SAnthony Koo */
1472d448521eSAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 {
1473d448521eSAnthony Koo uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1474d448521eSAnthony Koo uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1475d448521eSAnthony Koo union {
1476d448521eSAnthony Koo uint8_t digmode; /**< enum atom_encode_mode_def */
1477d448521eSAnthony Koo uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1478d448521eSAnthony Koo } mode_laneset;
1479d448521eSAnthony Koo uint8_t lanenum; /**< Number of lanes */
1480d448521eSAnthony Koo union {
1481d448521eSAnthony Koo uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1482d448521eSAnthony Koo } symclk_units;
1483d448521eSAnthony Koo uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1484d448521eSAnthony Koo uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1485d448521eSAnthony Koo uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
14865a2730fcSFangzhi Zuo uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1487d448521eSAnthony Koo uint8_t reserved1; /**< For future use */
1488d448521eSAnthony Koo uint8_t reserved2[3]; /**< For future use */
1489d448521eSAnthony Koo uint32_t reserved3[11]; /**< For future use */
1490d448521eSAnthony Koo };
1491d448521eSAnthony Koo
1492592a6318SAnthony Koo /**
1493592a6318SAnthony Koo * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1494592a6318SAnthony Koo */
1495d448521eSAnthony Koo union dmub_cmd_dig1_transmitter_control_data {
1496592a6318SAnthony Koo struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1497592a6318SAnthony Koo struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
14987c008829SNicholas Kazlauskas };
14997c008829SNicholas Kazlauskas
1500592a6318SAnthony Koo /**
1501592a6318SAnthony Koo * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1502592a6318SAnthony Koo */
15037c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control {
1504592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */
1505592a6318SAnthony Koo union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
15067c008829SNicholas Kazlauskas };
15077c008829SNicholas Kazlauskas
1508592a6318SAnthony Koo /**
1509e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
1510e383b127SNicholas Kazlauskas */
1511e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data {
1512e383b127SNicholas Kazlauskas uint8_t inst : 6; /**< DOMAIN instance to control */
1513e383b127SNicholas Kazlauskas uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
1514e383b127SNicholas Kazlauskas uint8_t reserved[3]; /**< Reserved for future use */
1515e383b127SNicholas Kazlauskas };
1516e383b127SNicholas Kazlauskas
1517e383b127SNicholas Kazlauskas /**
1518e383b127SNicholas Kazlauskas * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
1519e383b127SNicholas Kazlauskas */
1520e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control {
1521e383b127SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */
1522e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control_data data; /**< payload */
1523e383b127SNicholas Kazlauskas };
1524e383b127SNicholas Kazlauskas
1525e383b127SNicholas Kazlauskas /**
152676724b76SJimmy Kizito * DPIA tunnel command parameters.
152776724b76SJimmy Kizito */
152876724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data {
152976724b76SJimmy Kizito uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
153076724b76SJimmy Kizito uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
153176724b76SJimmy Kizito union {
153276724b76SJimmy Kizito uint8_t digmode; /** enum atom_encode_mode_def */
153376724b76SJimmy Kizito uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
153476724b76SJimmy Kizito } mode_laneset;
153576724b76SJimmy Kizito uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
153676724b76SJimmy Kizito uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
153776724b76SJimmy Kizito uint8_t hpdsel; /** =0: HPD is not assigned */
153876724b76SJimmy Kizito uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
153976724b76SJimmy Kizito uint8_t dpia_id; /** Index of DPIA */
154076724b76SJimmy Kizito uint8_t fec_rdy : 1;
154176724b76SJimmy Kizito uint8_t reserved : 7;
154276724b76SJimmy Kizito uint32_t reserved1;
154376724b76SJimmy Kizito };
154476724b76SJimmy Kizito
154576724b76SJimmy Kizito /**
154676724b76SJimmy Kizito * DMUB command for DPIA tunnel control.
154776724b76SJimmy Kizito */
154876724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control {
154976724b76SJimmy Kizito struct dmub_cmd_header header;
155076724b76SJimmy Kizito struct dmub_cmd_dig_dpia_control_data dpia_control;
155176724b76SJimmy Kizito };
155276724b76SJimmy Kizito
155376724b76SJimmy Kizito /**
155471af9d46SMeenakshikumar Somasundaram * SET_CONFIG Command Payload
155571af9d46SMeenakshikumar Somasundaram */
155671af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload {
155771af9d46SMeenakshikumar Somasundaram uint8_t msg_type; /* set config message type */
155871af9d46SMeenakshikumar Somasundaram uint8_t msg_data; /* set config message data */
155971af9d46SMeenakshikumar Somasundaram };
156071af9d46SMeenakshikumar Somasundaram
156171af9d46SMeenakshikumar Somasundaram /**
156271af9d46SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
156371af9d46SMeenakshikumar Somasundaram */
156471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data {
156571af9d46SMeenakshikumar Somasundaram struct set_config_cmd_payload cmd_pkt;
156671af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */
156771af9d46SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned in case of error */
156871af9d46SMeenakshikumar Somasundaram };
156971af9d46SMeenakshikumar Somasundaram
157071af9d46SMeenakshikumar Somasundaram /**
157171af9d46SMeenakshikumar Somasundaram * DMUB command structure for SET_CONFIG command.
157271af9d46SMeenakshikumar Somasundaram */
157371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access {
157471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */
157571af9d46SMeenakshikumar Somasundaram struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
157671af9d46SMeenakshikumar Somasundaram };
157771af9d46SMeenakshikumar Somasundaram
157871af9d46SMeenakshikumar Somasundaram /**
1579139a3311SMeenakshikumar Somasundaram * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1580139a3311SMeenakshikumar Somasundaram */
1581139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data {
1582139a3311SMeenakshikumar Somasundaram uint8_t mst_alloc_slots; /* mst slots to be allotted */
1583139a3311SMeenakshikumar Somasundaram uint8_t instance; /* DPIA instance */
1584139a3311SMeenakshikumar Somasundaram uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1585139a3311SMeenakshikumar Somasundaram uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1586139a3311SMeenakshikumar Somasundaram };
1587139a3311SMeenakshikumar Somasundaram
1588139a3311SMeenakshikumar Somasundaram /**
1589139a3311SMeenakshikumar Somasundaram * DMUB command structure for SET_ command.
1590139a3311SMeenakshikumar Somasundaram */
1591139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots {
1592139a3311SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */
1593139a3311SMeenakshikumar Somasundaram struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1594139a3311SMeenakshikumar Somasundaram };
1595139a3311SMeenakshikumar Somasundaram
1596139a3311SMeenakshikumar Somasundaram /**
15976f4f8ff5SMeenakshikumar Somasundaram * DMUB command structure for DPIA HPD int enable control.
15986f4f8ff5SMeenakshikumar Somasundaram */
15996f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable {
16006f4f8ff5SMeenakshikumar Somasundaram struct dmub_cmd_header header; /* header */
16016f4f8ff5SMeenakshikumar Somasundaram uint32_t enable; /* dpia hpd interrupt enable */
16026f4f8ff5SMeenakshikumar Somasundaram };
16036f4f8ff5SMeenakshikumar Somasundaram
16046f4f8ff5SMeenakshikumar Somasundaram /**
1605592a6318SAnthony Koo * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1606592a6318SAnthony Koo */
16077c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init {
1608592a6318SAnthony Koo struct dmub_cmd_header header; /**< header */
1609592a6318SAnthony Koo uint8_t reserved[60]; /**< reserved bits */
16107c008829SNicholas Kazlauskas };
16117c008829SNicholas Kazlauskas
16121a595f28SAnthony Koo /**
16131a595f28SAnthony Koo * enum dp_aux_request_action - DP AUX request command listing.
16141a595f28SAnthony Koo *
16151a595f28SAnthony Koo * 4 AUX request command bits are shifted to high nibble.
16161a595f28SAnthony Koo */
1617d9beecfcSAnthony Koo enum dp_aux_request_action {
16181a595f28SAnthony Koo /** I2C-over-AUX write request */
1619d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
16201a595f28SAnthony Koo /** I2C-over-AUX read request */
1621d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ = 0x10,
16221a595f28SAnthony Koo /** I2C-over-AUX write status request */
1623d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
16241a595f28SAnthony Koo /** I2C-over-AUX write request with MOT=1 */
1625d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
16261a595f28SAnthony Koo /** I2C-over-AUX read request with MOT=1 */
1627d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
16281a595f28SAnthony Koo /** I2C-over-AUX write status request with MOT=1 */
1629d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
16301a595f28SAnthony Koo /** Native AUX write request */
1631d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
16321a595f28SAnthony Koo /** Native AUX read request */
1633d9beecfcSAnthony Koo DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1634d9beecfcSAnthony Koo };
1635d9beecfcSAnthony Koo
16361a595f28SAnthony Koo /**
16371a595f28SAnthony Koo * enum aux_return_code_type - DP AUX process return code listing.
16381a595f28SAnthony Koo */
1639fd0f1d21SAnthony Koo enum aux_return_code_type {
16401a595f28SAnthony Koo /** AUX process succeeded */
1641fd0f1d21SAnthony Koo AUX_RET_SUCCESS = 0,
16421a595f28SAnthony Koo /** AUX process failed with unknown reason */
1643b6402afeSAnthony Koo AUX_RET_ERROR_UNKNOWN,
16441a595f28SAnthony Koo /** AUX process completed with invalid reply */
1645b6402afeSAnthony Koo AUX_RET_ERROR_INVALID_REPLY,
16461a595f28SAnthony Koo /** AUX process timed out */
1647fd0f1d21SAnthony Koo AUX_RET_ERROR_TIMEOUT,
16481a595f28SAnthony Koo /** HPD was low during AUX process */
1649b6402afeSAnthony Koo AUX_RET_ERROR_HPD_DISCON,
16501a595f28SAnthony Koo /** Failed to acquire AUX engine */
1651b6402afeSAnthony Koo AUX_RET_ERROR_ENGINE_ACQUIRE,
16521a595f28SAnthony Koo /** AUX request not supported */
1653fd0f1d21SAnthony Koo AUX_RET_ERROR_INVALID_OPERATION,
16541a595f28SAnthony Koo /** AUX process not available */
1655fd0f1d21SAnthony Koo AUX_RET_ERROR_PROTOCOL_ERROR,
1656fd0f1d21SAnthony Koo };
1657fd0f1d21SAnthony Koo
16581a595f28SAnthony Koo /**
16591a595f28SAnthony Koo * enum aux_channel_type - DP AUX channel type listing.
16601a595f28SAnthony Koo */
1661b6402afeSAnthony Koo enum aux_channel_type {
16621a595f28SAnthony Koo /** AUX thru Legacy DP AUX */
1663b6402afeSAnthony Koo AUX_CHANNEL_LEGACY_DDC,
16641a595f28SAnthony Koo /** AUX thru DPIA DP tunneling */
1665b6402afeSAnthony Koo AUX_CHANNEL_DPIA
1666b6402afeSAnthony Koo };
1667b6402afeSAnthony Koo
16681a595f28SAnthony Koo /**
16691a595f28SAnthony Koo * struct aux_transaction_parameters - DP AUX request transaction data
16701a595f28SAnthony Koo */
1671d9beecfcSAnthony Koo struct aux_transaction_parameters {
16721a595f28SAnthony Koo uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
16731a595f28SAnthony Koo uint8_t action; /**< enum dp_aux_request_action */
16741a595f28SAnthony Koo uint8_t length; /**< DP AUX request data length */
16751a595f28SAnthony Koo uint8_t reserved; /**< For future use */
16761a595f28SAnthony Koo uint32_t address; /**< DP AUX address */
16771a595f28SAnthony Koo uint8_t data[16]; /**< DP AUX write data */
1678d9beecfcSAnthony Koo };
1679d9beecfcSAnthony Koo
16801a595f28SAnthony Koo /**
16811a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
16821a595f28SAnthony Koo */
1683d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data {
16841a595f28SAnthony Koo uint8_t instance; /**< AUX instance or DPIA instance */
16851a595f28SAnthony Koo uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
16861a595f28SAnthony Koo uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
16871a595f28SAnthony Koo uint8_t reserved0; /**< For future use */
16881a595f28SAnthony Koo uint16_t timeout; /**< timeout time in us */
16891a595f28SAnthony Koo uint16_t reserved1; /**< For future use */
16901a595f28SAnthony Koo enum aux_channel_type type; /**< enum aux_channel_type */
16911a595f28SAnthony Koo struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1692d9beecfcSAnthony Koo };
1693d9beecfcSAnthony Koo
16941a595f28SAnthony Koo /**
16951a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
16961a595f28SAnthony Koo */
1697d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access {
16981a595f28SAnthony Koo /**
16991a595f28SAnthony Koo * Command header.
17001a595f28SAnthony Koo */
1701d9beecfcSAnthony Koo struct dmub_cmd_header header;
17021a595f28SAnthony Koo /**
17031a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
17041a595f28SAnthony Koo */
1705d9beecfcSAnthony Koo struct dmub_cmd_dp_aux_control_data aux_control;
1706d9beecfcSAnthony Koo };
1707d9beecfcSAnthony Koo
17081a595f28SAnthony Koo /**
17091a595f28SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
17101a595f28SAnthony Koo */
1711d9beecfcSAnthony Koo struct dmub_rb_cmd_outbox1_enable {
17121a595f28SAnthony Koo /**
17131a595f28SAnthony Koo * Command header.
17141a595f28SAnthony Koo */
1715d9beecfcSAnthony Koo struct dmub_cmd_header header;
17161a595f28SAnthony Koo /**
17171a595f28SAnthony Koo * enable: 0x0 -> disable outbox1 notification (default value)
17181a595f28SAnthony Koo * 0x1 -> enable outbox1 notification
17191a595f28SAnthony Koo */
1720d9beecfcSAnthony Koo uint32_t enable;
1721d9beecfcSAnthony Koo };
1722d9beecfcSAnthony Koo
1723d9beecfcSAnthony Koo /* DP AUX Reply command - OutBox Cmd */
17241a595f28SAnthony Koo /**
17251a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
17261a595f28SAnthony Koo */
1727d9beecfcSAnthony Koo struct aux_reply_data {
17281a595f28SAnthony Koo /**
17291a595f28SAnthony Koo * Aux cmd
17301a595f28SAnthony Koo */
1731d9beecfcSAnthony Koo uint8_t command;
17321a595f28SAnthony Koo /**
17331a595f28SAnthony Koo * Aux reply data length (max: 16 bytes)
17341a595f28SAnthony Koo */
1735d9beecfcSAnthony Koo uint8_t length;
17361a595f28SAnthony Koo /**
17371a595f28SAnthony Koo * Alignment only
17381a595f28SAnthony Koo */
1739d9beecfcSAnthony Koo uint8_t pad[2];
17401a595f28SAnthony Koo /**
17411a595f28SAnthony Koo * Aux reply data
17421a595f28SAnthony Koo */
1743d9beecfcSAnthony Koo uint8_t data[16];
1744d9beecfcSAnthony Koo };
1745d9beecfcSAnthony Koo
17461a595f28SAnthony Koo /**
17471a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
17481a595f28SAnthony Koo */
1749d9beecfcSAnthony Koo struct aux_reply_control_data {
17501a595f28SAnthony Koo /**
17511a595f28SAnthony Koo * Reserved for future use
17521a595f28SAnthony Koo */
1753d9beecfcSAnthony Koo uint32_t handle;
17541a595f28SAnthony Koo /**
17551a595f28SAnthony Koo * Aux Instance
17561a595f28SAnthony Koo */
1757b6402afeSAnthony Koo uint8_t instance;
17581a595f28SAnthony Koo /**
17591a595f28SAnthony Koo * Aux transaction result: definition in enum aux_return_code_type
17601a595f28SAnthony Koo */
1761d9beecfcSAnthony Koo uint8_t result;
17621a595f28SAnthony Koo /**
17631a595f28SAnthony Koo * Alignment only
17641a595f28SAnthony Koo */
1765d9beecfcSAnthony Koo uint16_t pad;
1766d9beecfcSAnthony Koo };
1767d9beecfcSAnthony Koo
17681a595f28SAnthony Koo /**
17691a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
17701a595f28SAnthony Koo */
1771d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply {
17721a595f28SAnthony Koo /**
17731a595f28SAnthony Koo * Command header.
17741a595f28SAnthony Koo */
1775d9beecfcSAnthony Koo struct dmub_cmd_header header;
17761a595f28SAnthony Koo /**
17771a595f28SAnthony Koo * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
17781a595f28SAnthony Koo */
1779d9beecfcSAnthony Koo struct aux_reply_control_data control;
17801a595f28SAnthony Koo /**
17811a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
17821a595f28SAnthony Koo */
1783d9beecfcSAnthony Koo struct aux_reply_data reply_data;
1784d9beecfcSAnthony Koo };
1785d9beecfcSAnthony Koo
1786fd0f1d21SAnthony Koo /* DP HPD Notify command - OutBox Cmd */
17871a595f28SAnthony Koo /**
17881a595f28SAnthony Koo * DP HPD Type
17891a595f28SAnthony Koo */
1790fd0f1d21SAnthony Koo enum dp_hpd_type {
17911a595f28SAnthony Koo /**
17921a595f28SAnthony Koo * Normal DP HPD
17931a595f28SAnthony Koo */
1794fd0f1d21SAnthony Koo DP_HPD = 0,
17951a595f28SAnthony Koo /**
17961a595f28SAnthony Koo * DP HPD short pulse
17971a595f28SAnthony Koo */
1798fd0f1d21SAnthony Koo DP_IRQ
1799fd0f1d21SAnthony Koo };
1800fd0f1d21SAnthony Koo
18011a595f28SAnthony Koo /**
18021a595f28SAnthony Koo * DP HPD Status
18031a595f28SAnthony Koo */
1804fd0f1d21SAnthony Koo enum dp_hpd_status {
18051a595f28SAnthony Koo /**
18061a595f28SAnthony Koo * DP_HPD status low
18071a595f28SAnthony Koo */
1808fd0f1d21SAnthony Koo DP_HPD_UNPLUG = 0,
18091a595f28SAnthony Koo /**
18101a595f28SAnthony Koo * DP_HPD status high
18111a595f28SAnthony Koo */
1812fd0f1d21SAnthony Koo DP_HPD_PLUG
1813fd0f1d21SAnthony Koo };
1814fd0f1d21SAnthony Koo
18151a595f28SAnthony Koo /**
18161a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
18171a595f28SAnthony Koo */
1818d9beecfcSAnthony Koo struct dp_hpd_data {
18191a595f28SAnthony Koo /**
18201a595f28SAnthony Koo * DP HPD instance
18211a595f28SAnthony Koo */
1822b6402afeSAnthony Koo uint8_t instance;
18231a595f28SAnthony Koo /**
18241a595f28SAnthony Koo * HPD type
18251a595f28SAnthony Koo */
1826d9beecfcSAnthony Koo uint8_t hpd_type;
18271a595f28SAnthony Koo /**
18281a595f28SAnthony Koo * HPD status: only for type: DP_HPD to indicate status
18291a595f28SAnthony Koo */
1830d9beecfcSAnthony Koo uint8_t hpd_status;
18311a595f28SAnthony Koo /**
18321a595f28SAnthony Koo * Alignment only
18331a595f28SAnthony Koo */
1834d9beecfcSAnthony Koo uint8_t pad;
1835d9beecfcSAnthony Koo };
1836d9beecfcSAnthony Koo
18371a595f28SAnthony Koo /**
18381a595f28SAnthony Koo * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
18391a595f28SAnthony Koo */
1840d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify {
18411a595f28SAnthony Koo /**
18421a595f28SAnthony Koo * Command header.
18431a595f28SAnthony Koo */
1844d9beecfcSAnthony Koo struct dmub_cmd_header header;
18451a595f28SAnthony Koo /**
18461a595f28SAnthony Koo * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
18471a595f28SAnthony Koo */
1848d9beecfcSAnthony Koo struct dp_hpd_data hpd_data;
1849d9beecfcSAnthony Koo };
1850d9beecfcSAnthony Koo
185171af9d46SMeenakshikumar Somasundaram /**
185271af9d46SMeenakshikumar Somasundaram * Definition of a SET_CONFIG reply from DPOA.
185371af9d46SMeenakshikumar Somasundaram */
185471af9d46SMeenakshikumar Somasundaram enum set_config_status {
185571af9d46SMeenakshikumar Somasundaram SET_CONFIG_PENDING = 0,
185671af9d46SMeenakshikumar Somasundaram SET_CONFIG_ACK_RECEIVED,
185771af9d46SMeenakshikumar Somasundaram SET_CONFIG_RX_TIMEOUT,
185871af9d46SMeenakshikumar Somasundaram SET_CONFIG_UNKNOWN_ERROR,
185971af9d46SMeenakshikumar Somasundaram };
186071af9d46SMeenakshikumar Somasundaram
186171af9d46SMeenakshikumar Somasundaram /**
186271af9d46SMeenakshikumar Somasundaram * Definition of a set_config reply
186371af9d46SMeenakshikumar Somasundaram */
186471af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data {
186571af9d46SMeenakshikumar Somasundaram uint8_t instance; /* DPIA Instance */
186671af9d46SMeenakshikumar Somasundaram uint8_t status; /* Set Config reply */
186771af9d46SMeenakshikumar Somasundaram uint16_t pad; /* Alignment */
186871af9d46SMeenakshikumar Somasundaram };
186971af9d46SMeenakshikumar Somasundaram
187071af9d46SMeenakshikumar Somasundaram /**
187171af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
187271af9d46SMeenakshikumar Somasundaram */
187371af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply {
187471af9d46SMeenakshikumar Somasundaram struct dmub_cmd_header header;
187571af9d46SMeenakshikumar Somasundaram struct set_config_reply_control_data set_config_reply_control;
187671af9d46SMeenakshikumar Somasundaram };
187771af9d46SMeenakshikumar Somasundaram
1878ea5a4db9SAnthony Koo /**
18798af54c61SMustapha Ghaddar * Definition of a DPIA notification header
18808af54c61SMustapha Ghaddar */
18818af54c61SMustapha Ghaddar struct dpia_notification_header {
18828af54c61SMustapha Ghaddar uint8_t instance; /**< DPIA Instance */
18838af54c61SMustapha Ghaddar uint8_t reserved[3];
18848af54c61SMustapha Ghaddar enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
18858af54c61SMustapha Ghaddar };
18868af54c61SMustapha Ghaddar
18878af54c61SMustapha Ghaddar /**
18888af54c61SMustapha Ghaddar * Definition of the common data struct of DPIA notification
18898af54c61SMustapha Ghaddar */
18908af54c61SMustapha Ghaddar struct dpia_notification_common {
18918af54c61SMustapha Ghaddar uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
18928af54c61SMustapha Ghaddar - sizeof(struct dpia_notification_header)];
18938af54c61SMustapha Ghaddar };
18948af54c61SMustapha Ghaddar
18958af54c61SMustapha Ghaddar /**
18968af54c61SMustapha Ghaddar * Definition of a DPIA notification data
18978af54c61SMustapha Ghaddar */
18988af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data {
18998af54c61SMustapha Ghaddar union {
19008af54c61SMustapha Ghaddar struct {
19018af54c61SMustapha Ghaddar uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
19028af54c61SMustapha Ghaddar uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
19038af54c61SMustapha Ghaddar uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
19048af54c61SMustapha Ghaddar uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
19058af54c61SMustapha Ghaddar uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
19068af54c61SMustapha Ghaddar uint16_t reserved: 11; /**< Reserved */
19078af54c61SMustapha Ghaddar } bits;
19088af54c61SMustapha Ghaddar
19098af54c61SMustapha Ghaddar uint16_t flags;
19108af54c61SMustapha Ghaddar };
19118af54c61SMustapha Ghaddar
19128af54c61SMustapha Ghaddar uint8_t cm_id; /**< CM ID */
19138af54c61SMustapha Ghaddar uint8_t group_id; /**< Group ID */
19148af54c61SMustapha Ghaddar uint8_t granularity; /**< BW Allocation Granularity */
19158af54c61SMustapha Ghaddar uint8_t estimated_bw; /**< Estimated_BW */
19168af54c61SMustapha Ghaddar uint8_t allocated_bw; /**< Allocated_BW */
19178af54c61SMustapha Ghaddar uint8_t reserved;
19188af54c61SMustapha Ghaddar };
19198af54c61SMustapha Ghaddar
19208af54c61SMustapha Ghaddar /**
19218af54c61SMustapha Ghaddar * union dpia_notify_data_type - DPIA Notification in Outbox command
19228af54c61SMustapha Ghaddar */
19238af54c61SMustapha Ghaddar union dpia_notification_data {
19248af54c61SMustapha Ghaddar /**
19258af54c61SMustapha Ghaddar * DPIA Notification for common data struct
19268af54c61SMustapha Ghaddar */
19278af54c61SMustapha Ghaddar struct dpia_notification_common common_data;
19288af54c61SMustapha Ghaddar
19298af54c61SMustapha Ghaddar /**
19308af54c61SMustapha Ghaddar * DPIA Notification for DP BW Allocation support
19318af54c61SMustapha Ghaddar */
19328af54c61SMustapha Ghaddar struct dpia_bw_allocation_notify_data dpia_bw_alloc;
19338af54c61SMustapha Ghaddar };
19348af54c61SMustapha Ghaddar
19358af54c61SMustapha Ghaddar /**
19368af54c61SMustapha Ghaddar * Definition of a DPIA notification payload
19378af54c61SMustapha Ghaddar */
19388af54c61SMustapha Ghaddar struct dpia_notification_payload {
19398af54c61SMustapha Ghaddar struct dpia_notification_header header;
19408af54c61SMustapha Ghaddar union dpia_notification_data data; /**< DPIA notification payload data */
19418af54c61SMustapha Ghaddar };
19428af54c61SMustapha Ghaddar
19438af54c61SMustapha Ghaddar /**
19448af54c61SMustapha Ghaddar * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
19458af54c61SMustapha Ghaddar */
19468af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification {
19478af54c61SMustapha Ghaddar struct dmub_cmd_header header; /**< DPIA notification header */
19488af54c61SMustapha Ghaddar struct dpia_notification_payload payload; /**< DPIA notification payload */
19498af54c61SMustapha Ghaddar };
19508af54c61SMustapha Ghaddar
19518af54c61SMustapha Ghaddar /**
1952ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1953ea5a4db9SAnthony Koo */
1954ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data {
1955ea5a4db9SAnthony Koo uint8_t instance; /**< HPD instance or DPIA instance */
1956ea5a4db9SAnthony Koo uint8_t result; /**< For returning HPD state */
1957874714feSAnthony Koo uint16_t pad; /** < Alignment */
1958ea5a4db9SAnthony Koo enum aux_channel_type ch_type; /**< enum aux_channel_type */
1959ea5a4db9SAnthony Koo enum aux_return_code_type status; /**< for returning the status of command */
1960ea5a4db9SAnthony Koo };
1961ea5a4db9SAnthony Koo
1962ea5a4db9SAnthony Koo /**
1963ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
1964ea5a4db9SAnthony Koo */
1965ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state {
1966ea5a4db9SAnthony Koo /**
1967ea5a4db9SAnthony Koo * Command header.
1968ea5a4db9SAnthony Koo */
1969ea5a4db9SAnthony Koo struct dmub_cmd_header header;
1970ea5a4db9SAnthony Koo /**
1971ea5a4db9SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1972ea5a4db9SAnthony Koo */
1973ea5a4db9SAnthony Koo struct dmub_cmd_hpd_state_query_data data;
1974ea5a4db9SAnthony Koo };
1975ea5a4db9SAnthony Koo
197684034ad4SAnthony Koo /*
197784034ad4SAnthony Koo * Command IDs should be treated as stable ABI.
197884034ad4SAnthony Koo * Do not reuse or modify IDs.
197984034ad4SAnthony Koo */
198084034ad4SAnthony Koo
19811a595f28SAnthony Koo /**
19821a595f28SAnthony Koo * PSR command sub-types.
19831a595f28SAnthony Koo */
198484034ad4SAnthony Koo enum dmub_cmd_psr_type {
19851a595f28SAnthony Koo /**
19861a595f28SAnthony Koo * Set PSR version support.
19871a595f28SAnthony Koo */
198884034ad4SAnthony Koo DMUB_CMD__PSR_SET_VERSION = 0,
19891a595f28SAnthony Koo /**
19901a595f28SAnthony Koo * Copy driver-calculated parameters to PSR state.
19911a595f28SAnthony Koo */
199284034ad4SAnthony Koo DMUB_CMD__PSR_COPY_SETTINGS = 1,
19931a595f28SAnthony Koo /**
19941a595f28SAnthony Koo * Enable PSR.
19951a595f28SAnthony Koo */
199684034ad4SAnthony Koo DMUB_CMD__PSR_ENABLE = 2,
19971a595f28SAnthony Koo
19981a595f28SAnthony Koo /**
19991a595f28SAnthony Koo * Disable PSR.
20001a595f28SAnthony Koo */
200184034ad4SAnthony Koo DMUB_CMD__PSR_DISABLE = 3,
20021a595f28SAnthony Koo
20031a595f28SAnthony Koo /**
20041a595f28SAnthony Koo * Set PSR level.
20051a595f28SAnthony Koo * PSR level is a 16-bit value dicated by driver that
20061a595f28SAnthony Koo * will enable/disable different functionality.
20071a595f28SAnthony Koo */
200884034ad4SAnthony Koo DMUB_CMD__PSR_SET_LEVEL = 4,
20091a595f28SAnthony Koo
20101a595f28SAnthony Koo /**
20111a595f28SAnthony Koo * Forces PSR enabled until an explicit PSR disable call.
20121a595f28SAnthony Koo */
2013672251b2SAnthony Koo DMUB_CMD__PSR_FORCE_STATIC = 5,
2014e5dfcd27SRobin Chen /**
201583eb5385SDavid Zhang * Set vtotal in psr active for FreeSync PSR.
201683eb5385SDavid Zhang */
201783eb5385SDavid Zhang DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
201883eb5385SDavid Zhang /**
2019e5dfcd27SRobin Chen * Set PSR power option
2020e5dfcd27SRobin Chen */
2021e5dfcd27SRobin Chen DMUB_CMD__SET_PSR_POWER_OPT = 7,
202284034ad4SAnthony Koo };
202384034ad4SAnthony Koo
202485f4bc0cSAlvin Lee enum dmub_cmd_fams_type {
202585f4bc0cSAlvin Lee DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
202685f4bc0cSAlvin Lee DMUB_CMD__FAMS_DRR_UPDATE = 1,
202785f4bc0cSAlvin Lee DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
202881f776b6SAnthony Koo /**
202981f776b6SAnthony Koo * For SubVP set manual trigger in FW because it
203081f776b6SAnthony Koo * triggers DRR_UPDATE_PENDING which SubVP relies
203181f776b6SAnthony Koo * on (for any SubVP cases that use a DRR display)
203281f776b6SAnthony Koo */
203381f776b6SAnthony Koo DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
203485f4bc0cSAlvin Lee };
203585f4bc0cSAlvin Lee
20361a595f28SAnthony Koo /**
20371a595f28SAnthony Koo * PSR versions.
20381a595f28SAnthony Koo */
203984034ad4SAnthony Koo enum psr_version {
20401a595f28SAnthony Koo /**
20411a595f28SAnthony Koo * PSR version 1.
20421a595f28SAnthony Koo */
204384034ad4SAnthony Koo PSR_VERSION_1 = 0,
20441a595f28SAnthony Koo /**
204583eb5385SDavid Zhang * Freesync PSR SU.
204683eb5385SDavid Zhang */
204783eb5385SDavid Zhang PSR_VERSION_SU_1 = 1,
204883eb5385SDavid Zhang /**
20491a595f28SAnthony Koo * PSR not supported.
20501a595f28SAnthony Koo */
205184034ad4SAnthony Koo PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
205284034ad4SAnthony Koo };
205384034ad4SAnthony Koo
2054592a6318SAnthony Koo /**
2055592a6318SAnthony Koo * enum dmub_cmd_mall_type - MALL commands
2056592a6318SAnthony Koo */
205752f2e83eSBhawanpreet Lakha enum dmub_cmd_mall_type {
2058592a6318SAnthony Koo /**
2059592a6318SAnthony Koo * Allows display refresh from MALL.
2060592a6318SAnthony Koo */
206152f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_ALLOW = 0,
2062592a6318SAnthony Koo /**
2063592a6318SAnthony Koo * Disallows display refresh from MALL.
2064592a6318SAnthony Koo */
206552f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_DISALLOW = 1,
2066592a6318SAnthony Koo /**
2067592a6318SAnthony Koo * Cursor copy for MALL.
2068592a6318SAnthony Koo */
206952f2e83eSBhawanpreet Lakha DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
2070592a6318SAnthony Koo /**
2071592a6318SAnthony Koo * Controls DF requests.
2072592a6318SAnthony Koo */
2073ea7154d8SBhawanpreet Lakha DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
207452f2e83eSBhawanpreet Lakha };
207552f2e83eSBhawanpreet Lakha
2076a91b402dSCharlene Liu /**
207778174f47SAnthony Koo * PHY Link rate for DP.
207878174f47SAnthony Koo */
207978174f47SAnthony Koo enum phy_link_rate {
208078174f47SAnthony Koo /**
208178174f47SAnthony Koo * not supported.
208278174f47SAnthony Koo */
208378174f47SAnthony Koo PHY_RATE_UNKNOWN = 0,
208478174f47SAnthony Koo /**
208578174f47SAnthony Koo * Rate_1 (RBR) - 1.62 Gbps/Lane
208678174f47SAnthony Koo */
208778174f47SAnthony Koo PHY_RATE_162 = 1,
208878174f47SAnthony Koo /**
208978174f47SAnthony Koo * Rate_2 - 2.16 Gbps/Lane
209078174f47SAnthony Koo */
209178174f47SAnthony Koo PHY_RATE_216 = 2,
209278174f47SAnthony Koo /**
209378174f47SAnthony Koo * Rate_3 - 2.43 Gbps/Lane
209478174f47SAnthony Koo */
209578174f47SAnthony Koo PHY_RATE_243 = 3,
209678174f47SAnthony Koo /**
209778174f47SAnthony Koo * Rate_4 (HBR) - 2.70 Gbps/Lane
209878174f47SAnthony Koo */
209978174f47SAnthony Koo PHY_RATE_270 = 4,
210078174f47SAnthony Koo /**
210178174f47SAnthony Koo * Rate_5 (RBR2)- 3.24 Gbps/Lane
210278174f47SAnthony Koo */
210378174f47SAnthony Koo PHY_RATE_324 = 5,
210478174f47SAnthony Koo /**
210578174f47SAnthony Koo * Rate_6 - 4.32 Gbps/Lane
210678174f47SAnthony Koo */
210778174f47SAnthony Koo PHY_RATE_432 = 6,
210878174f47SAnthony Koo /**
210978174f47SAnthony Koo * Rate_7 (HBR2)- 5.40 Gbps/Lane
211078174f47SAnthony Koo */
211178174f47SAnthony Koo PHY_RATE_540 = 7,
211278174f47SAnthony Koo /**
211378174f47SAnthony Koo * Rate_8 (HBR3)- 8.10 Gbps/Lane
211478174f47SAnthony Koo */
211578174f47SAnthony Koo PHY_RATE_810 = 8,
211678174f47SAnthony Koo /**
211778174f47SAnthony Koo * UHBR10 - 10.0 Gbps/Lane
211878174f47SAnthony Koo */
211978174f47SAnthony Koo PHY_RATE_1000 = 9,
212078174f47SAnthony Koo /**
212178174f47SAnthony Koo * UHBR13.5 - 13.5 Gbps/Lane
212278174f47SAnthony Koo */
212378174f47SAnthony Koo PHY_RATE_1350 = 10,
212478174f47SAnthony Koo /**
212578174f47SAnthony Koo * UHBR10 - 20.0 Gbps/Lane
212678174f47SAnthony Koo */
212778174f47SAnthony Koo PHY_RATE_2000 = 11,
212878174f47SAnthony Koo };
212978174f47SAnthony Koo
213078174f47SAnthony Koo /**
213178174f47SAnthony Koo * enum dmub_phy_fsm_state - PHY FSM states.
213278174f47SAnthony Koo * PHY FSM state to transit to during PSR enable/disable.
213378174f47SAnthony Koo */
213478174f47SAnthony Koo enum dmub_phy_fsm_state {
213578174f47SAnthony Koo DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
213678174f47SAnthony Koo DMUB_PHY_FSM_RESET,
213778174f47SAnthony Koo DMUB_PHY_FSM_RESET_RELEASED,
213878174f47SAnthony Koo DMUB_PHY_FSM_SRAM_LOAD_DONE,
213978174f47SAnthony Koo DMUB_PHY_FSM_INITIALIZED,
214078174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED,
214178174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_LP,
214278174f47SAnthony Koo DMUB_PHY_FSM_CALIBRATED_PG,
214378174f47SAnthony Koo DMUB_PHY_FSM_POWER_DOWN,
214478174f47SAnthony Koo DMUB_PHY_FSM_PLL_EN,
214578174f47SAnthony Koo DMUB_PHY_FSM_TX_EN,
214678174f47SAnthony Koo DMUB_PHY_FSM_FAST_LP,
21472e0847a7SAnthony Koo DMUB_PHY_FSM_P2_PLL_OFF_CPM,
21482e0847a7SAnthony Koo DMUB_PHY_FSM_P2_PLL_OFF_PG,
21492e0847a7SAnthony Koo DMUB_PHY_FSM_P2_PLL_OFF,
21502e0847a7SAnthony Koo DMUB_PHY_FSM_P2_PLL_ON,
215178174f47SAnthony Koo };
215278174f47SAnthony Koo
215378174f47SAnthony Koo /**
21541a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
21551a595f28SAnthony Koo */
21567c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data {
21571a595f28SAnthony Koo /**
21581a595f28SAnthony Koo * Flags that can be set by driver to change some PSR behaviour.
21591a595f28SAnthony Koo */
21607b8a6362SAnthony Koo union dmub_psr_debug_flags debug;
21611a595f28SAnthony Koo /**
21621a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality.
21631a595f28SAnthony Koo */
21644c1a1335SWyatt Wood uint16_t psr_level;
21651a595f28SAnthony Koo /**
21661a595f28SAnthony Koo * DPP HW instance.
21671a595f28SAnthony Koo */
21684c1a1335SWyatt Wood uint8_t dpp_inst;
21691a595f28SAnthony Koo /**
21701a595f28SAnthony Koo * MPCC HW instance.
21711a595f28SAnthony Koo * Not used in dmub fw,
217234ba432cSAnthony Koo * dmub fw will get active opp by reading odm registers.
217334ba432cSAnthony Koo */
21744c1a1335SWyatt Wood uint8_t mpcc_inst;
21751a595f28SAnthony Koo /**
21761a595f28SAnthony Koo * OPP HW instance.
21771a595f28SAnthony Koo * Not used in dmub fw,
21781a595f28SAnthony Koo * dmub fw will get active opp by reading odm registers.
21791a595f28SAnthony Koo */
21804c1a1335SWyatt Wood uint8_t opp_inst;
21811a595f28SAnthony Koo /**
21821a595f28SAnthony Koo * OTG HW instance.
21831a595f28SAnthony Koo */
21844c1a1335SWyatt Wood uint8_t otg_inst;
21851a595f28SAnthony Koo /**
21861a595f28SAnthony Koo * DIG FE HW instance.
21871a595f28SAnthony Koo */
21884c1a1335SWyatt Wood uint8_t digfe_inst;
21891a595f28SAnthony Koo /**
21901a595f28SAnthony Koo * DIG BE HW instance.
21911a595f28SAnthony Koo */
21924c1a1335SWyatt Wood uint8_t digbe_inst;
21931a595f28SAnthony Koo /**
21941a595f28SAnthony Koo * DP PHY HW instance.
21951a595f28SAnthony Koo */
21964c1a1335SWyatt Wood uint8_t dpphy_inst;
21971a595f28SAnthony Koo /**
21981a595f28SAnthony Koo * AUX HW instance.
21991a595f28SAnthony Koo */
22004c1a1335SWyatt Wood uint8_t aux_inst;
22011a595f28SAnthony Koo /**
22021a595f28SAnthony Koo * Determines if SMU optimzations are enabled/disabled.
22031a595f28SAnthony Koo */
22044c1a1335SWyatt Wood uint8_t smu_optimizations_en;
22051a595f28SAnthony Koo /**
22061a595f28SAnthony Koo * Unused.
22071a595f28SAnthony Koo * TODO: Remove.
22081a595f28SAnthony Koo */
22094c1a1335SWyatt Wood uint8_t frame_delay;
22101a595f28SAnthony Koo /**
22111a595f28SAnthony Koo * If RFB setup time is greater than the total VBLANK time,
22121a595f28SAnthony Koo * it is not possible for the sink to capture the video frame
22131a595f28SAnthony Koo * in the same frame the SDP is sent. In this case,
22141a595f28SAnthony Koo * the frame capture indication bit should be set and an extra
22151a595f28SAnthony Koo * static frame should be transmitted to the sink.
22161a595f28SAnthony Koo */
22174c1a1335SWyatt Wood uint8_t frame_cap_ind;
22181a595f28SAnthony Koo /**
221983eb5385SDavid Zhang * Granularity of Y offset supported by sink.
22201a595f28SAnthony Koo */
222183eb5385SDavid Zhang uint8_t su_y_granularity;
222283eb5385SDavid Zhang /**
222383eb5385SDavid Zhang * Indicates whether sink should start capturing
222483eb5385SDavid Zhang * immediately following active scan line,
222583eb5385SDavid Zhang * or starting with the 2nd active scan line.
222683eb5385SDavid Zhang */
222783eb5385SDavid Zhang uint8_t line_capture_indication;
22281a595f28SAnthony Koo /**
22291a595f28SAnthony Koo * Multi-display optimizations are implemented on certain ASICs.
22301a595f28SAnthony Koo */
2231175f0971SYongqiang Sun uint8_t multi_disp_optimizations_en;
22321a595f28SAnthony Koo /**
22331a595f28SAnthony Koo * The last possible line SDP may be transmitted without violating
22341a595f28SAnthony Koo * the RFB setup time or entering the active video frame.
22351a595f28SAnthony Koo */
223678ead771SAnthony Koo uint16_t init_sdp_deadline;
22371a595f28SAnthony Koo /**
223883eb5385SDavid Zhang * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
22391a595f28SAnthony Koo */
224083eb5385SDavid Zhang uint8_t rate_control_caps ;
224183eb5385SDavid Zhang /*
224283eb5385SDavid Zhang * Force PSRSU always doing full frame update
224383eb5385SDavid Zhang */
224483eb5385SDavid Zhang uint8_t force_ffu_mode;
22451a595f28SAnthony Koo /**
22461a595f28SAnthony Koo * Length of each horizontal line in us.
22471a595f28SAnthony Koo */
22489b56f6bcSAnthony Koo uint32_t line_time_in_us;
2249ecc11601SAnthony Koo /**
2250ecc11601SAnthony Koo * FEC enable status in driver
2251ecc11601SAnthony Koo */
2252ecc11601SAnthony Koo uint8_t fec_enable_status;
2253ecc11601SAnthony Koo /**
2254ecc11601SAnthony Koo * FEC re-enable delay when PSR exit.
2255ecc11601SAnthony Koo * unit is 100us, range form 0~255(0xFF).
2256ecc11601SAnthony Koo */
2257ecc11601SAnthony Koo uint8_t fec_enable_delay_in100us;
2258ecc11601SAnthony Koo /**
2259f56c837aSMikita Lipski * PSR control version.
2260ecc11601SAnthony Koo */
2261f56c837aSMikita Lipski uint8_t cmd_version;
2262f56c837aSMikita Lipski /**
2263f56c837aSMikita Lipski * Panel Instance.
226436e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
2265f56c837aSMikita Lipski * Currently the support is only for 0 or 1
2266f56c837aSMikita Lipski */
2267f56c837aSMikita Lipski uint8_t panel_inst;
22682665f63aSMikita Lipski /*
22692665f63aSMikita Lipski * DSC enable status in driver
2270360d1b65SIan Chen */
22712665f63aSMikita Lipski uint8_t dsc_enable_status;
2272b5175966SShah Dharati /*
2273b5175966SShah Dharati * Use FSM state for PSR power up/down
22742665f63aSMikita Lipski */
2275b5175966SShah Dharati uint8_t use_phy_fsm;
2276b5175966SShah Dharati /**
22771a2b886bSRyan Lin * frame delay for frame re-lock
22781a2b886bSRyan Lin */
22791a2b886bSRyan Lin uint8_t relock_delay_frame_cnt;
22801a2b886bSRyan Lin /**
2281b5175966SShah Dharati * Explicit padding to 2 byte boundary.
2282b5175966SShah Dharati */
22831a2b886bSRyan Lin uint8_t pad3;
2284c84ff24aSRobin Chen /**
2285c84ff24aSRobin Chen * DSC Slice height.
2286c84ff24aSRobin Chen */
2287c84ff24aSRobin Chen uint16_t dsc_slice_height;
2288c84ff24aSRobin Chen /**
2289c84ff24aSRobin Chen * Explicit padding to 4 byte boundary.
2290c84ff24aSRobin Chen */
2291c84ff24aSRobin Chen uint16_t pad;
22927c008829SNicholas Kazlauskas };
22937c008829SNicholas Kazlauskas
22941a595f28SAnthony Koo /**
22951a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
22961a595f28SAnthony Koo */
22977c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings {
22981a595f28SAnthony Koo /**
22991a595f28SAnthony Koo * Command header.
23001a595f28SAnthony Koo */
23017c008829SNicholas Kazlauskas struct dmub_cmd_header header;
23021a595f28SAnthony Koo /**
23031a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
23041a595f28SAnthony Koo */
23057c008829SNicholas Kazlauskas struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
23067c008829SNicholas Kazlauskas };
23077c008829SNicholas Kazlauskas
23081a595f28SAnthony Koo /**
23091a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
23101a595f28SAnthony Koo */
23117c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data {
23121a595f28SAnthony Koo /**
23131a595f28SAnthony Koo * 16-bit value dicated by driver that will enable/disable different functionality.
23141a595f28SAnthony Koo */
23157c008829SNicholas Kazlauskas uint16_t psr_level;
23161a595f28SAnthony Koo /**
2317f56c837aSMikita Lipski * PSR control version.
23181a595f28SAnthony Koo */
2319f56c837aSMikita Lipski uint8_t cmd_version;
2320f56c837aSMikita Lipski /**
2321f56c837aSMikita Lipski * Panel Instance.
232236e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
2323f56c837aSMikita Lipski * Currently the support is only for 0 or 1
2324f56c837aSMikita Lipski */
2325f56c837aSMikita Lipski uint8_t panel_inst;
23267c008829SNicholas Kazlauskas };
23277c008829SNicholas Kazlauskas
23281a595f28SAnthony Koo /**
23291a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
23301a595f28SAnthony Koo */
23317c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level {
23321a595f28SAnthony Koo /**
23331a595f28SAnthony Koo * Command header.
23341a595f28SAnthony Koo */
23357c008829SNicholas Kazlauskas struct dmub_cmd_header header;
23361a595f28SAnthony Koo /**
23371a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
23381a595f28SAnthony Koo */
23397c008829SNicholas Kazlauskas struct dmub_cmd_psr_set_level_data psr_set_level_data;
23407c008829SNicholas Kazlauskas };
23417c008829SNicholas Kazlauskas
2342f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data {
2343f56c837aSMikita Lipski /**
2344f56c837aSMikita Lipski * PSR control version.
2345f56c837aSMikita Lipski */
2346f56c837aSMikita Lipski uint8_t cmd_version;
2347f56c837aSMikita Lipski /**
2348f56c837aSMikita Lipski * Panel Instance.
234936e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
2350f56c837aSMikita Lipski * Currently the support is only for 0 or 1
2351f56c837aSMikita Lipski */
2352f56c837aSMikita Lipski uint8_t panel_inst;
2353f56c837aSMikita Lipski /**
235478174f47SAnthony Koo * Phy state to enter.
235578174f47SAnthony Koo * Values to use are defined in dmub_phy_fsm_state
2356f56c837aSMikita Lipski */
235778174f47SAnthony Koo uint8_t phy_fsm_state;
235878174f47SAnthony Koo /**
235978174f47SAnthony Koo * Phy rate for DP - RBR/HBR/HBR2/HBR3.
236078174f47SAnthony Koo * Set this using enum phy_link_rate.
236178174f47SAnthony Koo * This does not support HDMI/DP2 for now.
236278174f47SAnthony Koo */
236378174f47SAnthony Koo uint8_t phy_rate;
2364f56c837aSMikita Lipski };
2365f56c837aSMikita Lipski
23661a595f28SAnthony Koo /**
23671a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command.
23681a595f28SAnthony Koo * PSR enable/disable is controlled using the sub_type.
23691a595f28SAnthony Koo */
23707c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_enable {
23711a595f28SAnthony Koo /**
23721a595f28SAnthony Koo * Command header.
23731a595f28SAnthony Koo */
23747c008829SNicholas Kazlauskas struct dmub_cmd_header header;
2375f56c837aSMikita Lipski
2376f56c837aSMikita Lipski struct dmub_rb_cmd_psr_enable_data data;
23777c008829SNicholas Kazlauskas };
23787c008829SNicholas Kazlauskas
23791a595f28SAnthony Koo /**
23801a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
23811a595f28SAnthony Koo */
2382d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data {
23831a595f28SAnthony Koo /**
23841a595f28SAnthony Koo * PSR version that FW should implement.
23851a595f28SAnthony Koo */
23861a595f28SAnthony Koo enum psr_version version;
2387f56c837aSMikita Lipski /**
2388f56c837aSMikita Lipski * PSR control version.
2389f56c837aSMikita Lipski */
2390f56c837aSMikita Lipski uint8_t cmd_version;
2391f56c837aSMikita Lipski /**
2392f56c837aSMikita Lipski * Panel Instance.
239336e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
2394f56c837aSMikita Lipski * Currently the support is only for 0 or 1
2395f56c837aSMikita Lipski */
2396f56c837aSMikita Lipski uint8_t panel_inst;
2397f56c837aSMikita Lipski /**
2398f56c837aSMikita Lipski * Explicit padding to 4 byte boundary.
2399f56c837aSMikita Lipski */
2400f56c837aSMikita Lipski uint8_t pad[2];
24017c008829SNicholas Kazlauskas };
24027c008829SNicholas Kazlauskas
24031a595f28SAnthony Koo /**
24041a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command.
24051a595f28SAnthony Koo */
2406d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version {
24071a595f28SAnthony Koo /**
24081a595f28SAnthony Koo * Command header.
24091a595f28SAnthony Koo */
24107c008829SNicholas Kazlauskas struct dmub_cmd_header header;
24111a595f28SAnthony Koo /**
24121a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
24131a595f28SAnthony Koo */
2414d4b8573eSWyatt Wood struct dmub_cmd_psr_set_version_data psr_set_version_data;
24157c008829SNicholas Kazlauskas };
24167c008829SNicholas Kazlauskas
2417f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data {
2418f56c837aSMikita Lipski /**
2419f56c837aSMikita Lipski * PSR control version.
2420f56c837aSMikita Lipski */
2421f56c837aSMikita Lipski uint8_t cmd_version;
2422f56c837aSMikita Lipski /**
2423f56c837aSMikita Lipski * Panel Instance.
242436e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
2425f56c837aSMikita Lipski * Currently the support is only for 0 or 1
2426f56c837aSMikita Lipski */
2427f56c837aSMikita Lipski uint8_t panel_inst;
2428f56c837aSMikita Lipski /**
2429ad371c8aSAnthony Koo * Explicit padding to 4 byte boundary.
2430f56c837aSMikita Lipski */
2431ad371c8aSAnthony Koo uint8_t pad[2];
2432f56c837aSMikita Lipski };
2433f56c837aSMikita Lipski
24341a595f28SAnthony Koo /**
24351a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
24361a595f28SAnthony Koo */
2437672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static {
24381a595f28SAnthony Koo /**
24391a595f28SAnthony Koo * Command header.
24401a595f28SAnthony Koo */
2441672251b2SAnthony Koo struct dmub_cmd_header header;
2442f56c837aSMikita Lipski /**
2443f56c837aSMikita Lipski * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2444f56c837aSMikita Lipski */
2445f56c837aSMikita Lipski struct dmub_cmd_psr_force_static_data psr_force_static_data;
2446672251b2SAnthony Koo };
2447672251b2SAnthony Koo
24481a595f28SAnthony Koo /**
244983eb5385SDavid Zhang * PSR SU debug flags.
245083eb5385SDavid Zhang */
245183eb5385SDavid Zhang union dmub_psr_su_debug_flags {
245283eb5385SDavid Zhang /**
245383eb5385SDavid Zhang * PSR SU debug flags.
245483eb5385SDavid Zhang */
245583eb5385SDavid Zhang struct {
245683eb5385SDavid Zhang /**
245783eb5385SDavid Zhang * Update dirty rect in SW only.
245883eb5385SDavid Zhang */
245983eb5385SDavid Zhang uint8_t update_dirty_rect_only : 1;
246083eb5385SDavid Zhang /**
246183eb5385SDavid Zhang * Reset the cursor/plane state before processing the call.
246283eb5385SDavid Zhang */
246383eb5385SDavid Zhang uint8_t reset_state : 1;
246483eb5385SDavid Zhang } bitfields;
246583eb5385SDavid Zhang
246683eb5385SDavid Zhang /**
246783eb5385SDavid Zhang * Union for debug flags.
246883eb5385SDavid Zhang */
246983eb5385SDavid Zhang uint32_t u32All;
247083eb5385SDavid Zhang };
247183eb5385SDavid Zhang
247283eb5385SDavid Zhang /**
247383eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
247483eb5385SDavid Zhang * This triggers a selective update for PSR SU.
247583eb5385SDavid Zhang */
247683eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data {
247783eb5385SDavid Zhang /**
247883eb5385SDavid Zhang * Dirty rects from OS.
247983eb5385SDavid Zhang */
248083eb5385SDavid Zhang struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
248183eb5385SDavid Zhang /**
248283eb5385SDavid Zhang * PSR SU debug flags.
248383eb5385SDavid Zhang */
248483eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags;
248583eb5385SDavid Zhang /**
248683eb5385SDavid Zhang * OTG HW instance.
248783eb5385SDavid Zhang */
248883eb5385SDavid Zhang uint8_t pipe_idx;
248983eb5385SDavid Zhang /**
249083eb5385SDavid Zhang * Number of dirty rects.
249183eb5385SDavid Zhang */
249283eb5385SDavid Zhang uint8_t dirty_rect_count;
249383eb5385SDavid Zhang /**
249483eb5385SDavid Zhang * PSR control version.
249583eb5385SDavid Zhang */
249683eb5385SDavid Zhang uint8_t cmd_version;
249783eb5385SDavid Zhang /**
249883eb5385SDavid Zhang * Panel Instance.
249936e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
250083eb5385SDavid Zhang * Currently the support is only for 0 or 1
250183eb5385SDavid Zhang */
250283eb5385SDavid Zhang uint8_t panel_inst;
250383eb5385SDavid Zhang };
250483eb5385SDavid Zhang
250583eb5385SDavid Zhang /**
250683eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
250783eb5385SDavid Zhang */
250883eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect {
250983eb5385SDavid Zhang /**
251083eb5385SDavid Zhang * Command header.
251183eb5385SDavid Zhang */
251283eb5385SDavid Zhang struct dmub_cmd_header header;
251383eb5385SDavid Zhang /**
251483eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
251583eb5385SDavid Zhang */
251683eb5385SDavid Zhang struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
251783eb5385SDavid Zhang };
251883eb5385SDavid Zhang
251983eb5385SDavid Zhang /**
252083eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
252183eb5385SDavid Zhang */
2522b73353f7SMax Tseng union dmub_reg_cursor_control_cfg {
2523b73353f7SMax Tseng struct {
2524b73353f7SMax Tseng uint32_t cur_enable: 1;
2525b73353f7SMax Tseng uint32_t reser0: 3;
2526b73353f7SMax Tseng uint32_t cur_2x_magnify: 1;
2527b73353f7SMax Tseng uint32_t reser1: 3;
2528b73353f7SMax Tseng uint32_t mode: 3;
2529b73353f7SMax Tseng uint32_t reser2: 5;
2530b73353f7SMax Tseng uint32_t pitch: 2;
2531b73353f7SMax Tseng uint32_t reser3: 6;
2532b73353f7SMax Tseng uint32_t line_per_chunk: 5;
2533b73353f7SMax Tseng uint32_t reser4: 3;
2534b73353f7SMax Tseng } bits;
2535b73353f7SMax Tseng uint32_t raw;
2536b73353f7SMax Tseng };
2537b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp {
2538b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl;
2539b73353f7SMax Tseng union dmub_reg_position_cfg {
2540b73353f7SMax Tseng struct {
2541b73353f7SMax Tseng uint32_t cur_x_pos: 16;
2542b73353f7SMax Tseng uint32_t cur_y_pos: 16;
2543b73353f7SMax Tseng } bits;
2544b73353f7SMax Tseng uint32_t raw;
2545b73353f7SMax Tseng } position;
2546b73353f7SMax Tseng union dmub_reg_hot_spot_cfg {
2547b73353f7SMax Tseng struct {
2548b73353f7SMax Tseng uint32_t hot_x: 16;
2549b73353f7SMax Tseng uint32_t hot_y: 16;
2550b73353f7SMax Tseng } bits;
2551b73353f7SMax Tseng uint32_t raw;
2552b73353f7SMax Tseng } hot_spot;
2553b73353f7SMax Tseng union dmub_reg_dst_offset_cfg {
2554b73353f7SMax Tseng struct {
2555b73353f7SMax Tseng uint32_t dst_x_offset: 13;
2556b73353f7SMax Tseng uint32_t reserved: 19;
2557b73353f7SMax Tseng } bits;
2558b73353f7SMax Tseng uint32_t raw;
2559b73353f7SMax Tseng } dst_offset;
2560b73353f7SMax Tseng };
2561b73353f7SMax Tseng
2562b73353f7SMax Tseng union dmub_reg_cur0_control_cfg {
2563b73353f7SMax Tseng struct {
2564b73353f7SMax Tseng uint32_t cur0_enable: 1;
2565b73353f7SMax Tseng uint32_t expansion_mode: 1;
2566b73353f7SMax Tseng uint32_t reser0: 1;
2567b73353f7SMax Tseng uint32_t cur0_rom_en: 1;
2568b73353f7SMax Tseng uint32_t mode: 3;
2569b73353f7SMax Tseng uint32_t reserved: 25;
2570b73353f7SMax Tseng } bits;
2571b73353f7SMax Tseng uint32_t raw;
2572b73353f7SMax Tseng };
2573b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp {
2574b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl;
2575b73353f7SMax Tseng };
2576b73353f7SMax Tseng struct dmub_cursor_position_cfg {
2577b73353f7SMax Tseng struct dmub_cursor_position_cache_hubp pHubp;
2578b73353f7SMax Tseng struct dmub_cursor_position_cache_dpp pDpp;
2579b73353f7SMax Tseng uint8_t pipe_idx;
2580b73353f7SMax Tseng /*
2581b73353f7SMax Tseng * Padding is required. To be 4 Bytes Aligned.
2582b73353f7SMax Tseng */
2583b73353f7SMax Tseng uint8_t padding[3];
2584b73353f7SMax Tseng };
2585b73353f7SMax Tseng
2586b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp {
2587b73353f7SMax Tseng uint32_t SURFACE_ADDR_HIGH;
2588b73353f7SMax Tseng uint32_t SURFACE_ADDR;
2589b73353f7SMax Tseng union dmub_reg_cursor_control_cfg cur_ctl;
2590b73353f7SMax Tseng union dmub_reg_cursor_size_cfg {
2591b73353f7SMax Tseng struct {
2592b73353f7SMax Tseng uint32_t width: 16;
2593b73353f7SMax Tseng uint32_t height: 16;
2594b73353f7SMax Tseng } bits;
2595b73353f7SMax Tseng uint32_t raw;
2596b73353f7SMax Tseng } size;
2597b73353f7SMax Tseng union dmub_reg_cursor_settings_cfg {
2598b73353f7SMax Tseng struct {
2599b73353f7SMax Tseng uint32_t dst_y_offset: 8;
2600b73353f7SMax Tseng uint32_t chunk_hdl_adjust: 2;
2601b73353f7SMax Tseng uint32_t reserved: 22;
2602b73353f7SMax Tseng } bits;
2603b73353f7SMax Tseng uint32_t raw;
2604b73353f7SMax Tseng } settings;
2605b73353f7SMax Tseng };
2606b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp {
2607b73353f7SMax Tseng union dmub_reg_cur0_control_cfg cur0_ctl;
2608b73353f7SMax Tseng };
2609b73353f7SMax Tseng struct dmub_cursor_attributes_cfg {
2610b73353f7SMax Tseng struct dmub_cursor_attribute_cache_hubp aHubp;
2611b73353f7SMax Tseng struct dmub_cursor_attribute_cache_dpp aDpp;
2612b73353f7SMax Tseng };
2613b73353f7SMax Tseng
2614b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 {
261583eb5385SDavid Zhang /**
261683eb5385SDavid Zhang * Cursor dirty rects.
261783eb5385SDavid Zhang */
261883eb5385SDavid Zhang struct dmub_rect cursor_rect;
261983eb5385SDavid Zhang /**
262083eb5385SDavid Zhang * PSR SU debug flags.
262183eb5385SDavid Zhang */
262283eb5385SDavid Zhang union dmub_psr_su_debug_flags debug_flags;
262383eb5385SDavid Zhang /**
262483eb5385SDavid Zhang * Cursor enable/disable.
262583eb5385SDavid Zhang */
262683eb5385SDavid Zhang uint8_t enable;
262783eb5385SDavid Zhang /**
262883eb5385SDavid Zhang * OTG HW instance.
262983eb5385SDavid Zhang */
263083eb5385SDavid Zhang uint8_t pipe_idx;
263183eb5385SDavid Zhang /**
263283eb5385SDavid Zhang * PSR control version.
263383eb5385SDavid Zhang */
263483eb5385SDavid Zhang uint8_t cmd_version;
263583eb5385SDavid Zhang /**
263683eb5385SDavid Zhang * Panel Instance.
263736e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
263883eb5385SDavid Zhang * Currently the support is only for 0 or 1
263983eb5385SDavid Zhang */
264083eb5385SDavid Zhang uint8_t panel_inst;
2641b73353f7SMax Tseng /**
2642b73353f7SMax Tseng * Cursor Position Register.
2643b73353f7SMax Tseng * Registers contains Hubp & Dpp modules
2644b73353f7SMax Tseng */
2645b73353f7SMax Tseng struct dmub_cursor_position_cfg position_cfg;
2646b73353f7SMax Tseng };
2647b73353f7SMax Tseng
2648b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 {
2649b73353f7SMax Tseng struct dmub_cursor_attributes_cfg attribute_cfg;
2650b73353f7SMax Tseng };
2651b73353f7SMax Tseng
2652b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data {
2653b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload0 payload0;
2654b73353f7SMax Tseng struct dmub_cmd_update_cursor_payload1 payload1;
265583eb5385SDavid Zhang };
265683eb5385SDavid Zhang /**
265783eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
265883eb5385SDavid Zhang */
265983eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info {
266083eb5385SDavid Zhang /**
266183eb5385SDavid Zhang * Command header.
266283eb5385SDavid Zhang */
266383eb5385SDavid Zhang struct dmub_cmd_header header;
266483eb5385SDavid Zhang /**
266583eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
266683eb5385SDavid Zhang */
2667b73353f7SMax Tseng union dmub_cmd_update_cursor_info_data update_cursor_info_data;
266883eb5385SDavid Zhang };
266983eb5385SDavid Zhang
267083eb5385SDavid Zhang /**
267183eb5385SDavid Zhang * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
267283eb5385SDavid Zhang */
267383eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data {
267483eb5385SDavid Zhang /**
267583eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
267683eb5385SDavid Zhang */
267783eb5385SDavid Zhang uint16_t psr_vtotal_idle;
267883eb5385SDavid Zhang /**
267983eb5385SDavid Zhang * PSR control version.
268083eb5385SDavid Zhang */
268183eb5385SDavid Zhang uint8_t cmd_version;
268283eb5385SDavid Zhang /**
268383eb5385SDavid Zhang * Panel Instance.
268436e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
268583eb5385SDavid Zhang * Currently the support is only for 0 or 1
268683eb5385SDavid Zhang */
268783eb5385SDavid Zhang uint8_t panel_inst;
268883eb5385SDavid Zhang /*
268983eb5385SDavid Zhang * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
269083eb5385SDavid Zhang */
269183eb5385SDavid Zhang uint16_t psr_vtotal_su;
269283eb5385SDavid Zhang /**
269383eb5385SDavid Zhang * Explicit padding to 4 byte boundary.
269483eb5385SDavid Zhang */
269583eb5385SDavid Zhang uint8_t pad2[2];
269683eb5385SDavid Zhang };
269783eb5385SDavid Zhang
269883eb5385SDavid Zhang /**
269983eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
270083eb5385SDavid Zhang */
270183eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal {
270283eb5385SDavid Zhang /**
270383eb5385SDavid Zhang * Command header.
270483eb5385SDavid Zhang */
270583eb5385SDavid Zhang struct dmub_cmd_header header;
270683eb5385SDavid Zhang /**
270783eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
270883eb5385SDavid Zhang */
270983eb5385SDavid Zhang struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
271083eb5385SDavid Zhang };
271183eb5385SDavid Zhang
271283eb5385SDavid Zhang /**
2713e5dfcd27SRobin Chen * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2714e5dfcd27SRobin Chen */
2715e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data {
2716e5dfcd27SRobin Chen /**
2717e5dfcd27SRobin Chen * PSR control version.
2718e5dfcd27SRobin Chen */
2719e5dfcd27SRobin Chen uint8_t cmd_version;
2720e5dfcd27SRobin Chen /**
2721e5dfcd27SRobin Chen * Panel Instance.
272236e88a9eSHusain Alshehhi * Panel instance to identify which psr_state to use
2723e5dfcd27SRobin Chen * Currently the support is only for 0 or 1
2724e5dfcd27SRobin Chen */
2725e5dfcd27SRobin Chen uint8_t panel_inst;
2726e5dfcd27SRobin Chen /**
2727e5dfcd27SRobin Chen * Explicit padding to 4 byte boundary.
2728e5dfcd27SRobin Chen */
2729e5dfcd27SRobin Chen uint8_t pad[2];
2730e5dfcd27SRobin Chen /**
2731e5dfcd27SRobin Chen * PSR power option
2732e5dfcd27SRobin Chen */
2733e5dfcd27SRobin Chen uint32_t power_opt;
2734e5dfcd27SRobin Chen };
2735e5dfcd27SRobin Chen
2736e0138644SBhawanpreet Lakha #define REPLAY_RESIDENCY_MODE_SHIFT (0)
2737e0138644SBhawanpreet Lakha #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
2738e0138644SBhawanpreet Lakha
2739e0138644SBhawanpreet Lakha #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2740e0138644SBhawanpreet Lakha # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
2741e0138644SBhawanpreet Lakha # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2742e0138644SBhawanpreet Lakha
2743e0138644SBhawanpreet Lakha #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2744e0138644SBhawanpreet Lakha # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2745e0138644SBhawanpreet Lakha # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2746e0138644SBhawanpreet Lakha
2747e0138644SBhawanpreet Lakha enum replay_state {
2748e0138644SBhawanpreet Lakha REPLAY_STATE_0 = 0x0,
2749e0138644SBhawanpreet Lakha REPLAY_STATE_1 = 0x10,
2750e0138644SBhawanpreet Lakha REPLAY_STATE_1A = 0x11,
2751e0138644SBhawanpreet Lakha REPLAY_STATE_2 = 0x20,
2752e0138644SBhawanpreet Lakha REPLAY_STATE_3 = 0x30,
2753e0138644SBhawanpreet Lakha REPLAY_STATE_3INIT = 0x31,
2754e0138644SBhawanpreet Lakha REPLAY_STATE_4 = 0x40,
2755e0138644SBhawanpreet Lakha REPLAY_STATE_4A = 0x41,
2756e0138644SBhawanpreet Lakha REPLAY_STATE_4B = 0x42,
2757e0138644SBhawanpreet Lakha REPLAY_STATE_4C = 0x43,
2758e0138644SBhawanpreet Lakha REPLAY_STATE_4D = 0x44,
2759e0138644SBhawanpreet Lakha REPLAY_STATE_4B_LOCKED = 0x4A,
2760e0138644SBhawanpreet Lakha REPLAY_STATE_4C_UNLOCKED = 0x4B,
2761e0138644SBhawanpreet Lakha REPLAY_STATE_5 = 0x50,
2762e0138644SBhawanpreet Lakha REPLAY_STATE_5A = 0x51,
2763e0138644SBhawanpreet Lakha REPLAY_STATE_5B = 0x52,
2764e0138644SBhawanpreet Lakha REPLAY_STATE_5A_LOCKED = 0x5A,
2765e0138644SBhawanpreet Lakha REPLAY_STATE_5B_UNLOCKED = 0x5B,
2766e0138644SBhawanpreet Lakha REPLAY_STATE_6 = 0x60,
2767e0138644SBhawanpreet Lakha REPLAY_STATE_6A = 0x61,
2768e0138644SBhawanpreet Lakha REPLAY_STATE_6B = 0x62,
2769e0138644SBhawanpreet Lakha REPLAY_STATE_INVALID = 0xFF,
2770e0138644SBhawanpreet Lakha };
2771e0138644SBhawanpreet Lakha
2772e0138644SBhawanpreet Lakha /**
2773e0138644SBhawanpreet Lakha * Replay command sub-types.
2774e0138644SBhawanpreet Lakha */
2775e0138644SBhawanpreet Lakha enum dmub_cmd_replay_type {
2776e0138644SBhawanpreet Lakha /**
2777e0138644SBhawanpreet Lakha * Copy driver-calculated parameters to REPLAY state.
2778e0138644SBhawanpreet Lakha */
2779e0138644SBhawanpreet Lakha DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
2780e0138644SBhawanpreet Lakha /**
2781e0138644SBhawanpreet Lakha * Enable REPLAY.
2782e0138644SBhawanpreet Lakha */
2783e0138644SBhawanpreet Lakha DMUB_CMD__REPLAY_ENABLE = 1,
2784e0138644SBhawanpreet Lakha /**
2785e0138644SBhawanpreet Lakha * Set Replay power option.
2786e0138644SBhawanpreet Lakha */
2787e0138644SBhawanpreet Lakha DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
2788e0138644SBhawanpreet Lakha /**
2789e0138644SBhawanpreet Lakha * Set coasting vtotal.
2790e0138644SBhawanpreet Lakha */
2791e0138644SBhawanpreet Lakha DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
2792e0138644SBhawanpreet Lakha };
2793e0138644SBhawanpreet Lakha
2794e0138644SBhawanpreet Lakha /**
2795e0138644SBhawanpreet Lakha * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2796e0138644SBhawanpreet Lakha */
2797e0138644SBhawanpreet Lakha struct dmub_cmd_replay_copy_settings_data {
2798e0138644SBhawanpreet Lakha /**
2799e0138644SBhawanpreet Lakha * Flags that can be set by driver to change some replay behaviour.
2800e0138644SBhawanpreet Lakha */
2801e0138644SBhawanpreet Lakha union replay_debug_flags debug;
2802e0138644SBhawanpreet Lakha
2803e0138644SBhawanpreet Lakha /**
2804e0138644SBhawanpreet Lakha * @flags: Flags used to determine feature functionality.
2805e0138644SBhawanpreet Lakha */
2806e0138644SBhawanpreet Lakha union replay_hw_flags flags;
2807e0138644SBhawanpreet Lakha
2808e0138644SBhawanpreet Lakha /**
2809e0138644SBhawanpreet Lakha * DPP HW instance.
2810e0138644SBhawanpreet Lakha */
2811e0138644SBhawanpreet Lakha uint8_t dpp_inst;
2812e0138644SBhawanpreet Lakha /**
2813e0138644SBhawanpreet Lakha * OTG HW instance.
2814e0138644SBhawanpreet Lakha */
2815e0138644SBhawanpreet Lakha uint8_t otg_inst;
2816e0138644SBhawanpreet Lakha /**
2817e0138644SBhawanpreet Lakha * DIG FE HW instance.
2818e0138644SBhawanpreet Lakha */
2819e0138644SBhawanpreet Lakha uint8_t digfe_inst;
2820e0138644SBhawanpreet Lakha /**
2821e0138644SBhawanpreet Lakha * DIG BE HW instance.
2822e0138644SBhawanpreet Lakha */
2823e0138644SBhawanpreet Lakha uint8_t digbe_inst;
2824e0138644SBhawanpreet Lakha /**
2825e0138644SBhawanpreet Lakha * AUX HW instance.
2826e0138644SBhawanpreet Lakha */
2827e0138644SBhawanpreet Lakha uint8_t aux_inst;
2828e0138644SBhawanpreet Lakha /**
2829e0138644SBhawanpreet Lakha * Panel Instance.
2830e0138644SBhawanpreet Lakha * Panel isntance to identify which psr_state to use
2831e0138644SBhawanpreet Lakha * Currently the support is only for 0 or 1
2832e0138644SBhawanpreet Lakha */
2833e0138644SBhawanpreet Lakha uint8_t panel_inst;
2834e0138644SBhawanpreet Lakha /**
2835e0138644SBhawanpreet Lakha * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
2836e0138644SBhawanpreet Lakha * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
2837e0138644SBhawanpreet Lakha */
2838e0138644SBhawanpreet Lakha uint8_t pixel_deviation_per_line;
2839e0138644SBhawanpreet Lakha /**
2840e0138644SBhawanpreet Lakha * @max_deviation_line: The max number of deviation line that can keep the timing
2841e0138644SBhawanpreet Lakha * synchronized between the Source and Sink during Replay normal sleep mode.
2842e0138644SBhawanpreet Lakha */
2843e0138644SBhawanpreet Lakha uint8_t max_deviation_line;
2844e0138644SBhawanpreet Lakha /**
2845e0138644SBhawanpreet Lakha * Length of each horizontal line in ns.
2846e0138644SBhawanpreet Lakha */
2847e0138644SBhawanpreet Lakha uint32_t line_time_in_ns;
2848e0138644SBhawanpreet Lakha /**
2849e0138644SBhawanpreet Lakha * PHY instance.
2850e0138644SBhawanpreet Lakha */
2851e0138644SBhawanpreet Lakha uint8_t dpphy_inst;
2852e0138644SBhawanpreet Lakha /**
2853e0138644SBhawanpreet Lakha * Determines if SMU optimzations are enabled/disabled.
2854e0138644SBhawanpreet Lakha */
2855e0138644SBhawanpreet Lakha uint8_t smu_optimizations_en;
2856e0138644SBhawanpreet Lakha /**
2857e0138644SBhawanpreet Lakha * Determines if timing sync are enabled/disabled.
2858e0138644SBhawanpreet Lakha */
2859e0138644SBhawanpreet Lakha uint8_t replay_timing_sync_supported;
2860e0138644SBhawanpreet Lakha /*
2861e0138644SBhawanpreet Lakha * Use FSM state for Replay power up/down
2862e0138644SBhawanpreet Lakha */
2863e0138644SBhawanpreet Lakha uint8_t use_phy_fsm;
2864e0138644SBhawanpreet Lakha };
2865e0138644SBhawanpreet Lakha
2866e0138644SBhawanpreet Lakha /**
2867e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2868e0138644SBhawanpreet Lakha */
2869e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_copy_settings {
2870e0138644SBhawanpreet Lakha /**
2871e0138644SBhawanpreet Lakha * Command header.
2872e0138644SBhawanpreet Lakha */
2873e0138644SBhawanpreet Lakha struct dmub_cmd_header header;
2874e0138644SBhawanpreet Lakha /**
2875e0138644SBhawanpreet Lakha * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2876e0138644SBhawanpreet Lakha */
2877e0138644SBhawanpreet Lakha struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
2878e0138644SBhawanpreet Lakha };
2879e0138644SBhawanpreet Lakha
2880e0138644SBhawanpreet Lakha /**
2881e0138644SBhawanpreet Lakha * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
2882e0138644SBhawanpreet Lakha */
2883e0138644SBhawanpreet Lakha enum replay_enable {
2884e0138644SBhawanpreet Lakha /**
2885e0138644SBhawanpreet Lakha * Disable REPLAY.
2886e0138644SBhawanpreet Lakha */
2887e0138644SBhawanpreet Lakha REPLAY_DISABLE = 0,
2888e0138644SBhawanpreet Lakha /**
2889e0138644SBhawanpreet Lakha * Enable REPLAY.
2890e0138644SBhawanpreet Lakha */
2891e0138644SBhawanpreet Lakha REPLAY_ENABLE = 1,
2892e0138644SBhawanpreet Lakha };
2893e0138644SBhawanpreet Lakha
2894e0138644SBhawanpreet Lakha /**
2895e0138644SBhawanpreet Lakha * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
2896e0138644SBhawanpreet Lakha */
2897e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_enable_data {
2898e0138644SBhawanpreet Lakha /**
2899e0138644SBhawanpreet Lakha * Replay enable or disable.
2900e0138644SBhawanpreet Lakha */
2901e0138644SBhawanpreet Lakha uint8_t enable;
2902e0138644SBhawanpreet Lakha /**
2903e0138644SBhawanpreet Lakha * Panel Instance.
2904e0138644SBhawanpreet Lakha * Panel isntance to identify which replay_state to use
2905e0138644SBhawanpreet Lakha * Currently the support is only for 0 or 1
2906e0138644SBhawanpreet Lakha */
2907e0138644SBhawanpreet Lakha uint8_t panel_inst;
2908e0138644SBhawanpreet Lakha /**
2909e0138644SBhawanpreet Lakha * Phy state to enter.
2910e0138644SBhawanpreet Lakha * Values to use are defined in dmub_phy_fsm_state
2911e0138644SBhawanpreet Lakha */
2912e0138644SBhawanpreet Lakha uint8_t phy_fsm_state;
2913e0138644SBhawanpreet Lakha /**
2914e0138644SBhawanpreet Lakha * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2915e0138644SBhawanpreet Lakha * Set this using enum phy_link_rate.
2916e0138644SBhawanpreet Lakha * This does not support HDMI/DP2 for now.
2917e0138644SBhawanpreet Lakha */
2918e0138644SBhawanpreet Lakha uint8_t phy_rate;
2919e0138644SBhawanpreet Lakha };
2920e0138644SBhawanpreet Lakha
2921e0138644SBhawanpreet Lakha /**
2922e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_ENABLE command.
2923e0138644SBhawanpreet Lakha * Replay enable/disable is controlled using action in data.
2924e0138644SBhawanpreet Lakha */
2925e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_enable {
2926e0138644SBhawanpreet Lakha /**
2927e0138644SBhawanpreet Lakha * Command header.
2928e0138644SBhawanpreet Lakha */
2929e0138644SBhawanpreet Lakha struct dmub_cmd_header header;
2930e0138644SBhawanpreet Lakha
2931e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_enable_data data;
2932e0138644SBhawanpreet Lakha };
2933e0138644SBhawanpreet Lakha
2934e0138644SBhawanpreet Lakha /**
2935e0138644SBhawanpreet Lakha * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2936e0138644SBhawanpreet Lakha */
2937e0138644SBhawanpreet Lakha struct dmub_cmd_replay_set_power_opt_data {
2938e0138644SBhawanpreet Lakha /**
2939e0138644SBhawanpreet Lakha * Panel Instance.
2940e0138644SBhawanpreet Lakha * Panel isntance to identify which replay_state to use
2941e0138644SBhawanpreet Lakha * Currently the support is only for 0 or 1
2942e0138644SBhawanpreet Lakha */
2943e0138644SBhawanpreet Lakha uint8_t panel_inst;
2944e0138644SBhawanpreet Lakha /**
2945e0138644SBhawanpreet Lakha * Explicit padding to 4 byte boundary.
2946e0138644SBhawanpreet Lakha */
2947e0138644SBhawanpreet Lakha uint8_t pad[3];
2948e0138644SBhawanpreet Lakha /**
2949e0138644SBhawanpreet Lakha * REPLAY power option
2950e0138644SBhawanpreet Lakha */
2951e0138644SBhawanpreet Lakha uint32_t power_opt;
2952e0138644SBhawanpreet Lakha };
2953e0138644SBhawanpreet Lakha
2954e0138644SBhawanpreet Lakha /**
2955e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2956e0138644SBhawanpreet Lakha */
2957e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_set_power_opt {
2958e0138644SBhawanpreet Lakha /**
2959e0138644SBhawanpreet Lakha * Command header.
2960e0138644SBhawanpreet Lakha */
2961e0138644SBhawanpreet Lakha struct dmub_cmd_header header;
2962e0138644SBhawanpreet Lakha /**
2963e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2964e0138644SBhawanpreet Lakha */
2965e0138644SBhawanpreet Lakha struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
2966e0138644SBhawanpreet Lakha };
2967e0138644SBhawanpreet Lakha
2968e0138644SBhawanpreet Lakha /**
2969e0138644SBhawanpreet Lakha * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2970e0138644SBhawanpreet Lakha */
2971e0138644SBhawanpreet Lakha struct dmub_cmd_replay_set_coasting_vtotal_data {
2972e0138644SBhawanpreet Lakha /**
2973e0138644SBhawanpreet Lakha * 16-bit value dicated by driver that indicates the coasting vtotal.
2974e0138644SBhawanpreet Lakha */
2975e0138644SBhawanpreet Lakha uint16_t coasting_vtotal;
2976e0138644SBhawanpreet Lakha /**
2977e0138644SBhawanpreet Lakha * REPLAY control version.
2978e0138644SBhawanpreet Lakha */
2979e0138644SBhawanpreet Lakha uint8_t cmd_version;
2980e0138644SBhawanpreet Lakha /**
2981e0138644SBhawanpreet Lakha * Panel Instance.
2982e0138644SBhawanpreet Lakha * Panel isntance to identify which replay_state to use
2983e0138644SBhawanpreet Lakha * Currently the support is only for 0 or 1
2984e0138644SBhawanpreet Lakha */
2985e0138644SBhawanpreet Lakha uint8_t panel_inst;
2986e0138644SBhawanpreet Lakha };
2987e0138644SBhawanpreet Lakha
2988e0138644SBhawanpreet Lakha /**
2989e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2990e0138644SBhawanpreet Lakha */
2991e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_set_coasting_vtotal {
2992e0138644SBhawanpreet Lakha /**
2993e0138644SBhawanpreet Lakha * Command header.
2994e0138644SBhawanpreet Lakha */
2995e0138644SBhawanpreet Lakha struct dmub_cmd_header header;
2996e0138644SBhawanpreet Lakha /**
2997e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2998e0138644SBhawanpreet Lakha */
2999e0138644SBhawanpreet Lakha struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3000e0138644SBhawanpreet Lakha };
3001e0138644SBhawanpreet Lakha
3002e5dfcd27SRobin Chen /**
3003e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3004e5dfcd27SRobin Chen */
3005e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt {
3006e5dfcd27SRobin Chen /**
3007e5dfcd27SRobin Chen * Command header.
3008e5dfcd27SRobin Chen */
3009e5dfcd27SRobin Chen struct dmub_cmd_header header;
3010e5dfcd27SRobin Chen /**
3011e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3012e5dfcd27SRobin Chen */
3013e5dfcd27SRobin Chen struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3014e5dfcd27SRobin Chen };
3015e5dfcd27SRobin Chen
3016e5dfcd27SRobin Chen /**
30171a595f28SAnthony Koo * Set of HW components that can be locked.
30180b51e7e8SAnthony Koo *
30190b51e7e8SAnthony Koo * Note: If updating with more HW components, fields
30200b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match.
30211a595f28SAnthony Koo */
3022788408b7SAnthony Koo union dmub_hw_lock_flags {
30231a595f28SAnthony Koo /**
30241a595f28SAnthony Koo * Set of HW components that can be locked.
30251a595f28SAnthony Koo */
3026788408b7SAnthony Koo struct {
30271a595f28SAnthony Koo /**
30281a595f28SAnthony Koo * Lock/unlock OTG master update lock.
30291a595f28SAnthony Koo */
3030788408b7SAnthony Koo uint8_t lock_pipe : 1;
30311a595f28SAnthony Koo /**
30321a595f28SAnthony Koo * Lock/unlock cursor.
30331a595f28SAnthony Koo */
3034788408b7SAnthony Koo uint8_t lock_cursor : 1;
30351a595f28SAnthony Koo /**
30361a595f28SAnthony Koo * Lock/unlock global update lock.
30371a595f28SAnthony Koo */
3038788408b7SAnthony Koo uint8_t lock_dig : 1;
30391a595f28SAnthony Koo /**
30401a595f28SAnthony Koo * Triple buffer lock requires additional hw programming to usual OTG master lock.
30411a595f28SAnthony Koo */
3042788408b7SAnthony Koo uint8_t triple_buffer_lock : 1;
3043788408b7SAnthony Koo } bits;
3044788408b7SAnthony Koo
30451a595f28SAnthony Koo /**
30461a595f28SAnthony Koo * Union for HW Lock flags.
30471a595f28SAnthony Koo */
3048788408b7SAnthony Koo uint8_t u8All;
3049788408b7SAnthony Koo };
3050788408b7SAnthony Koo
30511a595f28SAnthony Koo /**
30521a595f28SAnthony Koo * Instances of HW to be locked.
30530b51e7e8SAnthony Koo *
30540b51e7e8SAnthony Koo * Note: If updating with more HW components, fields
30550b51e7e8SAnthony Koo * in dmub_inbox0_cmd_lock_hw must be updated to match.
30561a595f28SAnthony Koo */
3057788408b7SAnthony Koo struct dmub_hw_lock_inst_flags {
30581a595f28SAnthony Koo /**
30591a595f28SAnthony Koo * OTG HW instance for OTG master update lock.
30601a595f28SAnthony Koo */
3061788408b7SAnthony Koo uint8_t otg_inst;
30621a595f28SAnthony Koo /**
30631a595f28SAnthony Koo * OPP instance for cursor lock.
30641a595f28SAnthony Koo */
3065788408b7SAnthony Koo uint8_t opp_inst;
30661a595f28SAnthony Koo /**
30671a595f28SAnthony Koo * OTG HW instance for global update lock.
30681a595f28SAnthony Koo * TODO: Remove, and re-use otg_inst.
30691a595f28SAnthony Koo */
3070788408b7SAnthony Koo uint8_t dig_inst;
30711a595f28SAnthony Koo /**
30721a595f28SAnthony Koo * Explicit pad to 4 byte boundary.
30731a595f28SAnthony Koo */
3074788408b7SAnthony Koo uint8_t pad;
3075788408b7SAnthony Koo };
3076788408b7SAnthony Koo
30771a595f28SAnthony Koo /**
30781a595f28SAnthony Koo * Clients that can acquire the HW Lock Manager.
30790b51e7e8SAnthony Koo *
30800b51e7e8SAnthony Koo * Note: If updating with more clients, fields in
30810b51e7e8SAnthony Koo * dmub_inbox0_cmd_lock_hw must be updated to match.
30821a595f28SAnthony Koo */
3083788408b7SAnthony Koo enum hw_lock_client {
30841a595f28SAnthony Koo /**
30851a595f28SAnthony Koo * Driver is the client of HW Lock Manager.
30861a595f28SAnthony Koo */
3087788408b7SAnthony Koo HW_LOCK_CLIENT_DRIVER = 0,
30881a595f28SAnthony Koo /**
308983eb5385SDavid Zhang * PSR SU is the client of HW Lock Manager.
309083eb5385SDavid Zhang */
309183eb5385SDavid Zhang HW_LOCK_CLIENT_PSR_SU = 1,
309283eb5385SDavid Zhang /**
3093e0138644SBhawanpreet Lakha * Replay is the client of HW Lock Manager.
3094e0138644SBhawanpreet Lakha */
3095e0138644SBhawanpreet Lakha HW_LOCK_CLIENT_REPLAY = 4,
3096e0138644SBhawanpreet Lakha /**
30971a595f28SAnthony Koo * Invalid client.
30981a595f28SAnthony Koo */
3099788408b7SAnthony Koo HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3100788408b7SAnthony Koo };
3101788408b7SAnthony Koo
31021a595f28SAnthony Koo /**
31031a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
31041a595f28SAnthony Koo */
3105788408b7SAnthony Koo struct dmub_cmd_lock_hw_data {
31061a595f28SAnthony Koo /**
31071a595f28SAnthony Koo * Specifies the client accessing HW Lock Manager.
31081a595f28SAnthony Koo */
3109788408b7SAnthony Koo enum hw_lock_client client;
31101a595f28SAnthony Koo /**
31111a595f28SAnthony Koo * HW instances to be locked.
31121a595f28SAnthony Koo */
3113788408b7SAnthony Koo struct dmub_hw_lock_inst_flags inst_flags;
31141a595f28SAnthony Koo /**
31151a595f28SAnthony Koo * Which components to be locked.
31161a595f28SAnthony Koo */
3117788408b7SAnthony Koo union dmub_hw_lock_flags hw_locks;
31181a595f28SAnthony Koo /**
31191a595f28SAnthony Koo * Specifies lock/unlock.
31201a595f28SAnthony Koo */
3121788408b7SAnthony Koo uint8_t lock;
31221a595f28SAnthony Koo /**
31231a595f28SAnthony Koo * HW can be unlocked separately from releasing the HW Lock Mgr.
31241a595f28SAnthony Koo * This flag is set if the client wishes to release the object.
31251a595f28SAnthony Koo */
3126788408b7SAnthony Koo uint8_t should_release;
31271a595f28SAnthony Koo /**
31281a595f28SAnthony Koo * Explicit padding to 4 byte boundary.
31291a595f28SAnthony Koo */
3130788408b7SAnthony Koo uint8_t pad;
3131788408b7SAnthony Koo };
3132788408b7SAnthony Koo
31331a595f28SAnthony Koo /**
31341a595f28SAnthony Koo * Definition of a DMUB_CMD__HW_LOCK command.
31351a595f28SAnthony Koo * Command is used by driver and FW.
31361a595f28SAnthony Koo */
3137788408b7SAnthony Koo struct dmub_rb_cmd_lock_hw {
31381a595f28SAnthony Koo /**
31391a595f28SAnthony Koo * Command header.
31401a595f28SAnthony Koo */
3141788408b7SAnthony Koo struct dmub_cmd_header header;
31421a595f28SAnthony Koo /**
31431a595f28SAnthony Koo * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
31441a595f28SAnthony Koo */
3145788408b7SAnthony Koo struct dmub_cmd_lock_hw_data lock_hw_data;
3146788408b7SAnthony Koo };
3147788408b7SAnthony Koo
31481a595f28SAnthony Koo /**
31491a595f28SAnthony Koo * ABM command sub-types.
31501a595f28SAnthony Koo */
315184034ad4SAnthony Koo enum dmub_cmd_abm_type {
31521a595f28SAnthony Koo /**
31531a595f28SAnthony Koo * Initialize parameters for ABM algorithm.
31541a595f28SAnthony Koo * Data is passed through an indirect buffer.
31551a595f28SAnthony Koo */
315684034ad4SAnthony Koo DMUB_CMD__ABM_INIT_CONFIG = 0,
31571a595f28SAnthony Koo /**
31581a595f28SAnthony Koo * Set OTG and panel HW instance.
31591a595f28SAnthony Koo */
316084034ad4SAnthony Koo DMUB_CMD__ABM_SET_PIPE = 1,
31611a595f28SAnthony Koo /**
31621a595f28SAnthony Koo * Set user requested backklight level.
31631a595f28SAnthony Koo */
316484034ad4SAnthony Koo DMUB_CMD__ABM_SET_BACKLIGHT = 2,
31651a595f28SAnthony Koo /**
31661a595f28SAnthony Koo * Set ABM operating/aggression level.
31671a595f28SAnthony Koo */
316884034ad4SAnthony Koo DMUB_CMD__ABM_SET_LEVEL = 3,
31691a595f28SAnthony Koo /**
31701a595f28SAnthony Koo * Set ambient light level.
31711a595f28SAnthony Koo */
317284034ad4SAnthony Koo DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
31731a595f28SAnthony Koo /**
31741a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM.
31751a595f28SAnthony Koo */
317684034ad4SAnthony Koo DMUB_CMD__ABM_SET_PWM_FRAC = 5,
3177b629a824SEric Yang
3178b629a824SEric Yang /**
3179b629a824SEric Yang * unregister vertical interrupt after steady state is reached
3180b629a824SEric Yang */
3181b629a824SEric Yang DMUB_CMD__ABM_PAUSE = 6,
3182da915efaSReza Amini
3183da915efaSReza Amini /**
3184519e3637SReza Amini * Save and Restore ABM state. On save we save parameters, and
3185da915efaSReza Amini * on restore we update state with passed in data.
3186da915efaSReza Amini */
3187da915efaSReza Amini DMUB_CMD__ABM_SAVE_RESTORE = 7,
318884034ad4SAnthony Koo };
318984034ad4SAnthony Koo
31901a595f28SAnthony Koo /**
31911a595f28SAnthony Koo * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
31921a595f28SAnthony Koo * Requirements:
31931a595f28SAnthony Koo * - Padded explicitly to 32-bit boundary.
31941a595f28SAnthony Koo * - Must ensure this structure matches the one on driver-side,
31951a595f28SAnthony Koo * otherwise it won't be aligned.
319684034ad4SAnthony Koo */
319784034ad4SAnthony Koo struct abm_config_table {
31981a595f28SAnthony Koo /**
31991a595f28SAnthony Koo * Gamma curve thresholds, used for crgb conversion.
32001a595f28SAnthony Koo */
320184034ad4SAnthony Koo uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
32021a595f28SAnthony Koo /**
32031a595f28SAnthony Koo * Gamma curve offsets, used for crgb conversion.
32041a595f28SAnthony Koo */
3205b6402afeSAnthony Koo uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
32061a595f28SAnthony Koo /**
32071a595f28SAnthony Koo * Gamma curve slopes, used for crgb conversion.
32081a595f28SAnthony Koo */
3209b6402afeSAnthony Koo uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
32101a595f28SAnthony Koo /**
32111a595f28SAnthony Koo * Custom backlight curve thresholds.
32121a595f28SAnthony Koo */
3213b6402afeSAnthony Koo uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
32141a595f28SAnthony Koo /**
32151a595f28SAnthony Koo * Custom backlight curve offsets.
32161a595f28SAnthony Koo */
3217b6402afeSAnthony Koo uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
32181a595f28SAnthony Koo /**
32191a595f28SAnthony Koo * Ambient light thresholds.
32201a595f28SAnthony Koo */
3221b6402afeSAnthony Koo uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
32221a595f28SAnthony Koo /**
32231a595f28SAnthony Koo * Minimum programmable backlight.
32241a595f28SAnthony Koo */
3225b6402afeSAnthony Koo uint16_t min_abm_backlight; // 122B
32261a595f28SAnthony Koo /**
32271a595f28SAnthony Koo * Minimum reduction values.
32281a595f28SAnthony Koo */
3229b6402afeSAnthony Koo uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
32301a595f28SAnthony Koo /**
32311a595f28SAnthony Koo * Maximum reduction values.
32321a595f28SAnthony Koo */
3233b6402afeSAnthony Koo uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
32341a595f28SAnthony Koo /**
32351a595f28SAnthony Koo * Bright positive gain.
32361a595f28SAnthony Koo */
3237b6402afeSAnthony Koo uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
32381a595f28SAnthony Koo /**
32391a595f28SAnthony Koo * Dark negative gain.
32401a595f28SAnthony Koo */
3241b6402afeSAnthony Koo uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
32421a595f28SAnthony Koo /**
32431a595f28SAnthony Koo * Hybrid factor.
32441a595f28SAnthony Koo */
3245b6402afeSAnthony Koo uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
32461a595f28SAnthony Koo /**
32471a595f28SAnthony Koo * Contrast factor.
32481a595f28SAnthony Koo */
3249b6402afeSAnthony Koo uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
32501a595f28SAnthony Koo /**
32511a595f28SAnthony Koo * Deviation gain.
32521a595f28SAnthony Koo */
3253b6402afeSAnthony Koo uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
32541a595f28SAnthony Koo /**
32551a595f28SAnthony Koo * Minimum knee.
32561a595f28SAnthony Koo */
3257b6402afeSAnthony Koo uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
32581a595f28SAnthony Koo /**
32591a595f28SAnthony Koo * Maximum knee.
32601a595f28SAnthony Koo */
3261b6402afeSAnthony Koo uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
32621a595f28SAnthony Koo /**
32631a595f28SAnthony Koo * Unused.
32641a595f28SAnthony Koo */
3265b6402afeSAnthony Koo uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
32661a595f28SAnthony Koo /**
32671a595f28SAnthony Koo * Explicit padding to 4 byte boundary.
32681a595f28SAnthony Koo */
3269b6402afeSAnthony Koo uint8_t pad3[3]; // 229B
32701a595f28SAnthony Koo /**
32711a595f28SAnthony Koo * Backlight ramp reduction.
32721a595f28SAnthony Koo */
3273b6402afeSAnthony Koo uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
32741a595f28SAnthony Koo /**
32751a595f28SAnthony Koo * Backlight ramp start.
32761a595f28SAnthony Koo */
3277b6402afeSAnthony Koo uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
327884034ad4SAnthony Koo };
327984034ad4SAnthony Koo
32801a595f28SAnthony Koo /**
32811a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
32821a595f28SAnthony Koo */
3283e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data {
32841a595f28SAnthony Koo /**
32851a595f28SAnthony Koo * OTG HW instance.
32861a595f28SAnthony Koo */
32877b8a6362SAnthony Koo uint8_t otg_inst;
32881a595f28SAnthony Koo
32891a595f28SAnthony Koo /**
32901a595f28SAnthony Koo * Panel Control HW instance.
32911a595f28SAnthony Koo */
32927b8a6362SAnthony Koo uint8_t panel_inst;
32931a595f28SAnthony Koo
32941a595f28SAnthony Koo /**
32951a595f28SAnthony Koo * Controls how ABM will interpret a set pipe or set level command.
32961a595f28SAnthony Koo */
32977b8a6362SAnthony Koo uint8_t set_pipe_option;
32981a595f28SAnthony Koo
32991a595f28SAnthony Koo /**
33001a595f28SAnthony Koo * Unused.
33011a595f28SAnthony Koo * TODO: Remove.
33021a595f28SAnthony Koo */
33031a595f28SAnthony Koo uint8_t ramping_boundary;
3304*71be0f67SLewis Huang
3305*71be0f67SLewis Huang /**
3306*71be0f67SLewis Huang * PwrSeq HW Instance.
3307*71be0f67SLewis Huang */
3308*71be0f67SLewis Huang uint8_t pwrseq_inst;
3309*71be0f67SLewis Huang
3310*71be0f67SLewis Huang /**
3311*71be0f67SLewis Huang * Explicit padding to 4 byte boundary.
3312*71be0f67SLewis Huang */
3313*71be0f67SLewis Huang uint8_t pad[3];
3314e6ea8c34SWyatt Wood };
3315e6ea8c34SWyatt Wood
33161a595f28SAnthony Koo /**
33171a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command.
33181a595f28SAnthony Koo */
3319e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe {
33201a595f28SAnthony Koo /**
33211a595f28SAnthony Koo * Command header.
33221a595f28SAnthony Koo */
3323e6ea8c34SWyatt Wood struct dmub_cmd_header header;
33241a595f28SAnthony Koo
33251a595f28SAnthony Koo /**
33261a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
33271a595f28SAnthony Koo */
3328e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
3329e6ea8c34SWyatt Wood };
3330e6ea8c34SWyatt Wood
33311a595f28SAnthony Koo /**
33321a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
33331a595f28SAnthony Koo */
3334e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data {
33351a595f28SAnthony Koo /**
33361a595f28SAnthony Koo * Number of frames to ramp to backlight user level.
33371a595f28SAnthony Koo */
3338e6ea8c34SWyatt Wood uint32_t frame_ramp;
33391a595f28SAnthony Koo
33401a595f28SAnthony Koo /**
33411a595f28SAnthony Koo * Requested backlight level from user.
33421a595f28SAnthony Koo */
3343474ac4a8SYongqiang Sun uint32_t backlight_user_level;
3344e922057bSJake Wang
3345e922057bSJake Wang /**
334663de4f04SJake Wang * ABM control version.
3347e922057bSJake Wang */
3348e922057bSJake Wang uint8_t version;
3349e922057bSJake Wang
3350e922057bSJake Wang /**
3351e922057bSJake Wang * Panel Control HW instance mask.
3352e922057bSJake Wang * Bit 0 is Panel Control HW instance 0.
3353e922057bSJake Wang * Bit 1 is Panel Control HW instance 1.
3354e922057bSJake Wang */
3355e922057bSJake Wang uint8_t panel_mask;
3356e922057bSJake Wang
3357e922057bSJake Wang /**
3358e922057bSJake Wang * Explicit padding to 4 byte boundary.
3359e922057bSJake Wang */
3360e922057bSJake Wang uint8_t pad[2];
3361e6ea8c34SWyatt Wood };
3362e6ea8c34SWyatt Wood
33631a595f28SAnthony Koo /**
33641a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
33651a595f28SAnthony Koo */
3366e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight {
33671a595f28SAnthony Koo /**
33681a595f28SAnthony Koo * Command header.
33691a595f28SAnthony Koo */
3370e6ea8c34SWyatt Wood struct dmub_cmd_header header;
33711a595f28SAnthony Koo
33721a595f28SAnthony Koo /**
33731a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
33741a595f28SAnthony Koo */
3375e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
3376e6ea8c34SWyatt Wood };
3377e6ea8c34SWyatt Wood
33781a595f28SAnthony Koo /**
33791a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
33801a595f28SAnthony Koo */
3381e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data {
33821a595f28SAnthony Koo /**
33831a595f28SAnthony Koo * Set current ABM operating/aggression level.
33841a595f28SAnthony Koo */
3385e6ea8c34SWyatt Wood uint32_t level;
338663de4f04SJake Wang
338763de4f04SJake Wang /**
338863de4f04SJake Wang * ABM control version.
338963de4f04SJake Wang */
339063de4f04SJake Wang uint8_t version;
339163de4f04SJake Wang
339263de4f04SJake Wang /**
339363de4f04SJake Wang * Panel Control HW instance mask.
339463de4f04SJake Wang * Bit 0 is Panel Control HW instance 0.
339563de4f04SJake Wang * Bit 1 is Panel Control HW instance 1.
339663de4f04SJake Wang */
339763de4f04SJake Wang uint8_t panel_mask;
339863de4f04SJake Wang
339963de4f04SJake Wang /**
340063de4f04SJake Wang * Explicit padding to 4 byte boundary.
340163de4f04SJake Wang */
340263de4f04SJake Wang uint8_t pad[2];
3403e6ea8c34SWyatt Wood };
3404e6ea8c34SWyatt Wood
34051a595f28SAnthony Koo /**
34061a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
34071a595f28SAnthony Koo */
3408e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level {
34091a595f28SAnthony Koo /**
34101a595f28SAnthony Koo * Command header.
34111a595f28SAnthony Koo */
3412e6ea8c34SWyatt Wood struct dmub_cmd_header header;
34131a595f28SAnthony Koo
34141a595f28SAnthony Koo /**
34151a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
34161a595f28SAnthony Koo */
3417e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_level_data abm_set_level_data;
3418e6ea8c34SWyatt Wood };
3419e6ea8c34SWyatt Wood
34201a595f28SAnthony Koo /**
34211a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
34221a595f28SAnthony Koo */
3423e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data {
34241a595f28SAnthony Koo /**
34251a595f28SAnthony Koo * Ambient light sensor reading from OS.
34261a595f28SAnthony Koo */
3427e6ea8c34SWyatt Wood uint32_t ambient_lux;
342863de4f04SJake Wang
342963de4f04SJake Wang /**
343063de4f04SJake Wang * ABM control version.
343163de4f04SJake Wang */
343263de4f04SJake Wang uint8_t version;
343363de4f04SJake Wang
343463de4f04SJake Wang /**
343563de4f04SJake Wang * Panel Control HW instance mask.
343663de4f04SJake Wang * Bit 0 is Panel Control HW instance 0.
343763de4f04SJake Wang * Bit 1 is Panel Control HW instance 1.
343863de4f04SJake Wang */
343963de4f04SJake Wang uint8_t panel_mask;
344063de4f04SJake Wang
344163de4f04SJake Wang /**
344263de4f04SJake Wang * Explicit padding to 4 byte boundary.
344363de4f04SJake Wang */
344463de4f04SJake Wang uint8_t pad[2];
3445e6ea8c34SWyatt Wood };
3446e6ea8c34SWyatt Wood
34471a595f28SAnthony Koo /**
34481a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
34491a595f28SAnthony Koo */
3450e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level {
34511a595f28SAnthony Koo /**
34521a595f28SAnthony Koo * Command header.
34531a595f28SAnthony Koo */
3454e6ea8c34SWyatt Wood struct dmub_cmd_header header;
34551a595f28SAnthony Koo
34561a595f28SAnthony Koo /**
34571a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
34581a595f28SAnthony Koo */
3459e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
3460e6ea8c34SWyatt Wood };
3461e6ea8c34SWyatt Wood
34621a595f28SAnthony Koo /**
34631a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
34641a595f28SAnthony Koo */
3465e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data {
34661a595f28SAnthony Koo /**
34671a595f28SAnthony Koo * Enable/disable fractional duty cycle for backlight PWM.
34681a595f28SAnthony Koo * TODO: Convert to uint8_t.
34691a595f28SAnthony Koo */
3470e6ea8c34SWyatt Wood uint32_t fractional_pwm;
347163de4f04SJake Wang
347263de4f04SJake Wang /**
347363de4f04SJake Wang * ABM control version.
347463de4f04SJake Wang */
347563de4f04SJake Wang uint8_t version;
347663de4f04SJake Wang
347763de4f04SJake Wang /**
347863de4f04SJake Wang * Panel Control HW instance mask.
347963de4f04SJake Wang * Bit 0 is Panel Control HW instance 0.
348063de4f04SJake Wang * Bit 1 is Panel Control HW instance 1.
348163de4f04SJake Wang */
348263de4f04SJake Wang uint8_t panel_mask;
348363de4f04SJake Wang
348463de4f04SJake Wang /**
348563de4f04SJake Wang * Explicit padding to 4 byte boundary.
348663de4f04SJake Wang */
348763de4f04SJake Wang uint8_t pad[2];
3488e6ea8c34SWyatt Wood };
3489e6ea8c34SWyatt Wood
34901a595f28SAnthony Koo /**
34911a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
34921a595f28SAnthony Koo */
3493e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac {
34941a595f28SAnthony Koo /**
34951a595f28SAnthony Koo * Command header.
34961a595f28SAnthony Koo */
3497e6ea8c34SWyatt Wood struct dmub_cmd_header header;
34981a595f28SAnthony Koo
34991a595f28SAnthony Koo /**
35001a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
35011a595f28SAnthony Koo */
3502e6ea8c34SWyatt Wood struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
3503e6ea8c34SWyatt Wood };
3504e6ea8c34SWyatt Wood
35051a595f28SAnthony Koo /**
35061a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
35071a595f28SAnthony Koo */
350816012806SWyatt Wood struct dmub_cmd_abm_init_config_data {
35091a595f28SAnthony Koo /**
35101a595f28SAnthony Koo * Location of indirect buffer used to pass init data to ABM.
35111a595f28SAnthony Koo */
351216012806SWyatt Wood union dmub_addr src;
35131a595f28SAnthony Koo
35141a595f28SAnthony Koo /**
35151a595f28SAnthony Koo * Indirect buffer length.
35161a595f28SAnthony Koo */
351716012806SWyatt Wood uint16_t bytes;
351863de4f04SJake Wang
351963de4f04SJake Wang
352063de4f04SJake Wang /**
352163de4f04SJake Wang * ABM control version.
352263de4f04SJake Wang */
352363de4f04SJake Wang uint8_t version;
352463de4f04SJake Wang
352563de4f04SJake Wang /**
352663de4f04SJake Wang * Panel Control HW instance mask.
352763de4f04SJake Wang * Bit 0 is Panel Control HW instance 0.
352863de4f04SJake Wang * Bit 1 is Panel Control HW instance 1.
352963de4f04SJake Wang */
353063de4f04SJake Wang uint8_t panel_mask;
353163de4f04SJake Wang
353263de4f04SJake Wang /**
353363de4f04SJake Wang * Explicit padding to 4 byte boundary.
353463de4f04SJake Wang */
353563de4f04SJake Wang uint8_t pad[2];
353616012806SWyatt Wood };
353716012806SWyatt Wood
35381a595f28SAnthony Koo /**
35391a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
35401a595f28SAnthony Koo */
354116012806SWyatt Wood struct dmub_rb_cmd_abm_init_config {
35421a595f28SAnthony Koo /**
35431a595f28SAnthony Koo * Command header.
35441a595f28SAnthony Koo */
354516012806SWyatt Wood struct dmub_cmd_header header;
35461a595f28SAnthony Koo
35471a595f28SAnthony Koo /**
35481a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
35491a595f28SAnthony Koo */
355016012806SWyatt Wood struct dmub_cmd_abm_init_config_data abm_init_config_data;
355116012806SWyatt Wood };
355216012806SWyatt Wood
35531a595f28SAnthony Koo /**
3554b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3555b629a824SEric Yang */
3556b629a824SEric Yang
3557b629a824SEric Yang struct dmub_cmd_abm_pause_data {
3558b629a824SEric Yang
3559b629a824SEric Yang /**
3560b629a824SEric Yang * Panel Control HW instance mask.
3561b629a824SEric Yang * Bit 0 is Panel Control HW instance 0.
3562b629a824SEric Yang * Bit 1 is Panel Control HW instance 1.
3563b629a824SEric Yang */
3564b629a824SEric Yang uint8_t panel_mask;
3565b629a824SEric Yang
3566b629a824SEric Yang /**
3567b629a824SEric Yang * OTG hw instance
3568b629a824SEric Yang */
3569b629a824SEric Yang uint8_t otg_inst;
3570b629a824SEric Yang
3571b629a824SEric Yang /**
3572b629a824SEric Yang * Enable or disable ABM pause
3573b629a824SEric Yang */
3574b629a824SEric Yang uint8_t enable;
3575b629a824SEric Yang
3576b629a824SEric Yang /**
3577b629a824SEric Yang * Explicit padding to 4 byte boundary.
3578b629a824SEric Yang */
3579b629a824SEric Yang uint8_t pad[1];
3580b629a824SEric Yang };
3581b629a824SEric Yang
3582519e3637SReza Amini
3583b629a824SEric Yang /**
3584b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command.
3585b629a824SEric Yang */
3586b629a824SEric Yang struct dmub_rb_cmd_abm_pause {
3587b629a824SEric Yang /**
3588b629a824SEric Yang * Command header.
3589b629a824SEric Yang */
3590b629a824SEric Yang struct dmub_cmd_header header;
3591b629a824SEric Yang
3592b629a824SEric Yang /**
3593b629a824SEric Yang * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3594b629a824SEric Yang */
3595b629a824SEric Yang struct dmub_cmd_abm_pause_data abm_pause_data;
3596b629a824SEric Yang };
3597b629a824SEric Yang
3598b629a824SEric Yang /**
3599da915efaSReza Amini * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
3600da915efaSReza Amini */
3601da915efaSReza Amini struct dmub_rb_cmd_abm_save_restore {
3602da915efaSReza Amini /**
3603da915efaSReza Amini * Command header.
3604da915efaSReza Amini */
3605da915efaSReza Amini struct dmub_cmd_header header;
3606da915efaSReza Amini
3607da915efaSReza Amini /**
3608da915efaSReza Amini * OTG hw instance
3609da915efaSReza Amini */
3610da915efaSReza Amini uint8_t otg_inst;
3611da915efaSReza Amini
3612da915efaSReza Amini /**
3613da915efaSReza Amini * Enable or disable ABM pause
3614da915efaSReza Amini */
3615da915efaSReza Amini uint8_t freeze;
3616da915efaSReza Amini
3617da915efaSReza Amini /**
3618da915efaSReza Amini * Explicit padding to 4 byte boundary.
3619da915efaSReza Amini */
3620da915efaSReza Amini uint8_t debug;
3621da915efaSReza Amini
3622da915efaSReza Amini /**
3623da915efaSReza Amini * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3624da915efaSReza Amini */
3625da915efaSReza Amini struct dmub_cmd_abm_init_config_data abm_init_config_data;
3626da915efaSReza Amini };
3627da915efaSReza Amini
3628da915efaSReza Amini /**
36291a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
36301a595f28SAnthony Koo */
363134ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data {
36321a595f28SAnthony Koo /**
36331a595f28SAnthony Koo * DMUB feature capabilities.
36341a595f28SAnthony Koo * After DMUB init, driver will query FW capabilities prior to enabling certain features.
36351a595f28SAnthony Koo */
363634ba432cSAnthony Koo struct dmub_feature_caps feature_caps;
363734ba432cSAnthony Koo };
363834ba432cSAnthony Koo
36391a595f28SAnthony Koo /**
36401a595f28SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
36411a595f28SAnthony Koo */
364234ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps {
36431a595f28SAnthony Koo /**
36441a595f28SAnthony Koo * Command header.
36451a595f28SAnthony Koo */
364634ba432cSAnthony Koo struct dmub_cmd_header header;
36471a595f28SAnthony Koo /**
36481a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
36491a595f28SAnthony Koo */
365034ba432cSAnthony Koo struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
365134ba432cSAnthony Koo };
365234ba432cSAnthony Koo
3653b09c1fffSLeo (Hanghong) Ma /**
3654b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3655b09c1fffSLeo (Hanghong) Ma */
3656b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data {
3657b09c1fffSLeo (Hanghong) Ma /**
3658b09c1fffSLeo (Hanghong) Ma * DMUB feature capabilities.
3659b09c1fffSLeo (Hanghong) Ma * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3660b09c1fffSLeo (Hanghong) Ma */
3661b09c1fffSLeo (Hanghong) Ma struct dmub_visual_confirm_color visual_confirm_color;
3662b09c1fffSLeo (Hanghong) Ma };
3663b09c1fffSLeo (Hanghong) Ma
3664b09c1fffSLeo (Hanghong) Ma /**
3665b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3666b09c1fffSLeo (Hanghong) Ma */
3667b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color {
3668b09c1fffSLeo (Hanghong) Ma /**
3669b09c1fffSLeo (Hanghong) Ma * Command header.
3670b09c1fffSLeo (Hanghong) Ma */
3671b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_header header;
3672b09c1fffSLeo (Hanghong) Ma /**
3673b09c1fffSLeo (Hanghong) Ma * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3674b09c1fffSLeo (Hanghong) Ma */
3675b09c1fffSLeo (Hanghong) Ma struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
3676b09c1fffSLeo (Hanghong) Ma };
3677b09c1fffSLeo (Hanghong) Ma
3678592a6318SAnthony Koo struct dmub_optc_state {
3679592a6318SAnthony Koo uint32_t v_total_max;
3680592a6318SAnthony Koo uint32_t v_total_min;
3681592a6318SAnthony Koo uint32_t tg_inst;
3682592a6318SAnthony Koo };
3683592a6318SAnthony Koo
3684592a6318SAnthony Koo struct dmub_rb_cmd_drr_update {
3685592a6318SAnthony Koo struct dmub_cmd_header header;
3686592a6318SAnthony Koo struct dmub_optc_state dmub_optc_state_req;
3687592a6318SAnthony Koo };
3688592a6318SAnthony Koo
368900fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
369000fa7f03SRodrigo Siqueira uint32_t pix_clk_100hz;
369100fa7f03SRodrigo Siqueira uint8_t max_ramp_step;
369200fa7f03SRodrigo Siqueira uint8_t pipes;
369300fa7f03SRodrigo Siqueira uint8_t min_refresh_in_hz;
3694d3981ee7SAnthony Koo uint8_t pipe_count;
3695d3981ee7SAnthony Koo uint8_t pipe_index[4];
369600fa7f03SRodrigo Siqueira };
369700fa7f03SRodrigo Siqueira
369800fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config {
369900fa7f03SRodrigo Siqueira uint8_t fams_enabled;
370000fa7f03SRodrigo Siqueira uint8_t visual_confirm_enabled;
3701d3981ee7SAnthony Koo uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
3702d3981ee7SAnthony Koo struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
370300fa7f03SRodrigo Siqueira };
370400fa7f03SRodrigo Siqueira
370500fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch {
370600fa7f03SRodrigo Siqueira struct dmub_cmd_header header;
370700fa7f03SRodrigo Siqueira struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
370800fa7f03SRodrigo Siqueira };
370900fa7f03SRodrigo Siqueira
3710b04cb192SNicholas Kazlauskas /**
3711b04cb192SNicholas Kazlauskas * enum dmub_cmd_panel_cntl_type - Panel control command.
3712b04cb192SNicholas Kazlauskas */
3713b04cb192SNicholas Kazlauskas enum dmub_cmd_panel_cntl_type {
3714b04cb192SNicholas Kazlauskas /**
3715b04cb192SNicholas Kazlauskas * Initializes embedded panel hardware blocks.
3716b04cb192SNicholas Kazlauskas */
3717b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
3718b04cb192SNicholas Kazlauskas /**
3719b04cb192SNicholas Kazlauskas * Queries backlight info for the embedded panel.
3720b04cb192SNicholas Kazlauskas */
3721b04cb192SNicholas Kazlauskas DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
3722b04cb192SNicholas Kazlauskas };
3723b04cb192SNicholas Kazlauskas
3724b04cb192SNicholas Kazlauskas /**
3725b04cb192SNicholas Kazlauskas * struct dmub_cmd_panel_cntl_data - Panel control data.
3726b04cb192SNicholas Kazlauskas */
3727b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data {
3728*71be0f67SLewis Huang uint32_t pwrseq_inst; /**< pwrseq instance */
3729b04cb192SNicholas Kazlauskas uint32_t current_backlight; /* in/out */
3730b04cb192SNicholas Kazlauskas uint32_t bl_pwm_cntl; /* in/out */
3731b04cb192SNicholas Kazlauskas uint32_t bl_pwm_period_cntl; /* in/out */
3732b04cb192SNicholas Kazlauskas uint32_t bl_pwm_ref_div1; /* in/out */
3733b04cb192SNicholas Kazlauskas uint8_t is_backlight_on : 1; /* in/out */
3734b04cb192SNicholas Kazlauskas uint8_t is_powered_on : 1; /* in/out */
3735a91b402dSCharlene Liu uint8_t padding[3];
3736a91b402dSCharlene Liu uint32_t bl_pwm_ref_div2; /* in/out */
3737a91b402dSCharlene Liu uint8_t reserved[4];
3738b04cb192SNicholas Kazlauskas };
3739b04cb192SNicholas Kazlauskas
3740b04cb192SNicholas Kazlauskas /**
3741b04cb192SNicholas Kazlauskas * struct dmub_rb_cmd_panel_cntl - Panel control command.
3742b04cb192SNicholas Kazlauskas */
3743b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl {
3744b04cb192SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */
3745b04cb192SNicholas Kazlauskas struct dmub_cmd_panel_cntl_data data; /**< payload */
3746b04cb192SNicholas Kazlauskas };
3747b04cb192SNicholas Kazlauskas
37481a595f28SAnthony Koo /**
37491a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
37501a595f28SAnthony Koo */
37511a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data {
37521a595f28SAnthony Koo uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3753e0886e1fSTony Tascioglu uint8_t bypass_panel_control_wait;
37540888aa30SAnthony Koo uint8_t reserved_0[2]; /**< For future use */
3755*71be0f67SLewis Huang uint8_t pwrseq_inst; /**< LVTMA control instance */
37561a595f28SAnthony Koo uint8_t reserved_1[3]; /**< For future use */
37571a595f28SAnthony Koo };
37581a595f28SAnthony Koo
37591a595f28SAnthony Koo /**
37601a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
37611a595f28SAnthony Koo */
37621a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control {
37631a595f28SAnthony Koo /**
37641a595f28SAnthony Koo * Command header.
37651a595f28SAnthony Koo */
37661a595f28SAnthony Koo struct dmub_cmd_header header;
37671a595f28SAnthony Koo /**
37681a595f28SAnthony Koo * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
37691a595f28SAnthony Koo */
37701a595f28SAnthony Koo struct dmub_cmd_lvtma_control_data data;
37711a595f28SAnthony Koo };
37721a595f28SAnthony Koo
3773592a6318SAnthony Koo /**
377441f91315SNicholas Kazlauskas * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
377541f91315SNicholas Kazlauskas */
377641f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data {
377741f91315SNicholas Kazlauskas uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
377841f91315SNicholas Kazlauskas uint8_t is_usb; /**< is phy is usb */
377941f91315SNicholas Kazlauskas uint8_t is_dp_alt_disable; /**< is dp alt disable */
378041f91315SNicholas Kazlauskas uint8_t is_dp4; /**< is dp in 4 lane */
378141f91315SNicholas Kazlauskas };
378241f91315SNicholas Kazlauskas
378341f91315SNicholas Kazlauskas /**
378441f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
378541f91315SNicholas Kazlauskas */
378641f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt {
378741f91315SNicholas Kazlauskas struct dmub_cmd_header header; /**< header */
378841f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
378941f91315SNicholas Kazlauskas };
379041f91315SNicholas Kazlauskas
379141f91315SNicholas Kazlauskas /**
3792021eaef8SAnthony Koo * Maximum number of bytes a chunk sent to DMUB for parsing
3793021eaef8SAnthony Koo */
3794021eaef8SAnthony Koo #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
3795021eaef8SAnthony Koo
3796021eaef8SAnthony Koo /**
3797021eaef8SAnthony Koo * Represent a chunk of CEA blocks sent to DMUB for parsing
3798021eaef8SAnthony Koo */
3799021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea {
3800021eaef8SAnthony Koo uint16_t offset; /**< offset into the CEA block */
3801021eaef8SAnthony Koo uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
3802eb9e59ebSOliver Logush uint16_t cea_total_length; /**< total length of the CEA block */
3803021eaef8SAnthony Koo uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
3804021eaef8SAnthony Koo uint8_t pad[3]; /**< padding and for future expansion */
3805021eaef8SAnthony Koo };
3806021eaef8SAnthony Koo
3807021eaef8SAnthony Koo /**
3808021eaef8SAnthony Koo * Result of VSDB parsing from CEA block
3809021eaef8SAnthony Koo */
3810021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb {
3811021eaef8SAnthony Koo uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
3812021eaef8SAnthony Koo uint8_t freesync_supported; /**< 1 if Freesync is supported */
3813021eaef8SAnthony Koo uint16_t amd_vsdb_version; /**< AMD VSDB version */
3814021eaef8SAnthony Koo uint16_t min_frame_rate; /**< Maximum frame rate */
3815021eaef8SAnthony Koo uint16_t max_frame_rate; /**< Minimum frame rate */
3816021eaef8SAnthony Koo };
3817021eaef8SAnthony Koo
3818021eaef8SAnthony Koo /**
3819021eaef8SAnthony Koo * Result of sending a CEA chunk
3820021eaef8SAnthony Koo */
3821021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack {
3822021eaef8SAnthony Koo uint16_t offset; /**< offset of the chunk into the CEA block */
3823021eaef8SAnthony Koo uint8_t success; /**< 1 if this sending of chunk succeeded */
3824021eaef8SAnthony Koo uint8_t pad; /**< padding and for future expansion */
3825021eaef8SAnthony Koo };
3826021eaef8SAnthony Koo
3827021eaef8SAnthony Koo /**
3828021eaef8SAnthony Koo * Specify whether the result is an ACK/NACK or the parsing has finished
3829021eaef8SAnthony Koo */
3830021eaef8SAnthony Koo enum dmub_cmd_edid_cea_reply_type {
3831021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
3832021eaef8SAnthony Koo DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
3833021eaef8SAnthony Koo };
3834021eaef8SAnthony Koo
3835021eaef8SAnthony Koo /**
3836021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command.
3837021eaef8SAnthony Koo */
3838021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea {
3839021eaef8SAnthony Koo struct dmub_cmd_header header; /**< Command header */
3840021eaef8SAnthony Koo union dmub_cmd_edid_cea_data {
3841021eaef8SAnthony Koo struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
3842021eaef8SAnthony Koo struct dmub_cmd_edid_cea_output { /**< output with results */
3843021eaef8SAnthony Koo uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
3844021eaef8SAnthony Koo union {
3845021eaef8SAnthony Koo struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
3846021eaef8SAnthony Koo struct dmub_cmd_edid_cea_ack ack;
3847021eaef8SAnthony Koo };
3848021eaef8SAnthony Koo } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
3849021eaef8SAnthony Koo } data; /**< Command data */
3850021eaef8SAnthony Koo
3851021eaef8SAnthony Koo };
3852021eaef8SAnthony Koo
3853021eaef8SAnthony Koo /**
3854c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
3855c595fb05SWenjing Liu */
3856c595fb05SWenjing Liu struct dmub_cmd_cable_id_input {
3857c595fb05SWenjing Liu uint8_t phy_inst; /**< phy inst for cable id data */
3858c595fb05SWenjing Liu };
3859c595fb05SWenjing Liu
3860c595fb05SWenjing Liu /**
3861c595fb05SWenjing Liu * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
3862c595fb05SWenjing Liu */
3863c595fb05SWenjing Liu struct dmub_cmd_cable_id_output {
3864c595fb05SWenjing Liu uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
3865c595fb05SWenjing Liu uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
3866c595fb05SWenjing Liu uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
3867c595fb05SWenjing Liu uint8_t RESERVED :2; /**< reserved means not defined */
3868c595fb05SWenjing Liu };
3869c595fb05SWenjing Liu
3870c595fb05SWenjing Liu /**
3871c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
3872c595fb05SWenjing Liu */
3873c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id {
3874c595fb05SWenjing Liu struct dmub_cmd_header header; /**< Command header */
3875c595fb05SWenjing Liu /**
3876c595fb05SWenjing Liu * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
3877c595fb05SWenjing Liu */
3878c595fb05SWenjing Liu union dmub_cmd_cable_id_data {
3879c595fb05SWenjing Liu struct dmub_cmd_cable_id_input input; /**< Input */
3880c595fb05SWenjing Liu struct dmub_cmd_cable_id_output output; /**< Output */
3881c595fb05SWenjing Liu uint8_t output_raw; /**< Raw data output */
3882c595fb05SWenjing Liu } data;
3883c595fb05SWenjing Liu };
3884c595fb05SWenjing Liu
38851fb695d9SAnthony Koo /**
38861fb695d9SAnthony Koo * Command type of a DMUB_CMD__SECURE_DISPLAY command
38871fb695d9SAnthony Koo */
3888c0459bddSAlan Liu enum dmub_cmd_secure_display_type {
38891fb695d9SAnthony Koo DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
3890c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
3891c0459bddSAlan Liu DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
3892c0459bddSAlan Liu };
3893c0459bddSAlan Liu
38941fb695d9SAnthony Koo /**
38951fb695d9SAnthony Koo * Definition of a DMUB_CMD__SECURE_DISPLAY command
38961fb695d9SAnthony Koo */
3897c0459bddSAlan Liu struct dmub_rb_cmd_secure_display {
3898c0459bddSAlan Liu struct dmub_cmd_header header;
38991fb695d9SAnthony Koo /**
39001fb695d9SAnthony Koo * Data passed from driver to dmub firmware.
39011fb695d9SAnthony Koo */
3902c0459bddSAlan Liu struct dmub_cmd_roi_info {
3903c0459bddSAlan Liu uint16_t x_start;
3904c0459bddSAlan Liu uint16_t x_end;
3905c0459bddSAlan Liu uint16_t y_start;
3906c0459bddSAlan Liu uint16_t y_end;
3907c0459bddSAlan Liu uint8_t otg_id;
3908c0459bddSAlan Liu uint8_t phy_id;
3909c0459bddSAlan Liu } roi_info;
3910c0459bddSAlan Liu };
3911c0459bddSAlan Liu
3912c595fb05SWenjing Liu /**
3913592a6318SAnthony Koo * union dmub_rb_cmd - DMUB inbox command.
3914592a6318SAnthony Koo */
39157c008829SNicholas Kazlauskas union dmub_rb_cmd {
3916592a6318SAnthony Koo /**
3917592a6318SAnthony Koo * Elements shared with all commands.
3918592a6318SAnthony Koo */
39197c008829SNicholas Kazlauskas struct dmub_rb_cmd_common cmd_common;
3920592a6318SAnthony Koo /**
3921592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
3922592a6318SAnthony Koo */
3923592a6318SAnthony Koo struct dmub_rb_cmd_read_modify_write read_modify_write;
3924592a6318SAnthony Koo /**
3925592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
3926592a6318SAnthony Koo */
3927592a6318SAnthony Koo struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
3928592a6318SAnthony Koo /**
3929592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
3930592a6318SAnthony Koo */
3931592a6318SAnthony Koo struct dmub_rb_cmd_burst_write burst_write;
3932592a6318SAnthony Koo /**
3933592a6318SAnthony Koo * Definition of a DMUB_CMD__REG_REG_WAIT command.
3934592a6318SAnthony Koo */
3935592a6318SAnthony Koo struct dmub_rb_cmd_reg_wait reg_wait;
3936592a6318SAnthony Koo /**
3937592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
3938592a6318SAnthony Koo */
39397c008829SNicholas Kazlauskas struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
3940592a6318SAnthony Koo /**
3941592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
3942592a6318SAnthony Koo */
39437c008829SNicholas Kazlauskas struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
3944592a6318SAnthony Koo /**
3945592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
3946592a6318SAnthony Koo */
39477c008829SNicholas Kazlauskas struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
3948592a6318SAnthony Koo /**
3949592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
3950592a6318SAnthony Koo */
39517c008829SNicholas Kazlauskas struct dmub_rb_cmd_dpphy_init dpphy_init;
3952592a6318SAnthony Koo /**
3953592a6318SAnthony Koo * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
3954592a6318SAnthony Koo */
39557c008829SNicholas Kazlauskas struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
39561a595f28SAnthony Koo /**
3957e383b127SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
3958e383b127SNicholas Kazlauskas */
3959e383b127SNicholas Kazlauskas struct dmub_rb_cmd_domain_control domain_control;
3960e383b127SNicholas Kazlauskas /**
39611a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_VERSION command.
39621a595f28SAnthony Koo */
3963d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_set_version psr_set_version;
39641a595f28SAnthony Koo /**
39651a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
39661a595f28SAnthony Koo */
39677c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
39681a595f28SAnthony Koo /**
39691a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_ENABLE command.
39701a595f28SAnthony Koo */
3971d4b8573eSWyatt Wood struct dmub_rb_cmd_psr_enable psr_enable;
39721a595f28SAnthony Koo /**
39731a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
39741a595f28SAnthony Koo */
39757c008829SNicholas Kazlauskas struct dmub_rb_cmd_psr_set_level psr_set_level;
39761a595f28SAnthony Koo /**
39771a595f28SAnthony Koo * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
39781a595f28SAnthony Koo */
3979672251b2SAnthony Koo struct dmub_rb_cmd_psr_force_static psr_force_static;
3980592a6318SAnthony Koo /**
398183eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
398283eb5385SDavid Zhang */
398383eb5385SDavid Zhang struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
398483eb5385SDavid Zhang /**
398583eb5385SDavid Zhang * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
398683eb5385SDavid Zhang */
398783eb5385SDavid Zhang struct dmub_rb_cmd_update_cursor_info update_cursor_info;
398883eb5385SDavid Zhang /**
398983eb5385SDavid Zhang * Definition of a DMUB_CMD__HW_LOCK command.
399083eb5385SDavid Zhang * Command is used by driver and FW.
399183eb5385SDavid Zhang */
399283eb5385SDavid Zhang struct dmub_rb_cmd_lock_hw lock_hw;
399383eb5385SDavid Zhang /**
399483eb5385SDavid Zhang * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
399583eb5385SDavid Zhang */
399683eb5385SDavid Zhang struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
399783eb5385SDavid Zhang /**
3998e5dfcd27SRobin Chen * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3999e5dfcd27SRobin Chen */
4000e5dfcd27SRobin Chen struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
4001e5dfcd27SRobin Chen /**
4002592a6318SAnthony Koo * Definition of a DMUB_CMD__PLAT_54186_WA command.
4003592a6318SAnthony Koo */
4004bae9c49bSYongqiang Sun struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
4005592a6318SAnthony Koo /**
4006592a6318SAnthony Koo * Definition of a DMUB_CMD__MALL command.
4007592a6318SAnthony Koo */
400852f2e83eSBhawanpreet Lakha struct dmub_rb_cmd_mall mall;
4009b04cb192SNicholas Kazlauskas /**
4010ac2e555eSAurabindo Pillai * Definition of a DMUB_CMD__CAB command.
4011ac2e555eSAurabindo Pillai */
4012ac2e555eSAurabindo Pillai struct dmub_rb_cmd_cab_for_ss cab;
401385f4bc0cSAlvin Lee
401485f4bc0cSAlvin Lee struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
401585f4bc0cSAlvin Lee
4016ac2e555eSAurabindo Pillai /**
4017b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
4018b04cb192SNicholas Kazlauskas */
4019b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
4020b04cb192SNicholas Kazlauskas
4021b04cb192SNicholas Kazlauskas /**
4022b04cb192SNicholas Kazlauskas * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
4023b04cb192SNicholas Kazlauskas */
4024b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
4025b04cb192SNicholas Kazlauskas
4026b04cb192SNicholas Kazlauskas /**
4027b04cb192SNicholas Kazlauskas * Definition of DMUB_CMD__PANEL_CNTL commands.
4028b04cb192SNicholas Kazlauskas */
4029b04cb192SNicholas Kazlauskas struct dmub_rb_cmd_panel_cntl panel_cntl;
40301a595f28SAnthony Koo /**
40311a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PIPE command.
40321a595f28SAnthony Koo */
4033e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
40341a595f28SAnthony Koo
40351a595f28SAnthony Koo /**
40361a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
40371a595f28SAnthony Koo */
4038e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
40391a595f28SAnthony Koo
40401a595f28SAnthony Koo /**
40411a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
40421a595f28SAnthony Koo */
4043e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_level abm_set_level;
40441a595f28SAnthony Koo
40451a595f28SAnthony Koo /**
40461a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
40471a595f28SAnthony Koo */
4048e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
40491a595f28SAnthony Koo
40501a595f28SAnthony Koo /**
40511a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
40521a595f28SAnthony Koo */
4053e6ea8c34SWyatt Wood struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
40541a595f28SAnthony Koo
40551a595f28SAnthony Koo /**
40561a595f28SAnthony Koo * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
40571a595f28SAnthony Koo */
405816012806SWyatt Wood struct dmub_rb_cmd_abm_init_config abm_init_config;
40591a595f28SAnthony Koo
40601a595f28SAnthony Koo /**
4061b629a824SEric Yang * Definition of a DMUB_CMD__ABM_PAUSE command.
4062b629a824SEric Yang */
4063b629a824SEric Yang struct dmub_rb_cmd_abm_pause abm_pause;
4064b629a824SEric Yang
4065b629a824SEric Yang /**
4066da915efaSReza Amini * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4067da915efaSReza Amini */
4068da915efaSReza Amini struct dmub_rb_cmd_abm_save_restore abm_save_restore;
4069da915efaSReza Amini
4070da915efaSReza Amini /**
40711a595f28SAnthony Koo * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
40721a595f28SAnthony Koo */
4073d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_access dp_aux_access;
40741a595f28SAnthony Koo
40751a595f28SAnthony Koo /**
4076592a6318SAnthony Koo * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
4077592a6318SAnthony Koo */
4078592a6318SAnthony Koo struct dmub_rb_cmd_outbox1_enable outbox1_enable;
4079592a6318SAnthony Koo
4080592a6318SAnthony Koo /**
4081592a6318SAnthony Koo * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
40821a595f28SAnthony Koo */
408334ba432cSAnthony Koo struct dmub_rb_cmd_query_feature_caps query_feature_caps;
4084b09c1fffSLeo (Hanghong) Ma
4085b09c1fffSLeo (Hanghong) Ma /**
4086b09c1fffSLeo (Hanghong) Ma * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4087b09c1fffSLeo (Hanghong) Ma */
4088b09c1fffSLeo (Hanghong) Ma struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
4089592a6318SAnthony Koo struct dmub_rb_cmd_drr_update drr_update;
409000fa7f03SRodrigo Siqueira struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
409100fa7f03SRodrigo Siqueira
40921a595f28SAnthony Koo /**
40931a595f28SAnthony Koo * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
40941a595f28SAnthony Koo */
40951a595f28SAnthony Koo struct dmub_rb_cmd_lvtma_control lvtma_control;
4096021eaef8SAnthony Koo /**
409741f91315SNicholas Kazlauskas * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
409841f91315SNicholas Kazlauskas */
409941f91315SNicholas Kazlauskas struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
410041f91315SNicholas Kazlauskas /**
410176724b76SJimmy Kizito * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
410276724b76SJimmy Kizito */
410376724b76SJimmy Kizito struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
410476724b76SJimmy Kizito /**
410571af9d46SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
410671af9d46SMeenakshikumar Somasundaram */
410771af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_config_access set_config_access;
410871af9d46SMeenakshikumar Somasundaram /**
4109139a3311SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
4110139a3311SMeenakshikumar Somasundaram */
4111139a3311SMeenakshikumar Somasundaram struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
4112139a3311SMeenakshikumar Somasundaram /**
4113021eaef8SAnthony Koo * Definition of a DMUB_CMD__EDID_CEA command.
4114021eaef8SAnthony Koo */
4115021eaef8SAnthony Koo struct dmub_rb_cmd_edid_cea edid_cea;
4116c595fb05SWenjing Liu /**
4117c595fb05SWenjing Liu * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
4118c595fb05SWenjing Liu */
4119c595fb05SWenjing Liu struct dmub_rb_cmd_get_usbc_cable_id cable_id;
4120ea5a4db9SAnthony Koo
4121ea5a4db9SAnthony Koo /**
4122ea5a4db9SAnthony Koo * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
4123ea5a4db9SAnthony Koo */
4124ea5a4db9SAnthony Koo struct dmub_rb_cmd_query_hpd_state query_hpd;
41256f4f8ff5SMeenakshikumar Somasundaram /**
4126c0459bddSAlan Liu * Definition of a DMUB_CMD__SECURE_DISPLAY command.
4127c0459bddSAlan Liu */
4128c0459bddSAlan Liu struct dmub_rb_cmd_secure_display secure_display;
41291fb695d9SAnthony Koo
4130c0459bddSAlan Liu /**
41316f4f8ff5SMeenakshikumar Somasundaram * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
41326f4f8ff5SMeenakshikumar Somasundaram */
41336f4f8ff5SMeenakshikumar Somasundaram struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
413427664177SAnthony Koo /**
413527664177SAnthony Koo * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
413627664177SAnthony Koo */
413727664177SAnthony Koo struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
4138e0138644SBhawanpreet Lakha /*
4139e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4140e0138644SBhawanpreet Lakha */
4141e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
4142e0138644SBhawanpreet Lakha /**
4143e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4144e0138644SBhawanpreet Lakha */
4145e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_enable replay_enable;
4146e0138644SBhawanpreet Lakha /**
4147e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4148e0138644SBhawanpreet Lakha */
4149e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
4150e0138644SBhawanpreet Lakha /**
4151e0138644SBhawanpreet Lakha * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4152e0138644SBhawanpreet Lakha */
4153e0138644SBhawanpreet Lakha struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
41547c008829SNicholas Kazlauskas };
41557c008829SNicholas Kazlauskas
4156592a6318SAnthony Koo /**
4157592a6318SAnthony Koo * union dmub_rb_out_cmd - Outbox command
4158592a6318SAnthony Koo */
4159d9beecfcSAnthony Koo union dmub_rb_out_cmd {
4160592a6318SAnthony Koo /**
4161592a6318SAnthony Koo * Parameters common to every command.
4162592a6318SAnthony Koo */
4163d9beecfcSAnthony Koo struct dmub_rb_cmd_common cmd_common;
4164592a6318SAnthony Koo /**
4165592a6318SAnthony Koo * AUX reply command.
4166592a6318SAnthony Koo */
4167d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
4168592a6318SAnthony Koo /**
4169592a6318SAnthony Koo * HPD notify command.
4170592a6318SAnthony Koo */
4171d9beecfcSAnthony Koo struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
417271af9d46SMeenakshikumar Somasundaram /**
417371af9d46SMeenakshikumar Somasundaram * SET_CONFIG reply command.
417471af9d46SMeenakshikumar Somasundaram */
417571af9d46SMeenakshikumar Somasundaram struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
4176669018a9SMustapha Ghaddar /**
41778af54c61SMustapha Ghaddar * DPIA notification command.
4178669018a9SMustapha Ghaddar */
41798af54c61SMustapha Ghaddar struct dmub_rb_cmd_dpia_notification dpia_notification;
4180d9beecfcSAnthony Koo };
41817c008829SNicholas Kazlauskas #pragma pack(pop)
41827c008829SNicholas Kazlauskas
418384034ad4SAnthony Koo
418484034ad4SAnthony Koo //==============================================================================
418584034ad4SAnthony Koo //</DMUB_CMD>===================================================================
418684034ad4SAnthony Koo //==============================================================================
418784034ad4SAnthony Koo //< DMUB_RB>====================================================================
418884034ad4SAnthony Koo //==============================================================================
418984034ad4SAnthony Koo
419084034ad4SAnthony Koo #if defined(__cplusplus)
419184034ad4SAnthony Koo extern "C" {
419284034ad4SAnthony Koo #endif
419384034ad4SAnthony Koo
4194592a6318SAnthony Koo /**
4195592a6318SAnthony Koo * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
4196592a6318SAnthony Koo */
419784034ad4SAnthony Koo struct dmub_rb_init_params {
4198592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */
4199592a6318SAnthony Koo void *base_address; /**< CPU base address for ring's data */
4200592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */
4201592a6318SAnthony Koo uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
4202592a6318SAnthony Koo uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
420384034ad4SAnthony Koo };
420484034ad4SAnthony Koo
4205592a6318SAnthony Koo /**
4206592a6318SAnthony Koo * struct dmub_rb - Inbox or outbox DMUB ringbuffer
4207592a6318SAnthony Koo */
420884034ad4SAnthony Koo struct dmub_rb {
4209592a6318SAnthony Koo void *base_address; /**< CPU address for the ring's data */
4210592a6318SAnthony Koo uint32_t rptr; /**< Read pointer for consumer in bytes */
4211592a6318SAnthony Koo uint32_t wrpt; /**< Write pointer for producer in bytes */
4212592a6318SAnthony Koo uint32_t capacity; /**< Ringbuffer capacity in bytes */
421384034ad4SAnthony Koo
4214592a6318SAnthony Koo void *ctx; /**< Caller provided context pointer */
4215592a6318SAnthony Koo void *dmub; /**< Pointer to the DMUB interface */
421684034ad4SAnthony Koo };
421784034ad4SAnthony Koo
4218592a6318SAnthony Koo /**
4219592a6318SAnthony Koo * @brief Checks if the ringbuffer is empty.
4220592a6318SAnthony Koo *
4221592a6318SAnthony Koo * @param rb DMUB Ringbuffer
4222592a6318SAnthony Koo * @return true if empty
4223592a6318SAnthony Koo * @return false otherwise
4224592a6318SAnthony Koo */
dmub_rb_empty(struct dmub_rb * rb)422584034ad4SAnthony Koo static inline bool dmub_rb_empty(struct dmub_rb *rb)
422684034ad4SAnthony Koo {
422784034ad4SAnthony Koo return (rb->wrpt == rb->rptr);
422884034ad4SAnthony Koo }
422984034ad4SAnthony Koo
4230592a6318SAnthony Koo /**
4231592a6318SAnthony Koo * @brief Checks if the ringbuffer is full
4232592a6318SAnthony Koo *
4233592a6318SAnthony Koo * @param rb DMUB Ringbuffer
4234592a6318SAnthony Koo * @return true if full
4235592a6318SAnthony Koo * @return false otherwise
4236592a6318SAnthony Koo */
dmub_rb_full(struct dmub_rb * rb)423784034ad4SAnthony Koo static inline bool dmub_rb_full(struct dmub_rb *rb)
423884034ad4SAnthony Koo {
423984034ad4SAnthony Koo uint32_t data_count;
424084034ad4SAnthony Koo
424184034ad4SAnthony Koo if (rb->wrpt >= rb->rptr)
424284034ad4SAnthony Koo data_count = rb->wrpt - rb->rptr;
424384034ad4SAnthony Koo else
424484034ad4SAnthony Koo data_count = rb->capacity - (rb->rptr - rb->wrpt);
424584034ad4SAnthony Koo
424684034ad4SAnthony Koo return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
424784034ad4SAnthony Koo }
424884034ad4SAnthony Koo
4249592a6318SAnthony Koo /**
4250592a6318SAnthony Koo * @brief Pushes a command into the ringbuffer
4251592a6318SAnthony Koo *
4252592a6318SAnthony Koo * @param rb DMUB ringbuffer
4253592a6318SAnthony Koo * @param cmd The command to push
4254592a6318SAnthony Koo * @return true if the ringbuffer was not full
4255592a6318SAnthony Koo * @return false otherwise
4256592a6318SAnthony Koo */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)425784034ad4SAnthony Koo static inline bool dmub_rb_push_front(struct dmub_rb *rb,
425884034ad4SAnthony Koo const union dmub_rb_cmd *cmd)
425984034ad4SAnthony Koo {
42603f232a0fSAnthony Koo uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
42613a9d5b0bSAnthony Koo const uint64_t *src = (const uint64_t *)cmd;
42623a9d5b0bSAnthony Koo uint8_t i;
426384034ad4SAnthony Koo
426484034ad4SAnthony Koo if (dmub_rb_full(rb))
426584034ad4SAnthony Koo return false;
426684034ad4SAnthony Koo
426784034ad4SAnthony Koo // copying data
42683a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
42693a9d5b0bSAnthony Koo *dst++ = *src++;
427084034ad4SAnthony Koo
427184034ad4SAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE;
427284034ad4SAnthony Koo
427384034ad4SAnthony Koo if (rb->wrpt >= rb->capacity)
427484034ad4SAnthony Koo rb->wrpt %= rb->capacity;
427584034ad4SAnthony Koo
427684034ad4SAnthony Koo return true;
427784034ad4SAnthony Koo }
427884034ad4SAnthony Koo
4279592a6318SAnthony Koo /**
4280592a6318SAnthony Koo * @brief Pushes a command into the DMUB outbox ringbuffer
4281592a6318SAnthony Koo *
4282592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer
4283592a6318SAnthony Koo * @param cmd Outbox command
4284592a6318SAnthony Koo * @return true if not full
4285592a6318SAnthony Koo * @return false otherwise
4286592a6318SAnthony Koo */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)4287d9beecfcSAnthony Koo static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
4288d9beecfcSAnthony Koo const union dmub_rb_out_cmd *cmd)
4289d9beecfcSAnthony Koo {
4290d9beecfcSAnthony Koo uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
4291d459b79bSAnthony Koo const uint8_t *src = (const uint8_t *)cmd;
4292d9beecfcSAnthony Koo
4293d9beecfcSAnthony Koo if (dmub_rb_full(rb))
4294d9beecfcSAnthony Koo return false;
4295d9beecfcSAnthony Koo
4296d9beecfcSAnthony Koo dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
4297d9beecfcSAnthony Koo
4298d9beecfcSAnthony Koo rb->wrpt += DMUB_RB_CMD_SIZE;
4299d9beecfcSAnthony Koo
4300d9beecfcSAnthony Koo if (rb->wrpt >= rb->capacity)
4301d9beecfcSAnthony Koo rb->wrpt %= rb->capacity;
4302d9beecfcSAnthony Koo
4303d9beecfcSAnthony Koo return true;
4304d9beecfcSAnthony Koo }
4305d9beecfcSAnthony Koo
4306592a6318SAnthony Koo /**
4307592a6318SAnthony Koo * @brief Returns the next unprocessed command in the ringbuffer.
4308592a6318SAnthony Koo *
4309592a6318SAnthony Koo * @param rb DMUB ringbuffer
4310592a6318SAnthony Koo * @param cmd The command to return
4311592a6318SAnthony Koo * @return true if not empty
4312592a6318SAnthony Koo * @return false otherwise
4313592a6318SAnthony Koo */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)431484034ad4SAnthony Koo static inline bool dmub_rb_front(struct dmub_rb *rb,
431534ba432cSAnthony Koo union dmub_rb_cmd **cmd)
431684034ad4SAnthony Koo {
431734ba432cSAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
431884034ad4SAnthony Koo
431984034ad4SAnthony Koo if (dmub_rb_empty(rb))
432084034ad4SAnthony Koo return false;
432184034ad4SAnthony Koo
432234ba432cSAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd;
432384034ad4SAnthony Koo
432484034ad4SAnthony Koo return true;
432584034ad4SAnthony Koo }
432684034ad4SAnthony Koo
4327592a6318SAnthony Koo /**
43280b51e7e8SAnthony Koo * @brief Determines the next ringbuffer offset.
43290b51e7e8SAnthony Koo *
43300b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer
43310b51e7e8SAnthony Koo * @param num_cmds Number of commands
43320b51e7e8SAnthony Koo * @param next_rptr The next offset in the ringbuffer
43330b51e7e8SAnthony Koo */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)43340b51e7e8SAnthony Koo static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
43350b51e7e8SAnthony Koo uint32_t num_cmds,
43360b51e7e8SAnthony Koo uint32_t *next_rptr)
43370b51e7e8SAnthony Koo {
43380b51e7e8SAnthony Koo *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
43390b51e7e8SAnthony Koo
43400b51e7e8SAnthony Koo if (*next_rptr >= rb->capacity)
43410b51e7e8SAnthony Koo *next_rptr %= rb->capacity;
43420b51e7e8SAnthony Koo }
43430b51e7e8SAnthony Koo
43440b51e7e8SAnthony Koo /**
43450b51e7e8SAnthony Koo * @brief Returns a pointer to a command in the inbox.
43460b51e7e8SAnthony Koo *
43470b51e7e8SAnthony Koo * @param rb DMUB inbox ringbuffer
43480b51e7e8SAnthony Koo * @param cmd The inbox command to return
43490b51e7e8SAnthony Koo * @param rptr The ringbuffer offset
43500b51e7e8SAnthony Koo * @return true if not empty
43510b51e7e8SAnthony Koo * @return false otherwise
43520b51e7e8SAnthony Koo */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)43530b51e7e8SAnthony Koo static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
43540b51e7e8SAnthony Koo union dmub_rb_cmd **cmd,
43550b51e7e8SAnthony Koo uint32_t rptr)
43560b51e7e8SAnthony Koo {
43570b51e7e8SAnthony Koo uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
43580b51e7e8SAnthony Koo
43590b51e7e8SAnthony Koo if (dmub_rb_empty(rb))
43600b51e7e8SAnthony Koo return false;
43610b51e7e8SAnthony Koo
43620b51e7e8SAnthony Koo *cmd = (union dmub_rb_cmd *)rb_cmd;
43630b51e7e8SAnthony Koo
43640b51e7e8SAnthony Koo return true;
43650b51e7e8SAnthony Koo }
43660b51e7e8SAnthony Koo
43670b51e7e8SAnthony Koo /**
4368592a6318SAnthony Koo * @brief Returns the next unprocessed command in the outbox.
4369592a6318SAnthony Koo *
4370592a6318SAnthony Koo * @param rb DMUB outbox ringbuffer
4371592a6318SAnthony Koo * @param cmd The outbox command to return
4372592a6318SAnthony Koo * @return true if not empty
4373592a6318SAnthony Koo * @return false otherwise
4374592a6318SAnthony Koo */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)4375d9beecfcSAnthony Koo static inline bool dmub_rb_out_front(struct dmub_rb *rb,
4376d9beecfcSAnthony Koo union dmub_rb_out_cmd *cmd)
4377d9beecfcSAnthony Koo {
43783f232a0fSAnthony Koo const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
43793a9d5b0bSAnthony Koo uint64_t *dst = (uint64_t *)cmd;
43803a9d5b0bSAnthony Koo uint8_t i;
4381d9beecfcSAnthony Koo
4382d9beecfcSAnthony Koo if (dmub_rb_empty(rb))
4383d9beecfcSAnthony Koo return false;
4384d9beecfcSAnthony Koo
4385d9beecfcSAnthony Koo // copying data
43863a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
43873a9d5b0bSAnthony Koo *dst++ = *src++;
4388d9beecfcSAnthony Koo
4389d9beecfcSAnthony Koo return true;
4390d9beecfcSAnthony Koo }
4391d9beecfcSAnthony Koo
4392592a6318SAnthony Koo /**
4393592a6318SAnthony Koo * @brief Removes the front entry in the ringbuffer.
4394592a6318SAnthony Koo *
4395592a6318SAnthony Koo * @param rb DMUB ringbuffer
4396592a6318SAnthony Koo * @return true if the command was removed
4397592a6318SAnthony Koo * @return false if there were no commands
4398592a6318SAnthony Koo */
dmub_rb_pop_front(struct dmub_rb * rb)439984034ad4SAnthony Koo static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
440084034ad4SAnthony Koo {
440184034ad4SAnthony Koo if (dmub_rb_empty(rb))
440284034ad4SAnthony Koo return false;
440384034ad4SAnthony Koo
440484034ad4SAnthony Koo rb->rptr += DMUB_RB_CMD_SIZE;
440584034ad4SAnthony Koo
440684034ad4SAnthony Koo if (rb->rptr >= rb->capacity)
440784034ad4SAnthony Koo rb->rptr %= rb->capacity;
440884034ad4SAnthony Koo
440984034ad4SAnthony Koo return true;
441084034ad4SAnthony Koo }
441184034ad4SAnthony Koo
4412592a6318SAnthony Koo /**
4413592a6318SAnthony Koo * @brief Flushes commands in the ringbuffer to framebuffer memory.
4414592a6318SAnthony Koo *
4415592a6318SAnthony Koo * Avoids a race condition where DMCUB accesses memory while
4416592a6318SAnthony Koo * there are still writes in flight to framebuffer.
4417592a6318SAnthony Koo *
4418592a6318SAnthony Koo * @param rb DMUB ringbuffer
4419592a6318SAnthony Koo */
dmub_rb_flush_pending(const struct dmub_rb * rb)442084034ad4SAnthony Koo static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
442184034ad4SAnthony Koo {
442284034ad4SAnthony Koo uint32_t rptr = rb->rptr;
442384034ad4SAnthony Koo uint32_t wptr = rb->wrpt;
442484034ad4SAnthony Koo
442584034ad4SAnthony Koo while (rptr != wptr) {
44267da7b02eSAashish Sharma uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
44273a9d5b0bSAnthony Koo uint8_t i;
442884034ad4SAnthony Koo
442923da6e0fSMaíra Canal /* Don't remove this.
443023da6e0fSMaíra Canal * The contents need to actually be read from the ring buffer
443123da6e0fSMaíra Canal * for this function to be effective.
443223da6e0fSMaíra Canal */
44333a9d5b0bSAnthony Koo for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
44347da7b02eSAashish Sharma (void)READ_ONCE(*data++);
443584034ad4SAnthony Koo
443684034ad4SAnthony Koo rptr += DMUB_RB_CMD_SIZE;
443784034ad4SAnthony Koo if (rptr >= rb->capacity)
443884034ad4SAnthony Koo rptr %= rb->capacity;
443984034ad4SAnthony Koo }
444084034ad4SAnthony Koo }
444184034ad4SAnthony Koo
4442592a6318SAnthony Koo /**
4443592a6318SAnthony Koo * @brief Initializes a DMCUB ringbuffer
4444592a6318SAnthony Koo *
4445592a6318SAnthony Koo * @param rb DMUB ringbuffer
4446592a6318SAnthony Koo * @param init_params initial configuration for the ringbuffer
4447592a6318SAnthony Koo */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)444884034ad4SAnthony Koo static inline void dmub_rb_init(struct dmub_rb *rb,
444984034ad4SAnthony Koo struct dmub_rb_init_params *init_params)
445084034ad4SAnthony Koo {
445184034ad4SAnthony Koo rb->base_address = init_params->base_address;
445284034ad4SAnthony Koo rb->capacity = init_params->capacity;
445384034ad4SAnthony Koo rb->rptr = init_params->read_ptr;
445484034ad4SAnthony Koo rb->wrpt = init_params->write_ptr;
445584034ad4SAnthony Koo }
445684034ad4SAnthony Koo
4457592a6318SAnthony Koo /**
4458592a6318SAnthony Koo * @brief Copies output data from in/out commands into the given command.
4459592a6318SAnthony Koo *
4460592a6318SAnthony Koo * @param rb DMUB ringbuffer
4461592a6318SAnthony Koo * @param cmd Command to copy data into
4462592a6318SAnthony Koo */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)446334ba432cSAnthony Koo static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
446434ba432cSAnthony Koo union dmub_rb_cmd *cmd)
446534ba432cSAnthony Koo {
446634ba432cSAnthony Koo // Copy rb entry back into command
446734ba432cSAnthony Koo uint8_t *rd_ptr = (rb->rptr == 0) ?
446834ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
446934ba432cSAnthony Koo (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
447034ba432cSAnthony Koo
447134ba432cSAnthony Koo dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
447234ba432cSAnthony Koo }
447334ba432cSAnthony Koo
447484034ad4SAnthony Koo #if defined(__cplusplus)
447584034ad4SAnthony Koo }
447684034ad4SAnthony Koo #endif
447784034ad4SAnthony Koo
447884034ad4SAnthony Koo //==============================================================================
447984034ad4SAnthony Koo //</DMUB_RB>====================================================================
448084034ad4SAnthony Koo //==============================================================================
448184034ad4SAnthony Koo
44827c008829SNicholas Kazlauskas #endif /* _DMUB_CMD_H_ */
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