Lines Matching +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy
1 /* SPDX-License-Identifier: GPL-2.0+ */
5 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
10 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
36 printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
40 printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
51 writel((value), ((a)->hw_addr + E1000_##reg))
53 readl((a)->hw_addr + E1000_##reg)
55 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
57 readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
169 /* PHY status info structure and supporting enums */
322 #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
328 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
345 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
347 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
349 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
356 state of 100BASE-TX */
358 state of 10BASE-T */
359 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
361 #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
363 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
365 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
380 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
382 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
384 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
388 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
394 #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
414 /* MAC decode size is 128K - This is the size of BAR0 */
435 (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
437 (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN)
480 * E1000_RAR_ENTRIES - 1 multicast addresses.
504 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
557 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
683 * RW - register is both readable and writable
684 * RO - register is read only
685 * WO - register is write only
686 * R/clr - register is read only and is cleared when read
687 * A - register array
689 #define E1000_CTRL 0x00000 /* Device Control - RW */
690 #define E1000_STATUS 0x00008 /* Device Status - RO */
691 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
692 #define E1000_I210_EECD 0x12010 /* EEPROM/Flash Control - RW */
693 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
694 #define E1000_I210_EERD 0x12014 /* EEPROM Read - RW */
695 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
696 #define E1000_MDIC 0x00020 /* MDI Control - RW */
697 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
698 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
699 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
700 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
701 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
702 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
703 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
704 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
705 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
706 #define E1000_I210_IAM 0x000E0 /* Interrupt Ack Auto Mask - RW */
707 #define E1000_RCTL 0x00100 /* RX Control - RW */
708 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
709 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
710 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
711 #define E1000_TCTL 0x00400 /* TX Control - RW */
712 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
713 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
714 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
715 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
716 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
719 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
720 #define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */
722 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
729 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
730 #define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */
735 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
736 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
737 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
738 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
739 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
740 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
741 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
742 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
743 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
744 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
745 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
746 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
747 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
748 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
749 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
750 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
751 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
752 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
753 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
754 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
755 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
756 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
757 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
758 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
759 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
760 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
761 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
763 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
764 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
765 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
766 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
767 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
768 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
770 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
771 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
772 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
773 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
774 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
775 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
776 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
777 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
778 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
779 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
780 #define E1000_DC 0x04030 /* Defer Count - R/clr */
781 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
782 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
783 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
784 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
785 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
786 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
787 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
788 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
789 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
790 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
791 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
792 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
793 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
794 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
795 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
796 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
797 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
798 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
799 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
800 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
801 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
802 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
803 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
804 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
805 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
806 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
807 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
808 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
809 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
810 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
811 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
812 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
813 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
814 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
815 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
816 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
817 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
818 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
819 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
820 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
821 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
822 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
823 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
824 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
825 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
826 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
827 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
828 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
829 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
830 #define E1000_RA 0x05400 /* Receive Address - RW Array */
831 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
832 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
833 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
834 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
835 #define E1000_MANC 0x05820 /* Management Control - RW */
836 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
837 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
838 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
839 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
840 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
841 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
842 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
843 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1167 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1169 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1181 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1182 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1183 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1184 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1190 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1208 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1209 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1210 #define E1000_STATUS_PF_RST_DONE 0x00200000 /* PCI-X bus speed */
1212 /* Constants used to intrepret the masked PCI-X bus speed. */
1213 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1214 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1215 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1231 * (0-small, 1-large) */
1233 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1266 /* EEPROM Commands - Microwire */
1273 /* EEPROM Commands - SPI */
1277 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1330 #define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
1332 #define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
1515 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1554 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1563 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1574 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1575 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1624 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1625 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1626 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1769 /* Flow Control High-Watermark: 43464 bytes */
1771 /* Flow Control Low-Watermark: 43456 bytes */
1815 /* The number of milliseconds we wait for auto-negotiation to complete */
1843 * frame_length--;
1851 ((adapter)->tbi_compatibility_on && \
1855 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1856 ((length) <= ((adapter)->max_frame_size + 1))) : \
1857 (((length) > (adapter)->min_frame_size) && \
1858 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1860 /* Structures, enums, and macros for the PHY */
1874 /* PHY 1000 MII Register/Bit Definitions */
1875 /* PHY Registers defined by IEEE */
1878 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1879 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1885 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1886 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1890 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1891 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1894 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1900 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1919 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1920 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1921 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1922 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1924 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1926 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1928 /* IGP01E1000 AGC Registers - stores the cable length values*/
1934 /* IGP01E1000 Specific Port Config Register - R/W */
1949 non-D0a modes */
1975 /* IGP01E1000 PCS Initialization register - stores the polarity status when
1984 * on Link-Up */
2004 /* IGP01E1000 Specific Port Control Register - R/W */
2010 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2011 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2037 /* PHY Specific Status Register (Page 0, Register 17) */
2049 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
2055 /* PHY Specific Status Register 2 (Page 0, Register 19) */
2064 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
2068 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
2070 /* PHY Specific Control Register 2 (Page 0, Register 26) */
2081 Auto-Negotiation */
2083 1000BASE-T */
2089 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2100 1 = 50-80M;
2101 2 = 80-110M;
2102 3 = 110-140M;
2106 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
2121 Auto-Negotiation */
2123 Auto-Neg in non D0 */
2125 Auto-Neg Always */
2127 Reverse Auto-Negotiation */
2135 /* In-Band Control Register (Page 194, Register 18) */
2140 * 15-5: page
2141 * 4-0: register offset
2150 GG82563_REG(0, 16) /* PHY Specific Control */
2152 GG82563_REG(0, 17) /* PHY Specific Status */
2156 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2162 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2176 /* Page 193 - Port Control Registers */
2190 /* Page 194 - KMRN Registers */
2212 /* PHY Control Register */
2217 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2222 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2224 /* PHY Status Register */
2300 /* 1000BASE-T Control Register */
2306 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2307 /* 0=Configure PHY as Slave */
2316 /* 1000BASE-T Status Register */
2340 /* M88E1000 PHY Specific Control Register */
2350 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2351 * 100BASE-TX/10BASE-T:
2358 /* 1=Enable Extended 10BASE-T distance
2359 * (Lower 10BASE-T RX Threshold)
2360 * 0=Normal 10BASE-T RX Threshold */
2362 /* 1=5-Bit interface in 100BASE-TX
2363 * 0=MII interface in 100BASE-TX */
2372 /* M88E1000 PHY Specific Status Register */
2376 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2377 * 3=110-140M;4=>140M */
2391 /* M88E1000 Extended PHY Specific Control Register */
2396 * within 1ms in 1000BASE-T
2416 /* Bit definitions for valid PHY IDs. */
2432 /* Miscellaneous PHY bit definitions. */
2479 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
2499 #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2508 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
2509 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
2510 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
2511 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
2512 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
2523 /* Mask bit for PHY class in Word 7 of the EEPROM */
2525 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2548 /* In-Band Control */
2552 /* Half-Duplex Control */
2567 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2568 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
2569 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
2576 /* Switch to override PHY master/slave setting */