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/openbmc/linux/drivers/net/ethernet/arc/
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
12 #include <linux/dma-mapping.h>
27 #define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
34 #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
38 #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
77 * struct arc_emac_bd - EMAC buffer descriptor (BD).
80 * @data: 32-bit byte addressable pointer to the packet data.
87 /* Number of Rx/Tx BD's */
95 * struct buffer_state - Stores Rx/Tx buffer state.
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/openbmc/u-boot/arch/arm/mach-tegra/
H A Dboard2.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/board.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/sys_proto.h>
19 #include <asm/arch-tegra/uart.h>
20 #include <asm/arch-tegra/warmboot.h>
21 #include <asm/arch-tegra/gpu.h>
22 #include <asm/arch-tegra/usb.h>
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/openbmc/u-boot/arch/arm/lib/
H A Dbootm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
4 * - Added prep subcommand support
5 * - Reorganized source - modeled after powerpc version
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
19 #include <u-boot/zlib.h>
55 * Allocate space for command line and board info - the in arch_lmb_reserve()
56 * address should be as high as possible within the reach of in arch_lmb_reserve()
65 sp -= 4096; in arch_lmb_reserve()
67 if (!gd->bd->bi_dram[bank].size || in arch_lmb_reserve()
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/openbmc/u-boot/drivers/net/
H A Dfec_mxc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
25 /* Control and status Registers (offset 000-1FF) */
33 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
36 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
39 uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
42 uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
44 uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
46 uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
51 uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
56 uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
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H A Dethoc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
7 * Thierry Reding <thierry.reding@avionic-design.de>
49 #define MODER_BRO (1 << 3) /* broadcast address */
50 #define MODER_IAM (1 << 4) /* individual address mode */
54 #define MODER_NBO (1 << 8) /* no back-off */
106 /* MII address register */
168 * struct ethoc - driver-private device structure
192 * struct ethoc_bd - buffer descriptor
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H A Dxilinx_axi_emac.c1 // SPDX-License-Identifier: GPL-2.0+
42 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
43 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
44 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
45 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
98 /* BD descriptors */
102 u32 phys; /* Buffer address */
118 /* Static BDs - driver uses only one BD */
138 u32 uaw0; /* 0x700: Unicast address word 0 */
139 u32 uaw1; /* 0x704: Unicast address word 1 */
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/openbmc/qemu/hw/net/
H A Dftgmac100.c4 * Copyright (C) 2016-2017, IBM Corporation.
11 * COPYING file in the top-level directory.
24 #include "hw/qdev-properties.h"
61 * values below are offset by - FTGMAC100_REG_HIGH_OFFSET from datasheet
64 #define FTGMAC100_NPTXR_BADR_HIGH (0x17C - FTGMAC100_REG_HIGH_OFFSET)
65 #define FTGMAC100_HPTXR_BADR_HIGH (0x184 - FTGMAC100_REG_HIGH_OFFSET)
66 #define FTGMAC100_RXR_BADR_HIGH (0x18C - FTGMAC100_REG_HIGH_OFFSET)
117 * PHY control register - New MDC/MDIO interface
262 int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518); in ftgmac100_max_frame_size()
269 qemu_set_irq(s->irq, s->isr & s->ier); in ftgmac100_update_irq()
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H A Dspapr_llan.c4 * PAPR Inter-VM Logical Lan, aka ibmveth
35 #include "hw/qdev-properties.h"
60 #define VLAN_BD_LEN(bd) (((bd) & VLAN_BD_LEN_MASK) >> 32) argument
62 #define VLAN_BD_ADDR(bd) ((bd) & VLAN_BD_ADDR_MASK) argument
83 #define VLAN_RX_BDS_LEN (SPAPR_TCE_PAGE_SIZE - VLAN_RX_BDS_OFF - 8)
86 #define TYPE_VIO_SPAPR_VLAN_DEVICE "spapr-vlan"
116 return dev->isopen && dev->rx_bufs > 0; in spapr_vlan_can_receive()
130 cnt = vio_ldq(&dev->sdev, dev->buf_list + 4096 - 8); in spapr_vlan_record_dropped_rx_frame()
131 vio_stq(&dev->sdev, dev->buf_list + 4096 - 8, cnt + 1); in spapr_vlan_record_dropped_rx_frame()
140 vlan_bd_t bd; in spapr_vlan_get_rx_bd_from_pool() local
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/armada100/
H A Ddram.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
25 u32 cs; /* Memory Address Map Register -CS */
30 u8 pad[0x100 - 0x000];
35 * armd1_sdram_base - reads SDRAM Base Address Register
42 u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); in armd1_sdram_base()
47 result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; in armd1_sdram_base()
52 * armd1_sdram_size - reads SDRAM size
59 u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); in armd1_sdram_size()
64 result = readl(&ddr_regs->mmap[chip_sel].cs); in armd1_sdram_size()
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/openbmc/linux/drivers/scsi/bnx2i/
H A Dbnx2i.h3 * Copyright (c) 2006 - 2013 Broadcom Corporation
14 * Maintained by: QLogic-Storage-Upstream@qlogic.com
60 #define ISCSI_MAX_CMDS_PER_HBA_5708 (28 * (ISCSI_MAX_CMDS_PER_SESS - 1))
61 #define ISCSI_MAX_CMDS_PER_HBA_5709 (128 * (ISCSI_MAX_CMDS_PER_SESS - 1))
62 #define ISCSI_MAX_CMDS_PER_HBA_57710 (256 * (ISCSI_MAX_CMDS_PER_SESS - 1))
71 /* 5706/08 hardware has limit on maximum buffer size per BD it can handle */
129 readl(__hba->regview + offset)
131 writel(val, __hba->regview + offset)
136 spin_lock_bh(&__hba->stat_lock); \
137 dst->field##_lo = __hba->stats.field##_lo; \
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/openbmc/linux/drivers/net/wan/
H A Dwanxlfw.S1 /* SPDX-License-Identifier: GPL-2.0-only */
14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#0
15 0x140 - 0x190 TX#1 0x190 - 0x280 RX#1
16 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#2
17 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#3
20 000 5FF 1536 Bytes Dual-Port RAM User Data / BDs
21 600 6FF 256 Bytes Dual-Port RAM User Data / BDs
22 700 7FF 256 Bytes Dual-Port RAM User Data / BDs
23 C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 1
24 D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 2
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/openbmc/linux/include/soc/fsl/qe/
H A Ducc_slow.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 /* transmit BD's status */
28 #define T_A 0x04000000 /* Address - the data transmitted as address
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
44 /* Receive BD's status */
52 #define R_A 0x04000000 /* the first byte in this buffer is address
58 #define R_AM 0x00800000 /* Address match */
59 #define R_DE 0x00800000 /* Address match */
89 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
93 /* 32-bit CCITT CRC (Ethernet and HDLC) */
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
22 #include <fsl-mc/fsl_mc.h>
86 /* For IFC Region #1, only the first 4MB is cache-enabled */
93 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
114 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
227 /* For QBMAN portal, only the first 64MB is cache-enabled */
235 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
368 svr = gur_in32(&gur->svr); in cpu_name()
394 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
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/openbmc/linux/drivers/dma/
H A Dimx-sdma.c1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
27 #include <linux/dma-mapping.h>
38 #include <linux/dma/imx-dma.h>
41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 #include "virt-dma.h"
122 * Change endianness indicator in the BD command field
129 * 0-7 Lower WML Lower watermark level
140 * 13-15 --------- MUST BE 0
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/openbmc/u-boot/board/armltd/vexpress/
H A Dvexpress_common.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
23 #include <asm/mach-types.h>
52 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; in board_init()
53 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; in board_init()
54 gd->flags = 0; in board_init()
82 return -ENOMEM; in cpu_mmc_init()
85 strcpy(host->name, "MMC"); in cpu_mmc_init()
86 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; in cpu_mmc_init()
87 host->pwr_init = INIT_PWR; in cpu_mmc_init()
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/openbmc/u-boot/board/qualcomm/dragonboard410c/
H A Ddragonboard410c.c1 // SPDX-License-Identifier: GPL-2.0+
34 gd->ram_size = PHYS_SDRAM_1_SIZE; in dram_init()
41 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
42 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; in dram_init_banksize()
65 node = fdt_subnode_offset(gd->fdt_blob, in board_usb_init()
81 node = fdt_subnode_offset(gd->fdt_blob, in board_usb_init()
115 /* Check for vol- button - if pressed - stop autoboot */
128 node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), in misc_init_r()
142 env_set("bootdelay", "-1"); in misc_init_r()
144 printf("key_vol_down pressed - Starting fastboot.\n"); in misc_init_r()
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/openbmc/linux/drivers/net/ethernet/freescale/
H A Ducc_geth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
26 #include <linux/dma-mapping.h>
62 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
69 } debug = { -1 };
102 /* adjusted at startup if max-speed 1000 */
215 struct list_head *node = lh->next; in dequeue()
226 u8 __iomem *bd) in get_new_skb() argument
230 skb = netdev_alloc_skb(ugeth->ndev, in get_new_skb()
231 ugeth->ug_info->uf_info.max_rx_buf_length + in get_new_skb()
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/openbmc/linux/drivers/net/ethernet/
H A Dethoc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
8 * Written by Thierry Reding <thierry.reding@avionic-design.de>
11 #include <linux/dma-mapping.h>
59 #define MODER_BRO (1 << 3) /* broadcast address */
60 #define MODER_IAM (1 << 4) /* individual address mode */
64 #define MODER_NBO (1 << 8) /* no back-off */
116 /* MII address register */
177 * struct ethoc - driver-private device structure
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/openbmc/u-boot/board/freescale/common/
H A Dcds_pci_ft.c1 // SPDX-License-Identifier: GPL-2.0+
26 map = fdt_getprop_w(blob, node, "interrupt-map", &len); in cds_pci_fixup()
28 /* Each item in "interrupt-map" property is translated with in cds_pci_fixup()
30 * PCI #address-cells, PCI #interrupt-cells, in cds_pci_fixup()
31 * PIC address, PIC #address-cells, PIC #interrupt-cells. in cds_pci_fixup()
33 cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1); in cds_pci_fixup()
34 cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1); in cds_pci_fixup()
39 piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL); in cds_pci_fixup()
43 piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL); in cds_pci_fixup()
59 map[3] = ((map[3] + slot - 2) % 4) + 1; in cds_pci_fixup()
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/openbmc/u-boot/drivers/qe/
H A Duec.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
21 /* Default UTBIPAR SMI address */
64 return -EINVAL; in uec_mac_enable()
66 uec_regs = uec->uec_regs; in uec_mac_enable()
68 maccfg1 = in_be32(&uec_regs->maccfg1); in uec_mac_enable()
72 out_be32(&uec_regs->maccfg1, maccfg1); in uec_mac_enable()
73 uec->mac_tx_enabled = 1; in uec_mac_enable()
78 out_be32(&uec_regs->maccfg1, maccfg1); in uec_mac_enable()
79 uec->mac_rx_enabled = 1; in uec_mac_enable()
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H A Duec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
35 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
37 #define UPSMR_CAM 0x00000400 /* CAM Address Matching */
38 #define UPSMR_BRO 0x00000200 /* Broadcast Address */
39 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
58 #define MACCFG2_PREL_SHIFT (31 - 19)
129 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
137 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
138 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
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/openbmc/u-boot/arch/arm/mach-zynqmp/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
87 if (!gd->bd->bi_dram[i].size) in mem_map_fill()
90 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; in mem_map_fill()
91 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; in mem_map_fill()
92 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; in mem_map_fill()
120 gd->arch.tlb_size = PGTABLE_SIZE; in reserve_mmu()
121 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; in reserve_mmu()
131 ver = readl(&csu_base->version); in zynqmp_get_silicon_version_secure()
143 gd->cpu_clk = get_tbclk(); in zynqmp_get_silicon_version()
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/openbmc/u-boot/arch/arm/mach-omap2/
H A Dfdt-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016-2017 Texas Instruments, Inc.
23 int ft_hs_disable_rng(void *fdt, bd_t *bd) in ft_hs_disable_rng() argument
48 * fdt_pack_reg - pack address and size array into the "reg"-suitable stream
50 static int fdt_pack_reg(const void *fdt, void *buf, u64 address, u64 size) in fdt_pack_reg() argument
57 *(fdt64_t *)p = cpu_to_fdt64(address); in fdt_pack_reg()
59 *(fdt32_t *)p = cpu_to_fdt32(address); in fdt_pack_reg()
68 return p - (char *)buf; in fdt_pack_reg()
71 int ft_hs_fixup_dram(void *fdt, bd_t *bd) in ft_hs_fixup_dram() argument
79 u8 temp[16]; /* Up to 64-bit address + 64-bit size */ in ft_hs_fixup_dram()
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/openbmc/linux/drivers/spi/
H A Dspi-pic32-sqi.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
87 #define PESQI_BDDONE BIT(9) /* BD processing complete */
94 #define PESQI_BDP_START BIT(2) /* start BD processor */
106 #define BD_CBD_INT_EN BIT(16) /* Current BD is processed */
117 #define BD_CS_DEASSERT BIT(30) /* de-assert CS after current BD */
118 #define BD_EN BIT(31) /* BD owned by H/W */
121 * struct ring_desc - Representation of SQI ring descriptor
123 * @bd: PESQI controller buffer descriptor
124 * @bd_dma: DMA address of PESQI controller buffer descriptor
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/openbmc/linux/arch/powerpc/boot/
H A Dcuboot-hotfoot.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for Esteem 195E Hotfoot CPU Board
5 * Author: Solomon Peachy <solomon@linux-wlan.com>
18 #include "ppcboot-hotfoot.h"
20 static bd_t bd; variable
28 dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); in hotfoot_fixups()
30 dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0); in hotfoot_fixups()
31 dt_fixup_clock("/plb", bd.bi_plb_busfreq); in hotfoot_fixups()
32 dt_fixup_clock("/plb/opb", bd.bi_opbfreq); in hotfoot_fixups()
33 dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq); in hotfoot_fixups()
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