183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
29f3183d2SMingkai Hu /*
3e809e747SPriyanka Jain * Copyright 2017 NXP
49f3183d2SMingkai Hu * Copyright 2014-2015 Freescale Semiconductor, Inc.
59f3183d2SMingkai Hu */
69f3183d2SMingkai Hu
79f3183d2SMingkai Hu #include <common.h>
83eace37eSSimon Glass #include <fsl_ddr_sdram.h>
99f3183d2SMingkai Hu #include <asm/io.h>
101221ce45SMasahiro Yamada #include <linux/errno.h>
119f3183d2SMingkai Hu #include <asm/system.h>
129cce5663SJoe Hershberger #include <fm_eth.h>
139f3183d2SMingkai Hu #include <asm/armv8/mmu.h>
149f3183d2SMingkai Hu #include <asm/io.h>
159f3183d2SMingkai Hu #include <asm/arch/fsl_serdes.h>
169f3183d2SMingkai Hu #include <asm/arch/soc.h>
179f3183d2SMingkai Hu #include <asm/arch/cpu.h>
189f3183d2SMingkai Hu #include <asm/arch/speed.h>
1963b2316cSAshish Kumar #include <fsl_immap.h>
209f3183d2SMingkai Hu #include <asm/arch/mp.h>
2178d57842SAlexander Graf #include <efi_loader.h>
229f3183d2SMingkai Hu #include <fsl-mc/fsl_mc.h>
239f3183d2SMingkai Hu #ifdef CONFIG_FSL_ESDHC
249f3183d2SMingkai Hu #include <fsl_esdhc.h>
259f3183d2SMingkai Hu #endif
26032d5bb4SHou Zhiqiang #include <asm/armv8/sec_firmware.h>
2702fb2761SShengzhou Liu #ifdef CONFIG_SYS_FSL_DDR
2802fb2761SShengzhou Liu #include <fsl_ddr.h>
2902fb2761SShengzhou Liu #endif
306e2941d7SSimon Glass #include <asm/arch/clock.h>
312db53cfeSPrabhakar Kushwaha #include <hwconfig.h>
3244262327SAhmed Mansour #include <fsl_qbman.h>
339f3183d2SMingkai Hu
344c417384SRajesh Bhagat #ifdef CONFIG_TFABOOT
354c417384SRajesh Bhagat #include <environment.h>
362141d250SPankit Garg #ifdef CONFIG_CHAIN_OF_TRUST
372141d250SPankit Garg #include <fsl_validate.h>
382141d250SPankit Garg #endif
394c417384SRajesh Bhagat #endif
404c417384SRajesh Bhagat
419f3183d2SMingkai Hu DECLARE_GLOBAL_DATA_PTR;
429f3183d2SMingkai Hu
43d171c707SYork Sun static struct cpu_type cpu_type_list[] = {
44d171c707SYork Sun CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
45d171c707SYork Sun CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
46d171c707SYork Sun CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
47d171c707SYork Sun CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
48d171c707SYork Sun CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
49d171c707SYork Sun CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
50d171c707SYork Sun CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
51d171c707SYork Sun CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
52d171c707SYork Sun CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
53d171c707SYork Sun CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
54ec88ff80SHou Zhiqiang CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
55d171c707SYork Sun CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
56ec88ff80SHou Zhiqiang CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
57d171c707SYork Sun CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
58d171c707SYork Sun CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
59d171c707SYork Sun CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
60d171c707SYork Sun CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
61d171c707SYork Sun CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
62d171c707SYork Sun CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
63d171c707SYork Sun CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
64d171c707SYork Sun CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
654909b89eSPriyanka Jain CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
664909b89eSPriyanka Jain CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
674909b89eSPriyanka Jain CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
68d171c707SYork Sun };
69d171c707SYork Sun
70d171c707SYork Sun #define EARLY_PGTABLE_SIZE 0x5000
71d171c707SYork Sun static struct mm_region early_map[] = {
72d171c707SYork Sun #ifdef CONFIG_FSL_LSCH3
73d171c707SYork Sun { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
74d171c707SYork Sun CONFIG_SYS_FSL_CCSR_SIZE,
75d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
76d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
77d171c707SYork Sun },
78d171c707SYork Sun { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
79d171c707SYork Sun SYS_FSL_OCRAM_SPACE_SIZE,
80d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
81d171c707SYork Sun },
82d171c707SYork Sun { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
83d171c707SYork Sun CONFIG_SYS_FSL_QSPI_SIZE1,
84d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
85d171c707SYork Sun #ifdef CONFIG_FSL_IFC
86d171c707SYork Sun /* For IFC Region #1, only the first 4MB is cache-enabled */
87d171c707SYork Sun { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
88d171c707SYork Sun CONFIG_SYS_FSL_IFC_SIZE1_1,
89d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
90d171c707SYork Sun },
91d171c707SYork Sun { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
92d171c707SYork Sun CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
93d171c707SYork Sun CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
94d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
95d171c707SYork Sun },
96d171c707SYork Sun { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
97d171c707SYork Sun CONFIG_SYS_FSL_IFC_SIZE1,
98d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
99d171c707SYork Sun },
100d171c707SYork Sun #endif
101d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
102d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE1,
103535d76a1SRajesh Bhagat #if defined(CONFIG_TFABOOT) || \
104535d76a1SRajesh Bhagat (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
105d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
106d171c707SYork Sun #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
107d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
108d171c707SYork Sun #endif
109d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
110d171c707SYork Sun },
111d171c707SYork Sun #ifdef CONFIG_FSL_IFC
112d171c707SYork Sun /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
113d171c707SYork Sun { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
114d171c707SYork Sun CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
115d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
116d171c707SYork Sun },
117d171c707SYork Sun #endif
118d171c707SYork Sun { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
119d171c707SYork Sun CONFIG_SYS_FSL_DCSR_SIZE,
120d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
121d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
122d171c707SYork Sun },
123d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
124d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE2,
125d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
126d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
127d171c707SYork Sun },
128d6fdec21SPriyanka Jain #ifdef CONFIG_SYS_FSL_DRAM_BASE3
129d6fdec21SPriyanka Jain { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
130d6fdec21SPriyanka Jain CONFIG_SYS_FSL_DRAM_SIZE3,
131d6fdec21SPriyanka Jain PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
132d6fdec21SPriyanka Jain PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
133d6fdec21SPriyanka Jain },
134d6fdec21SPriyanka Jain #endif
135d171c707SYork Sun #elif defined(CONFIG_FSL_LSCH2)
136d171c707SYork Sun { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
137d171c707SYork Sun CONFIG_SYS_FSL_CCSR_SIZE,
138d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
139d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
140d171c707SYork Sun },
141d171c707SYork Sun { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
142d171c707SYork Sun SYS_FSL_OCRAM_SPACE_SIZE,
143d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
144d171c707SYork Sun },
145d171c707SYork Sun { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
146d171c707SYork Sun CONFIG_SYS_FSL_DCSR_SIZE,
147d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
148d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
149d171c707SYork Sun },
150d171c707SYork Sun { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
151d171c707SYork Sun CONFIG_SYS_FSL_QSPI_SIZE,
152d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
153d171c707SYork Sun },
154d171c707SYork Sun #ifdef CONFIG_FSL_IFC
155d171c707SYork Sun { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
156d171c707SYork Sun CONFIG_SYS_FSL_IFC_SIZE,
157d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
158d171c707SYork Sun },
159d171c707SYork Sun #endif
160d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
161d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE1,
162535d76a1SRajesh Bhagat #if defined(CONFIG_TFABOOT) || \
163535d76a1SRajesh Bhagat (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
164d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
165d171c707SYork Sun #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
166d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
167d171c707SYork Sun #endif
168d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
169d171c707SYork Sun },
170d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
171d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE2,
172d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
173d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
174d171c707SYork Sun },
175d171c707SYork Sun #endif
176d171c707SYork Sun {}, /* list terminator */
177d171c707SYork Sun };
178d171c707SYork Sun
179d171c707SYork Sun static struct mm_region final_map[] = {
180d171c707SYork Sun #ifdef CONFIG_FSL_LSCH3
181d171c707SYork Sun { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
182d171c707SYork Sun CONFIG_SYS_FSL_CCSR_SIZE,
183d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
184d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
185d171c707SYork Sun },
186d171c707SYork Sun { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
187d171c707SYork Sun SYS_FSL_OCRAM_SPACE_SIZE,
188d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
189d171c707SYork Sun },
190d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
191d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE1,
192d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
193d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
194d171c707SYork Sun },
195d171c707SYork Sun { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
196d171c707SYork Sun CONFIG_SYS_FSL_QSPI_SIZE1,
197d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
198d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
199d171c707SYork Sun },
200d171c707SYork Sun { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
201d171c707SYork Sun CONFIG_SYS_FSL_QSPI_SIZE2,
202d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
203d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
204d171c707SYork Sun },
205d171c707SYork Sun #ifdef CONFIG_FSL_IFC
206d171c707SYork Sun { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
207d171c707SYork Sun CONFIG_SYS_FSL_IFC_SIZE2,
208d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
209d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
210d171c707SYork Sun },
211d171c707SYork Sun #endif
212d171c707SYork Sun { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
213d171c707SYork Sun CONFIG_SYS_FSL_DCSR_SIZE,
214d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
215d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
216d171c707SYork Sun },
217d171c707SYork Sun { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
218d171c707SYork Sun CONFIG_SYS_FSL_MC_SIZE,
219d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
220d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
221d171c707SYork Sun },
222d171c707SYork Sun { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
223d171c707SYork Sun CONFIG_SYS_FSL_NI_SIZE,
224d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
225d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
226d171c707SYork Sun },
227d171c707SYork Sun /* For QBMAN portal, only the first 64MB is cache-enabled */
228d171c707SYork Sun { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
229d171c707SYork Sun CONFIG_SYS_FSL_QBMAN_SIZE_1,
230d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
231d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
232d171c707SYork Sun },
233d171c707SYork Sun { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
234d171c707SYork Sun CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
235d171c707SYork Sun CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
236d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
237d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
238d171c707SYork Sun },
239d171c707SYork Sun { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
240d171c707SYork Sun CONFIG_SYS_PCIE1_PHYS_SIZE,
241d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
242d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
243d171c707SYork Sun },
244d171c707SYork Sun { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
245d171c707SYork Sun CONFIG_SYS_PCIE2_PHYS_SIZE,
246d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
247d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
248d171c707SYork Sun },
249d171c707SYork Sun { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
250d171c707SYork Sun CONFIG_SYS_PCIE3_PHYS_SIZE,
251d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
253d171c707SYork Sun },
2544909b89eSPriyanka Jain #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
255d171c707SYork Sun { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
256d171c707SYork Sun CONFIG_SYS_PCIE4_PHYS_SIZE,
257d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
258d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
259d171c707SYork Sun },
260d171c707SYork Sun #endif
261d171c707SYork Sun { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
262d171c707SYork Sun CONFIG_SYS_FSL_WRIOP1_SIZE,
263d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
264d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
265d171c707SYork Sun },
266d171c707SYork Sun { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
267d171c707SYork Sun CONFIG_SYS_FSL_AIOP1_SIZE,
268d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
269d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
270d171c707SYork Sun },
271d171c707SYork Sun { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
272d171c707SYork Sun CONFIG_SYS_FSL_PEBUF_SIZE,
273d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
274d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
275d171c707SYork Sun },
276d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
277d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE2,
278d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
279d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
280d171c707SYork Sun },
281d6fdec21SPriyanka Jain #ifdef CONFIG_SYS_FSL_DRAM_BASE3
282d6fdec21SPriyanka Jain { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
283d6fdec21SPriyanka Jain CONFIG_SYS_FSL_DRAM_SIZE3,
284d6fdec21SPriyanka Jain PTE_BLOCK_MEMTYPE(MT_NORMAL) |
285d6fdec21SPriyanka Jain PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
286d6fdec21SPriyanka Jain },
287d6fdec21SPriyanka Jain #endif
288d171c707SYork Sun #elif defined(CONFIG_FSL_LSCH2)
289d171c707SYork Sun { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
290d171c707SYork Sun CONFIG_SYS_FSL_BOOTROM_SIZE,
291d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
292d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
293d171c707SYork Sun },
294d171c707SYork Sun { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
295d171c707SYork Sun CONFIG_SYS_FSL_CCSR_SIZE,
296d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
297d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
298d171c707SYork Sun },
299d171c707SYork Sun { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
300d171c707SYork Sun SYS_FSL_OCRAM_SPACE_SIZE,
301d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
302d171c707SYork Sun },
303d171c707SYork Sun { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
304d171c707SYork Sun CONFIG_SYS_FSL_DCSR_SIZE,
305d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
306d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
307d171c707SYork Sun },
308d171c707SYork Sun { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
309d171c707SYork Sun CONFIG_SYS_FSL_QSPI_SIZE,
310d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
311d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
312d171c707SYork Sun },
313d171c707SYork Sun #ifdef CONFIG_FSL_IFC
314d171c707SYork Sun { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
315d171c707SYork Sun CONFIG_SYS_FSL_IFC_SIZE,
316d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
317d171c707SYork Sun },
318d171c707SYork Sun #endif
319d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
320d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE1,
321d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
322d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
323d171c707SYork Sun },
324d171c707SYork Sun { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
325d171c707SYork Sun CONFIG_SYS_FSL_QBMAN_SIZE,
326d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
327d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
328d171c707SYork Sun },
329d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
330d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE2,
331d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
332d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
333d171c707SYork Sun },
334d171c707SYork Sun { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
335d171c707SYork Sun CONFIG_SYS_PCIE1_PHYS_SIZE,
336d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
337d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
338d171c707SYork Sun },
339d171c707SYork Sun { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
340d171c707SYork Sun CONFIG_SYS_PCIE2_PHYS_SIZE,
341d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
342d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
343d171c707SYork Sun },
344d171c707SYork Sun { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
345d171c707SYork Sun CONFIG_SYS_PCIE3_PHYS_SIZE,
346d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
347d171c707SYork Sun PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
348d171c707SYork Sun },
349d171c707SYork Sun { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
350d171c707SYork Sun CONFIG_SYS_FSL_DRAM_SIZE3,
351d171c707SYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
352d171c707SYork Sun PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
353d171c707SYork Sun },
354d171c707SYork Sun #endif
355d171c707SYork Sun #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
356d171c707SYork Sun {}, /* space holder for secure mem */
357d171c707SYork Sun #endif
358d171c707SYork Sun {},
359d171c707SYork Sun };
360d171c707SYork Sun
3615ad5823dSYork Sun struct mm_region *mem_map = early_map;
3627985cdf7SAlexander Graf
cpu_name(char * name)3639f3183d2SMingkai Hu void cpu_name(char *name)
3649f3183d2SMingkai Hu {
3659f3183d2SMingkai Hu struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
3669f3183d2SMingkai Hu unsigned int i, svr, ver;
3679f3183d2SMingkai Hu
3689f3183d2SMingkai Hu svr = gur_in32(&gur->svr);
3699f3183d2SMingkai Hu ver = SVR_SOC_VER(svr);
3709f3183d2SMingkai Hu
3719f3183d2SMingkai Hu for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
3729f3183d2SMingkai Hu if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
3739f3183d2SMingkai Hu strcpy(name, cpu_type_list[i].name);
3744909b89eSPriyanka Jain #ifdef CONFIG_ARCH_LX2160A
3754909b89eSPriyanka Jain if (IS_C_PROCESSOR(svr))
3764909b89eSPriyanka Jain strcat(name, "C");
3774909b89eSPriyanka Jain #endif
3789f3183d2SMingkai Hu
3799f3183d2SMingkai Hu if (IS_E_PROCESSOR(svr))
3809f3183d2SMingkai Hu strcat(name, "E");
3815d1a7a9dSWenbin Song
3825d1a7a9dSWenbin Song sprintf(name + strlen(name), " Rev%d.%d",
3835d1a7a9dSWenbin Song SVR_MAJ(svr), SVR_MIN(svr));
3849f3183d2SMingkai Hu break;
3859f3183d2SMingkai Hu }
3869f3183d2SMingkai Hu
3879f3183d2SMingkai Hu if (i == ARRAY_SIZE(cpu_type_list))
3889f3183d2SMingkai Hu strcpy(name, "unknown");
3899f3183d2SMingkai Hu }
3909f3183d2SMingkai Hu
3919f3183d2SMingkai Hu #ifndef CONFIG_SYS_DCACHE_OFF
3929f3183d2SMingkai Hu /*
3939f3183d2SMingkai Hu * To start MMU before DDR is available, we create MMU table in SRAM.
3949f3183d2SMingkai Hu * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
3959f3183d2SMingkai Hu * levels of translation tables here to cover 40-bit address space.
3969f3183d2SMingkai Hu * We use 4KB granule size, with 40 bits physical address, T0SZ=24
3975ad5823dSYork Sun * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
3985ad5823dSYork Sun * Note, the debug print in cache_v8.c is not usable for debugging
3995ad5823dSYork Sun * these early MMU tables because UART is not yet available.
4009f3183d2SMingkai Hu */
early_mmu_setup(void)4019f3183d2SMingkai Hu static inline void early_mmu_setup(void)
4029f3183d2SMingkai Hu {
4035ad5823dSYork Sun unsigned int el = current_el();
4049f3183d2SMingkai Hu
4055ad5823dSYork Sun /* global data is already setup, no allocation yet */
406e3506480SPankit Garg if (el == 3)
4075ad5823dSYork Sun gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
408e3506480SPankit Garg else
409e3506480SPankit Garg gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
4105ad5823dSYork Sun gd->arch.tlb_fillptr = gd->arch.tlb_addr;
4115ad5823dSYork Sun gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
4129f3183d2SMingkai Hu
4135ad5823dSYork Sun /* Create early page tables */
4145ad5823dSYork Sun setup_pgtables();
4159f3183d2SMingkai Hu
4165ad5823dSYork Sun /* point TTBR to the new table */
4175ad5823dSYork Sun set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
4185ad5823dSYork Sun get_tcr(el, NULL, NULL) &
4195ad5823dSYork Sun ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
4209f3183d2SMingkai Hu MEMORY_ATTRIBUTES);
4215ad5823dSYork Sun
4229f3183d2SMingkai Hu set_sctlr(get_sctlr() | CR_M);
4239f3183d2SMingkai Hu }
4249f3183d2SMingkai Hu
fix_pcie_mmu_map(void)4253d8553f0SHou Zhiqiang static void fix_pcie_mmu_map(void)
4263d8553f0SHou Zhiqiang {
4274a3ab193SYork Sun #ifdef CONFIG_ARCH_LS2080A
4283d8553f0SHou Zhiqiang unsigned int i;
4293d8553f0SHou Zhiqiang u32 svr, ver;
4303d8553f0SHou Zhiqiang struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
4313d8553f0SHou Zhiqiang
4323d8553f0SHou Zhiqiang svr = gur_in32(&gur->svr);
4333d8553f0SHou Zhiqiang ver = SVR_SOC_VER(svr);
4343d8553f0SHou Zhiqiang
4353d8553f0SHou Zhiqiang /* Fix PCIE base and size for LS2088A */
4363d8553f0SHou Zhiqiang if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
437e809e747SPriyanka Jain (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
438e809e747SPriyanka Jain (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
4393d8553f0SHou Zhiqiang for (i = 0; i < ARRAY_SIZE(final_map); i++) {
4403d8553f0SHou Zhiqiang switch (final_map[i].phys) {
4413d8553f0SHou Zhiqiang case CONFIG_SYS_PCIE1_PHYS_ADDR:
4423d8553f0SHou Zhiqiang final_map[i].phys = 0x2000000000ULL;
4433d8553f0SHou Zhiqiang final_map[i].virt = 0x2000000000ULL;
4443d8553f0SHou Zhiqiang final_map[i].size = 0x800000000ULL;
4453d8553f0SHou Zhiqiang break;
4463d8553f0SHou Zhiqiang case CONFIG_SYS_PCIE2_PHYS_ADDR:
4473d8553f0SHou Zhiqiang final_map[i].phys = 0x2800000000ULL;
4483d8553f0SHou Zhiqiang final_map[i].virt = 0x2800000000ULL;
4493d8553f0SHou Zhiqiang final_map[i].size = 0x800000000ULL;
4503d8553f0SHou Zhiqiang break;
4513d8553f0SHou Zhiqiang case CONFIG_SYS_PCIE3_PHYS_ADDR:
4523d8553f0SHou Zhiqiang final_map[i].phys = 0x3000000000ULL;
4533d8553f0SHou Zhiqiang final_map[i].virt = 0x3000000000ULL;
4543d8553f0SHou Zhiqiang final_map[i].size = 0x800000000ULL;
4553d8553f0SHou Zhiqiang break;
4563d8553f0SHou Zhiqiang case CONFIG_SYS_PCIE4_PHYS_ADDR:
4573d8553f0SHou Zhiqiang final_map[i].phys = 0x3800000000ULL;
4583d8553f0SHou Zhiqiang final_map[i].virt = 0x3800000000ULL;
4593d8553f0SHou Zhiqiang final_map[i].size = 0x800000000ULL;
4603d8553f0SHou Zhiqiang break;
4613d8553f0SHou Zhiqiang default:
4623d8553f0SHou Zhiqiang break;
4633d8553f0SHou Zhiqiang }
4643d8553f0SHou Zhiqiang }
4653d8553f0SHou Zhiqiang }
4663d8553f0SHou Zhiqiang #endif
4673d8553f0SHou Zhiqiang }
4683d8553f0SHou Zhiqiang
4699f3183d2SMingkai Hu /*
4709f3183d2SMingkai Hu * The final tables look similar to early tables, but different in detail.
4719f3183d2SMingkai Hu * These tables are in DRAM. Sub tables are added to enable cache for
4729f3183d2SMingkai Hu * QBMan and OCRAM.
4739f3183d2SMingkai Hu *
474e61a7534SYork Sun * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
475e61a7534SYork Sun * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
4769f3183d2SMingkai Hu */
final_mmu_setup(void)4779f3183d2SMingkai Hu static inline void final_mmu_setup(void)
4789f3183d2SMingkai Hu {
4795ad5823dSYork Sun u64 tlb_addr_save = gd->arch.tlb_addr;
480c107c0c0SYork Sun unsigned int el = current_el();
4815ad5823dSYork Sun int index;
4825ad5823dSYork Sun
4833d8553f0SHou Zhiqiang /* fix the final_map before filling in the block entries */
4843d8553f0SHou Zhiqiang fix_pcie_mmu_map();
4853d8553f0SHou Zhiqiang
4865ad5823dSYork Sun mem_map = final_map;
487c107c0c0SYork Sun
48824f55496SYork Sun /* Update mapping for DDR to actual size */
48924f55496SYork Sun for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
49024f55496SYork Sun /*
49124f55496SYork Sun * Find the entry for DDR mapping and update the address and
49224f55496SYork Sun * size. Zero-sized mapping will be skipped when creating MMU
49324f55496SYork Sun * table.
49424f55496SYork Sun */
49524f55496SYork Sun switch (final_map[index].virt) {
49624f55496SYork Sun case CONFIG_SYS_FSL_DRAM_BASE1:
49724f55496SYork Sun final_map[index].virt = gd->bd->bi_dram[0].start;
49824f55496SYork Sun final_map[index].phys = gd->bd->bi_dram[0].start;
49924f55496SYork Sun final_map[index].size = gd->bd->bi_dram[0].size;
50024f55496SYork Sun break;
50124f55496SYork Sun #ifdef CONFIG_SYS_FSL_DRAM_BASE2
50224f55496SYork Sun case CONFIG_SYS_FSL_DRAM_BASE2:
50324f55496SYork Sun #if (CONFIG_NR_DRAM_BANKS >= 2)
50424f55496SYork Sun final_map[index].virt = gd->bd->bi_dram[1].start;
50524f55496SYork Sun final_map[index].phys = gd->bd->bi_dram[1].start;
50624f55496SYork Sun final_map[index].size = gd->bd->bi_dram[1].size;
50724f55496SYork Sun #else
50824f55496SYork Sun final_map[index].size = 0;
50924f55496SYork Sun #endif
51024f55496SYork Sun break;
51124f55496SYork Sun #endif
51224f55496SYork Sun #ifdef CONFIG_SYS_FSL_DRAM_BASE3
51324f55496SYork Sun case CONFIG_SYS_FSL_DRAM_BASE3:
51424f55496SYork Sun #if (CONFIG_NR_DRAM_BANKS >= 3)
51524f55496SYork Sun final_map[index].virt = gd->bd->bi_dram[2].start;
51624f55496SYork Sun final_map[index].phys = gd->bd->bi_dram[2].start;
51724f55496SYork Sun final_map[index].size = gd->bd->bi_dram[2].size;
51824f55496SYork Sun #else
51924f55496SYork Sun final_map[index].size = 0;
52024f55496SYork Sun #endif
52124f55496SYork Sun break;
52224f55496SYork Sun #endif
52324f55496SYork Sun default:
52424f55496SYork Sun break;
52524f55496SYork Sun }
52624f55496SYork Sun }
52724f55496SYork Sun
528c107c0c0SYork Sun #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
5295ad5823dSYork Sun if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
530c107c0c0SYork Sun if (el == 3) {
531c107c0c0SYork Sun /*
5325ad5823dSYork Sun * Only use gd->arch.secure_ram if the address is
5335ad5823dSYork Sun * recalculated. Align to 4KB for MMU table.
534c107c0c0SYork Sun */
5355ad5823dSYork Sun /* put page tables in secure ram */
5365ad5823dSYork Sun index = ARRAY_SIZE(final_map) - 2;
5375ad5823dSYork Sun gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
5385ad5823dSYork Sun final_map[index].virt = gd->arch.secure_ram & ~0x3;
5395ad5823dSYork Sun final_map[index].phys = final_map[index].virt;
5405ad5823dSYork Sun final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
5415ad5823dSYork Sun final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
542e61a7534SYork Sun gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
5435ad5823dSYork Sun tlb_addr_save = gd->arch.tlb_addr;
544c107c0c0SYork Sun } else {
5455ad5823dSYork Sun /* Use allocated (board_f.c) memory for TLB */
5465ad5823dSYork Sun tlb_addr_save = gd->arch.tlb_allocated;
5475ad5823dSYork Sun gd->arch.tlb_addr = tlb_addr_save;
548c107c0c0SYork Sun }
549c107c0c0SYork Sun }
550c107c0c0SYork Sun #endif
5519f3183d2SMingkai Hu
5525ad5823dSYork Sun /* Reset the fill ptr */
5535ad5823dSYork Sun gd->arch.tlb_fillptr = tlb_addr_save;
5545ad5823dSYork Sun
5555ad5823dSYork Sun /* Create normal system page tables */
5565ad5823dSYork Sun setup_pgtables();
5575ad5823dSYork Sun
5585ad5823dSYork Sun /* Create emergency page tables */
5595ad5823dSYork Sun gd->arch.tlb_addr = gd->arch.tlb_fillptr;
5605ad5823dSYork Sun gd->arch.tlb_emerg = gd->arch.tlb_addr;
5615ad5823dSYork Sun setup_pgtables();
5625ad5823dSYork Sun gd->arch.tlb_addr = tlb_addr_save;
5635ad5823dSYork Sun
564a045a0c3SYork Sun /* Disable cache and MMU */
565a045a0c3SYork Sun dcache_disable(); /* TLBs are invalidated */
566a045a0c3SYork Sun invalidate_icache_all();
5679f3183d2SMingkai Hu
5689f3183d2SMingkai Hu /* point TTBR to the new table */
5695ad5823dSYork Sun set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
5709f3183d2SMingkai Hu MEMORY_ATTRIBUTES);
571a045a0c3SYork Sun
572ed7a3943SYork Sun set_sctlr(get_sctlr() | CR_M);
5739f3183d2SMingkai Hu }
5749f3183d2SMingkai Hu
get_page_table_size(void)575c05016abSAlexander Graf u64 get_page_table_size(void)
576c05016abSAlexander Graf {
577c05016abSAlexander Graf return 0x10000;
578c05016abSAlexander Graf }
579c05016abSAlexander Graf
arch_cpu_init(void)5809f3183d2SMingkai Hu int arch_cpu_init(void)
5819f3183d2SMingkai Hu {
582399e2bb6SYork Sun /*
583399e2bb6SYork Sun * This function is called before U-Boot relocates itself to speed up
584399e2bb6SYork Sun * on system running. It is not necessary to run if performance is not
585399e2bb6SYork Sun * critical. Skip if MMU is already enabled by SPL or other means.
586399e2bb6SYork Sun */
587399e2bb6SYork Sun if (get_sctlr() & CR_M)
588399e2bb6SYork Sun return 0;
589399e2bb6SYork Sun
5909f3183d2SMingkai Hu icache_enable();
5919f3183d2SMingkai Hu __asm_invalidate_dcache_all();
5929f3183d2SMingkai Hu __asm_invalidate_tlb_all();
5939f3183d2SMingkai Hu early_mmu_setup();
5949f3183d2SMingkai Hu set_sctlr(get_sctlr() | CR_C);
5959f3183d2SMingkai Hu return 0;
5969f3183d2SMingkai Hu }
5979f3183d2SMingkai Hu
mmu_setup(void)59885cdf38eSHou Zhiqiang void mmu_setup(void)
59985cdf38eSHou Zhiqiang {
60085cdf38eSHou Zhiqiang final_mmu_setup();
60185cdf38eSHou Zhiqiang }
60285cdf38eSHou Zhiqiang
6039f3183d2SMingkai Hu /*
60485cdf38eSHou Zhiqiang * This function is called from common/board_r.c.
60585cdf38eSHou Zhiqiang * It recreates MMU table in main memory.
6069f3183d2SMingkai Hu */
enable_caches(void)6079f3183d2SMingkai Hu void enable_caches(void)
6089f3183d2SMingkai Hu {
60985cdf38eSHou Zhiqiang mmu_setup();
6109f3183d2SMingkai Hu __asm_invalidate_tlb_all();
61185cdf38eSHou Zhiqiang icache_enable();
61285cdf38eSHou Zhiqiang dcache_enable();
6139f3183d2SMingkai Hu }
6144c417384SRajesh Bhagat #endif /* CONFIG_SYS_DCACHE_OFF */
6154c417384SRajesh Bhagat
6164c417384SRajesh Bhagat #ifdef CONFIG_TFABOOT
__get_boot_src(u32 porsr1)6174c417384SRajesh Bhagat enum boot_src __get_boot_src(u32 porsr1)
6184c417384SRajesh Bhagat {
6194c417384SRajesh Bhagat enum boot_src src = BOOT_SOURCE_RESERVED;
6204c417384SRajesh Bhagat u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
621d6fdec21SPriyanka Jain #if !defined(CONFIG_NXP_LSCH3_2)
6224c417384SRajesh Bhagat u32 val;
6239f3183d2SMingkai Hu #endif
6244c417384SRajesh Bhagat debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
6254c417384SRajesh Bhagat
6264c417384SRajesh Bhagat #if defined(CONFIG_FSL_LSCH3)
627d6fdec21SPriyanka Jain #if defined(CONFIG_NXP_LSCH3_2)
6284c417384SRajesh Bhagat switch (rcw_src) {
6294c417384SRajesh Bhagat case RCW_SRC_SDHC1_VAL:
6304c417384SRajesh Bhagat src = BOOT_SOURCE_SD_MMC;
6314c417384SRajesh Bhagat break;
6324c417384SRajesh Bhagat case RCW_SRC_SDHC2_VAL:
6334c417384SRajesh Bhagat src = BOOT_SOURCE_SD_MMC2;
6344c417384SRajesh Bhagat break;
6354c417384SRajesh Bhagat case RCW_SRC_I2C1_VAL:
6364c417384SRajesh Bhagat src = BOOT_SOURCE_I2C1_EXTENDED;
6374c417384SRajesh Bhagat break;
6384c417384SRajesh Bhagat case RCW_SRC_FLEXSPI_NAND2K_VAL:
6394c417384SRajesh Bhagat src = BOOT_SOURCE_XSPI_NAND;
6404c417384SRajesh Bhagat break;
6414c417384SRajesh Bhagat case RCW_SRC_FLEXSPI_NAND4K_VAL:
6424c417384SRajesh Bhagat src = BOOT_SOURCE_XSPI_NAND;
6434c417384SRajesh Bhagat break;
6444c417384SRajesh Bhagat case RCW_SRC_RESERVED_1_VAL:
6454c417384SRajesh Bhagat src = BOOT_SOURCE_RESERVED;
6464c417384SRajesh Bhagat break;
6474c417384SRajesh Bhagat case RCW_SRC_FLEXSPI_NOR_24B:
6484c417384SRajesh Bhagat src = BOOT_SOURCE_XSPI_NOR;
6494c417384SRajesh Bhagat break;
6504c417384SRajesh Bhagat default:
6514c417384SRajesh Bhagat src = BOOT_SOURCE_RESERVED;
6524c417384SRajesh Bhagat }
6534c417384SRajesh Bhagat #else
6544c417384SRajesh Bhagat val = rcw_src & RCW_SRC_TYPE_MASK;
6554c417384SRajesh Bhagat if (val == RCW_SRC_NOR_VAL) {
6564c417384SRajesh Bhagat val = rcw_src & NOR_TYPE_MASK;
6574c417384SRajesh Bhagat
6584c417384SRajesh Bhagat switch (val) {
6594c417384SRajesh Bhagat case NOR_16B_VAL:
6604c417384SRajesh Bhagat case NOR_32B_VAL:
6614c417384SRajesh Bhagat src = BOOT_SOURCE_IFC_NOR;
6624c417384SRajesh Bhagat break;
6634c417384SRajesh Bhagat default:
6644c417384SRajesh Bhagat src = BOOT_SOURCE_RESERVED;
6654c417384SRajesh Bhagat }
6664c417384SRajesh Bhagat } else {
6674c417384SRajesh Bhagat /* RCW SRC Serial Flash */
6684c417384SRajesh Bhagat val = rcw_src & RCW_SRC_SERIAL_MASK;
6694c417384SRajesh Bhagat switch (val) {
6704c417384SRajesh Bhagat case RCW_SRC_QSPI_VAL:
6714c417384SRajesh Bhagat /* RCW SRC Serial NOR (QSPI) */
6724c417384SRajesh Bhagat src = BOOT_SOURCE_QSPI_NOR;
6734c417384SRajesh Bhagat break;
6744c417384SRajesh Bhagat case RCW_SRC_SD_CARD_VAL:
6754c417384SRajesh Bhagat /* RCW SRC SD Card */
6764c417384SRajesh Bhagat src = BOOT_SOURCE_SD_MMC;
6774c417384SRajesh Bhagat break;
6784c417384SRajesh Bhagat case RCW_SRC_EMMC_VAL:
6794c417384SRajesh Bhagat /* RCW SRC EMMC */
680d23da2aeSRajesh Bhagat src = BOOT_SOURCE_SD_MMC;
6814c417384SRajesh Bhagat break;
6824c417384SRajesh Bhagat case RCW_SRC_I2C1_VAL:
6834c417384SRajesh Bhagat /* RCW SRC I2C1 Extended */
6844c417384SRajesh Bhagat src = BOOT_SOURCE_I2C1_EXTENDED;
6854c417384SRajesh Bhagat break;
6864c417384SRajesh Bhagat default:
6874c417384SRajesh Bhagat src = BOOT_SOURCE_RESERVED;
6884c417384SRajesh Bhagat }
6894c417384SRajesh Bhagat }
6904c417384SRajesh Bhagat #endif
6914c417384SRajesh Bhagat #elif defined(CONFIG_FSL_LSCH2)
6924c417384SRajesh Bhagat /* RCW SRC NAND */
6934c417384SRajesh Bhagat val = rcw_src & RCW_SRC_NAND_MASK;
6944c417384SRajesh Bhagat if (val == RCW_SRC_NAND_VAL) {
6954c417384SRajesh Bhagat val = rcw_src & NAND_RESERVED_MASK;
6964c417384SRajesh Bhagat if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
6974c417384SRajesh Bhagat src = BOOT_SOURCE_IFC_NAND;
6984c417384SRajesh Bhagat
6994c417384SRajesh Bhagat } else {
7004c417384SRajesh Bhagat /* RCW SRC NOR */
7014c417384SRajesh Bhagat val = rcw_src & RCW_SRC_NOR_MASK;
7024c417384SRajesh Bhagat if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
7034c417384SRajesh Bhagat src = BOOT_SOURCE_IFC_NOR;
7044c417384SRajesh Bhagat } else {
7054c417384SRajesh Bhagat switch (rcw_src) {
7064c417384SRajesh Bhagat case QSPI_VAL1:
7074c417384SRajesh Bhagat case QSPI_VAL2:
7084c417384SRajesh Bhagat src = BOOT_SOURCE_QSPI_NOR;
7094c417384SRajesh Bhagat break;
7104c417384SRajesh Bhagat case SD_VAL:
7114c417384SRajesh Bhagat src = BOOT_SOURCE_SD_MMC;
7124c417384SRajesh Bhagat break;
7134c417384SRajesh Bhagat default:
7144c417384SRajesh Bhagat src = BOOT_SOURCE_RESERVED;
7154c417384SRajesh Bhagat }
7164c417384SRajesh Bhagat }
7174c417384SRajesh Bhagat }
7184c417384SRajesh Bhagat #endif
71956db948bSYork Sun
72056db948bSYork Sun if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
72156db948bSYork Sun src = BOOT_SOURCE_QSPI_NOR;
72256db948bSYork Sun
7234c417384SRajesh Bhagat debug("%s: src 0x%x\n", __func__, src);
7244c417384SRajesh Bhagat return src;
7254c417384SRajesh Bhagat }
7264c417384SRajesh Bhagat
get_boot_src(void)7274c417384SRajesh Bhagat enum boot_src get_boot_src(void)
7284c417384SRajesh Bhagat {
72956db948bSYork Sun struct pt_regs regs;
73056db948bSYork Sun u32 porsr1 = 0;
7314c417384SRajesh Bhagat
7324c417384SRajesh Bhagat #if defined(CONFIG_FSL_LSCH3)
7334c417384SRajesh Bhagat u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
7344c417384SRajesh Bhagat #elif defined(CONFIG_FSL_LSCH2)
7354c417384SRajesh Bhagat struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
73656db948bSYork Sun #endif
7374c417384SRajesh Bhagat
73856db948bSYork Sun if (current_el() == 2) {
73956db948bSYork Sun regs.regs[0] = SIP_SVC_RCW;
74056db948bSYork Sun
74156db948bSYork Sun smc_call(®s);
74256db948bSYork Sun if (!regs.regs[0])
74356db948bSYork Sun porsr1 = regs.regs[1];
74456db948bSYork Sun }
74556db948bSYork Sun
74656db948bSYork Sun if (current_el() == 3 || !porsr1) {
74756db948bSYork Sun #ifdef CONFIG_FSL_LSCH3
74856db948bSYork Sun porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
74956db948bSYork Sun #elif defined(CONFIG_FSL_LSCH2)
7504c417384SRajesh Bhagat porsr1 = in_be32(&gur->porsr1);
7514c417384SRajesh Bhagat #endif
75256db948bSYork Sun }
75356db948bSYork Sun
7544c417384SRajesh Bhagat debug("%s: porsr1 0x%x\n", __func__, porsr1);
7554c417384SRajesh Bhagat
7564c417384SRajesh Bhagat return __get_boot_src(porsr1);
7574c417384SRajesh Bhagat }
7584c417384SRajesh Bhagat
7594c417384SRajesh Bhagat #ifdef CONFIG_ENV_IS_IN_MMC
mmc_get_env_dev(void)7604c417384SRajesh Bhagat int mmc_get_env_dev(void)
7614c417384SRajesh Bhagat {
7624c417384SRajesh Bhagat enum boot_src src = get_boot_src();
7634c417384SRajesh Bhagat int dev = CONFIG_SYS_MMC_ENV_DEV;
7644c417384SRajesh Bhagat
7654c417384SRajesh Bhagat switch (src) {
7664c417384SRajesh Bhagat case BOOT_SOURCE_SD_MMC:
7674c417384SRajesh Bhagat dev = 0;
7684c417384SRajesh Bhagat break;
7694c417384SRajesh Bhagat case BOOT_SOURCE_SD_MMC2:
7704c417384SRajesh Bhagat dev = 1;
7714c417384SRajesh Bhagat break;
7724c417384SRajesh Bhagat default:
7734c417384SRajesh Bhagat break;
7744c417384SRajesh Bhagat }
7754c417384SRajesh Bhagat
7764c417384SRajesh Bhagat return dev;
7774c417384SRajesh Bhagat }
7784c417384SRajesh Bhagat #endif
7794c417384SRajesh Bhagat
env_get_location(enum env_operation op,int prio)7804c417384SRajesh Bhagat enum env_location env_get_location(enum env_operation op, int prio)
7814c417384SRajesh Bhagat {
7824c417384SRajesh Bhagat enum boot_src src = get_boot_src();
7834c417384SRajesh Bhagat enum env_location env_loc = ENVL_NOWHERE;
7844c417384SRajesh Bhagat
7854c417384SRajesh Bhagat if (prio)
7864c417384SRajesh Bhagat return ENVL_UNKNOWN;
7874c417384SRajesh Bhagat
7882141d250SPankit Garg #ifdef CONFIG_CHAIN_OF_TRUST
7892141d250SPankit Garg /* Check Boot Mode
7902141d250SPankit Garg * If Boot Mode is Secure, return ENVL_NOWHERE
7912141d250SPankit Garg */
7922141d250SPankit Garg if (fsl_check_boot_mode_secure() == 1)
7932141d250SPankit Garg goto done;
7942141d250SPankit Garg #endif
7952141d250SPankit Garg
7964c417384SRajesh Bhagat switch (src) {
7974c417384SRajesh Bhagat case BOOT_SOURCE_IFC_NOR:
7984c417384SRajesh Bhagat env_loc = ENVL_FLASH;
7994c417384SRajesh Bhagat break;
8004c417384SRajesh Bhagat case BOOT_SOURCE_QSPI_NOR:
8014c417384SRajesh Bhagat /* FALLTHROUGH */
8024c417384SRajesh Bhagat case BOOT_SOURCE_XSPI_NOR:
8034c417384SRajesh Bhagat env_loc = ENVL_SPI_FLASH;
8044c417384SRajesh Bhagat break;
8054c417384SRajesh Bhagat case BOOT_SOURCE_IFC_NAND:
8064c417384SRajesh Bhagat /* FALLTHROUGH */
8074c417384SRajesh Bhagat case BOOT_SOURCE_QSPI_NAND:
8084c417384SRajesh Bhagat /* FALLTHROUGH */
8094c417384SRajesh Bhagat case BOOT_SOURCE_XSPI_NAND:
8104c417384SRajesh Bhagat env_loc = ENVL_NAND;
8114c417384SRajesh Bhagat break;
8124c417384SRajesh Bhagat case BOOT_SOURCE_SD_MMC:
8134c417384SRajesh Bhagat /* FALLTHROUGH */
8144c417384SRajesh Bhagat case BOOT_SOURCE_SD_MMC2:
8154c417384SRajesh Bhagat env_loc = ENVL_MMC;
8164c417384SRajesh Bhagat break;
8174c417384SRajesh Bhagat case BOOT_SOURCE_I2C1_EXTENDED:
8184c417384SRajesh Bhagat /* FALLTHROUGH */
8194c417384SRajesh Bhagat default:
8204c417384SRajesh Bhagat break;
8214c417384SRajesh Bhagat }
8224c417384SRajesh Bhagat
8232141d250SPankit Garg #ifdef CONFIG_CHAIN_OF_TRUST
8242141d250SPankit Garg done:
8252141d250SPankit Garg #endif
8264c417384SRajesh Bhagat return env_loc;
8274c417384SRajesh Bhagat }
8284c417384SRajesh Bhagat #endif /* CONFIG_TFABOOT */
8299f3183d2SMingkai Hu
initiator_type(u32 cluster,int init_id)830e87c673cSPriyanka Jain u32 initiator_type(u32 cluster, int init_id)
8319f3183d2SMingkai Hu {
8329f3183d2SMingkai Hu struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
8339f3183d2SMingkai Hu u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
8349f3183d2SMingkai Hu u32 type = 0;
8359f3183d2SMingkai Hu
8369f3183d2SMingkai Hu type = gur_in32(&gur->tp_ityp[idx]);
8379f3183d2SMingkai Hu if (type & TP_ITYP_AV)
8389f3183d2SMingkai Hu return type;
8399f3183d2SMingkai Hu
8409f3183d2SMingkai Hu return 0;
8419f3183d2SMingkai Hu }
8429f3183d2SMingkai Hu
cpu_pos_mask(void)843ef9a5fd8SYork Sun u32 cpu_pos_mask(void)
844ef9a5fd8SYork Sun {
845ef9a5fd8SYork Sun struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
846ef9a5fd8SYork Sun int i = 0;
847ef9a5fd8SYork Sun u32 cluster, type, mask = 0;
848ef9a5fd8SYork Sun
849ef9a5fd8SYork Sun do {
850ef9a5fd8SYork Sun int j;
851ef9a5fd8SYork Sun
852ef9a5fd8SYork Sun cluster = gur_in32(&gur->tp_cluster[i].lower);
853ef9a5fd8SYork Sun for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
854ef9a5fd8SYork Sun type = initiator_type(cluster, j);
855ef9a5fd8SYork Sun if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
856ef9a5fd8SYork Sun mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
857ef9a5fd8SYork Sun }
858ef9a5fd8SYork Sun i++;
859ef9a5fd8SYork Sun } while ((cluster & TP_CLUSTER_EOC) == 0x0);
860ef9a5fd8SYork Sun
861ef9a5fd8SYork Sun return mask;
862ef9a5fd8SYork Sun }
863ef9a5fd8SYork Sun
cpu_mask(void)8649f3183d2SMingkai Hu u32 cpu_mask(void)
8659f3183d2SMingkai Hu {
8669f3183d2SMingkai Hu struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
8679f3183d2SMingkai Hu int i = 0, count = 0;
8689f3183d2SMingkai Hu u32 cluster, type, mask = 0;
8699f3183d2SMingkai Hu
8709f3183d2SMingkai Hu do {
8719f3183d2SMingkai Hu int j;
8729f3183d2SMingkai Hu
8739f3183d2SMingkai Hu cluster = gur_in32(&gur->tp_cluster[i].lower);
8749f3183d2SMingkai Hu for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
8759f3183d2SMingkai Hu type = initiator_type(cluster, j);
8769f3183d2SMingkai Hu if (type) {
8779f3183d2SMingkai Hu if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
8789f3183d2SMingkai Hu mask |= 1 << count;
8799f3183d2SMingkai Hu count++;
8809f3183d2SMingkai Hu }
8819f3183d2SMingkai Hu }
8829f3183d2SMingkai Hu i++;
8839f3183d2SMingkai Hu } while ((cluster & TP_CLUSTER_EOC) == 0x0);
8849f3183d2SMingkai Hu
8859f3183d2SMingkai Hu return mask;
8869f3183d2SMingkai Hu }
8879f3183d2SMingkai Hu
8889f3183d2SMingkai Hu /*
8899f3183d2SMingkai Hu * Return the number of cores on this SOC.
8909f3183d2SMingkai Hu */
cpu_numcores(void)8919f3183d2SMingkai Hu int cpu_numcores(void)
8929f3183d2SMingkai Hu {
8939f3183d2SMingkai Hu return hweight32(cpu_mask());
8949f3183d2SMingkai Hu }
8959f3183d2SMingkai Hu
fsl_qoriq_core_to_cluster(unsigned int core)8969f3183d2SMingkai Hu int fsl_qoriq_core_to_cluster(unsigned int core)
8979f3183d2SMingkai Hu {
8989f3183d2SMingkai Hu struct ccsr_gur __iomem *gur =
8999f3183d2SMingkai Hu (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
9009f3183d2SMingkai Hu int i = 0, count = 0;
9019f3183d2SMingkai Hu u32 cluster;
9029f3183d2SMingkai Hu
9039f3183d2SMingkai Hu do {
9049f3183d2SMingkai Hu int j;
9059f3183d2SMingkai Hu
9069f3183d2SMingkai Hu cluster = gur_in32(&gur->tp_cluster[i].lower);
9079f3183d2SMingkai Hu for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
9089f3183d2SMingkai Hu if (initiator_type(cluster, j)) {
9099f3183d2SMingkai Hu if (count == core)
9109f3183d2SMingkai Hu return i;
9119f3183d2SMingkai Hu count++;
9129f3183d2SMingkai Hu }
9139f3183d2SMingkai Hu }
9149f3183d2SMingkai Hu i++;
9159f3183d2SMingkai Hu } while ((cluster & TP_CLUSTER_EOC) == 0x0);
9169f3183d2SMingkai Hu
9179f3183d2SMingkai Hu return -1; /* cannot identify the cluster */
9189f3183d2SMingkai Hu }
9199f3183d2SMingkai Hu
fsl_qoriq_core_to_type(unsigned int core)9209f3183d2SMingkai Hu u32 fsl_qoriq_core_to_type(unsigned int core)
9219f3183d2SMingkai Hu {
9229f3183d2SMingkai Hu struct ccsr_gur __iomem *gur =
9239f3183d2SMingkai Hu (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
9249f3183d2SMingkai Hu int i = 0, count = 0;
9259f3183d2SMingkai Hu u32 cluster, type;
9269f3183d2SMingkai Hu
9279f3183d2SMingkai Hu do {
9289f3183d2SMingkai Hu int j;
9299f3183d2SMingkai Hu
9309f3183d2SMingkai Hu cluster = gur_in32(&gur->tp_cluster[i].lower);
9319f3183d2SMingkai Hu for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
9329f3183d2SMingkai Hu type = initiator_type(cluster, j);
9339f3183d2SMingkai Hu if (type) {
9349f3183d2SMingkai Hu if (count == core)
9359f3183d2SMingkai Hu return type;
9369f3183d2SMingkai Hu count++;
9379f3183d2SMingkai Hu }
9389f3183d2SMingkai Hu }
9399f3183d2SMingkai Hu i++;
9409f3183d2SMingkai Hu } while ((cluster & TP_CLUSTER_EOC) == 0x0);
9419f3183d2SMingkai Hu
9429f3183d2SMingkai Hu return -1; /* cannot identify the cluster */
9439f3183d2SMingkai Hu }
9449f3183d2SMingkai Hu
945f6a70b3aSPriyanka Jain #ifndef CONFIG_FSL_LSCH3
get_svr(void)9466fb522dcSSriram Dash uint get_svr(void)
9476fb522dcSSriram Dash {
9486fb522dcSSriram Dash struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
9496fb522dcSSriram Dash
9506fb522dcSSriram Dash return gur_in32(&gur->svr);
9516fb522dcSSriram Dash }
952f6a70b3aSPriyanka Jain #endif
9536fb522dcSSriram Dash
9549f3183d2SMingkai Hu #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)9559f3183d2SMingkai Hu int print_cpuinfo(void)
9569f3183d2SMingkai Hu {
9579f3183d2SMingkai Hu struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
9589f3183d2SMingkai Hu struct sys_info sysinfo;
9599f3183d2SMingkai Hu char buf[32];
9609f3183d2SMingkai Hu unsigned int i, core;
9613c1d218aSYork Sun u32 type, rcw, svr = gur_in32(&gur->svr);
9629f3183d2SMingkai Hu
9639f3183d2SMingkai Hu puts("SoC: ");
9649f3183d2SMingkai Hu
9659f3183d2SMingkai Hu cpu_name(buf);
9663c1d218aSYork Sun printf(" %s (0x%x)\n", buf, svr);
9679f3183d2SMingkai Hu memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
9689f3183d2SMingkai Hu get_sys_info(&sysinfo);
9699f3183d2SMingkai Hu puts("Clock Configuration:");
9709f3183d2SMingkai Hu for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
9719f3183d2SMingkai Hu if (!(i % 3))
9729f3183d2SMingkai Hu puts("\n ");
9739f3183d2SMingkai Hu type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
9749f3183d2SMingkai Hu printf("CPU%d(%s):%-4s MHz ", core,
9759f3183d2SMingkai Hu type == TY_ITYP_VER_A7 ? "A7 " :
9769f3183d2SMingkai Hu (type == TY_ITYP_VER_A53 ? "A53" :
97779119a4dSAlison Wang (type == TY_ITYP_VER_A57 ? "A57" :
97879119a4dSAlison Wang (type == TY_ITYP_VER_A72 ? "A72" : " "))),
9799f3183d2SMingkai Hu strmhz(buf, sysinfo.freq_processor[core]));
9809f3183d2SMingkai Hu }
981904110c7SHou Zhiqiang /* Display platform clock as Bus frequency. */
9829f3183d2SMingkai Hu printf("\n Bus: %-4s MHz ",
983904110c7SHou Zhiqiang strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
9849f3183d2SMingkai Hu printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
985e8297341SShaohui Xie #ifdef CONFIG_SYS_DPAA_FMAN
986e8297341SShaohui Xie printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
987e8297341SShaohui Xie #endif
98844937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
9893c1d218aSYork Sun if (soc_has_dp_ddr()) {
9903c1d218aSYork Sun printf(" DP-DDR: %-4s MT/s",
9913c1d218aSYork Sun strmhz(buf, sysinfo.freq_ddrbus2));
9923c1d218aSYork Sun }
9939f3183d2SMingkai Hu #endif
9949f3183d2SMingkai Hu puts("\n");
9959f3183d2SMingkai Hu
9969f3183d2SMingkai Hu /*
9979f3183d2SMingkai Hu * Display the RCW, so that no one gets confused as to what RCW
9989f3183d2SMingkai Hu * we're actually using for this boot.
9999f3183d2SMingkai Hu */
10009f3183d2SMingkai Hu puts("Reset Configuration Word (RCW):");
10019f3183d2SMingkai Hu for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
10029f3183d2SMingkai Hu rcw = gur_in32(&gur->rcwsr[i]);
10039f3183d2SMingkai Hu if ((i % 4) == 0)
10049f3183d2SMingkai Hu printf("\n %08x:", i * 4);
10059f3183d2SMingkai Hu printf(" %08x", rcw);
10069f3183d2SMingkai Hu }
10079f3183d2SMingkai Hu puts("\n");
10089f3183d2SMingkai Hu
10099f3183d2SMingkai Hu return 0;
10109f3183d2SMingkai Hu }
10119f3183d2SMingkai Hu #endif
10129f3183d2SMingkai Hu
10139f3183d2SMingkai Hu #ifdef CONFIG_FSL_ESDHC
cpu_mmc_init(bd_t * bis)10149f3183d2SMingkai Hu int cpu_mmc_init(bd_t *bis)
10159f3183d2SMingkai Hu {
10169f3183d2SMingkai Hu return fsl_esdhc_mmc_init(bis);
10179f3183d2SMingkai Hu }
10189f3183d2SMingkai Hu #endif
10199f3183d2SMingkai Hu
cpu_eth_init(bd_t * bis)10209f3183d2SMingkai Hu int cpu_eth_init(bd_t *bis)
10219f3183d2SMingkai Hu {
10229f3183d2SMingkai Hu int error = 0;
10239f3183d2SMingkai Hu
10241f55a938SSantan Kumar #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
10259f3183d2SMingkai Hu error = fsl_mc_ldpaa_init(bis);
10269f3183d2SMingkai Hu #endif
1027e8297341SShaohui Xie #ifdef CONFIG_FMAN_ENET
1028e8297341SShaohui Xie fm_standard_init(bis);
1029e8297341SShaohui Xie #endif
10309f3183d2SMingkai Hu return error;
10319f3183d2SMingkai Hu }
10329f3183d2SMingkai Hu
check_psci(void)1033026f30ecSYuantian Tang static inline int check_psci(void)
1034026f30ecSYuantian Tang {
1035026f30ecSYuantian Tang unsigned int psci_ver;
1036026f30ecSYuantian Tang
1037026f30ecSYuantian Tang psci_ver = sec_firmware_support_psci_version();
1038026f30ecSYuantian Tang if (psci_ver == PSCI_INVALID_VER)
1039026f30ecSYuantian Tang return 1;
1040026f30ecSYuantian Tang
1041026f30ecSYuantian Tang return 0;
1042026f30ecSYuantian Tang }
1043026f30ecSYuantian Tang
config_core_prefetch(void)10442db53cfeSPrabhakar Kushwaha static void config_core_prefetch(void)
10452db53cfeSPrabhakar Kushwaha {
10462db53cfeSPrabhakar Kushwaha char *buf = NULL;
10472db53cfeSPrabhakar Kushwaha char buffer[HWCONFIG_BUFFER_SIZE];
10482db53cfeSPrabhakar Kushwaha const char *prefetch_arg = NULL;
10492db53cfeSPrabhakar Kushwaha size_t arglen;
10502db53cfeSPrabhakar Kushwaha unsigned int mask;
10512db53cfeSPrabhakar Kushwaha struct pt_regs regs;
10522db53cfeSPrabhakar Kushwaha
10532db53cfeSPrabhakar Kushwaha if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
10542db53cfeSPrabhakar Kushwaha buf = buffer;
10552db53cfeSPrabhakar Kushwaha
10562db53cfeSPrabhakar Kushwaha prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
10572db53cfeSPrabhakar Kushwaha &arglen, buf);
10582db53cfeSPrabhakar Kushwaha
10592db53cfeSPrabhakar Kushwaha if (prefetch_arg) {
10602db53cfeSPrabhakar Kushwaha mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
10612db53cfeSPrabhakar Kushwaha if (mask & 0x1) {
10622db53cfeSPrabhakar Kushwaha printf("Core0 prefetch can't be disabled\n");
10632db53cfeSPrabhakar Kushwaha return;
10642db53cfeSPrabhakar Kushwaha }
10652db53cfeSPrabhakar Kushwaha
10662db53cfeSPrabhakar Kushwaha #define SIP_PREFETCH_DISABLE_64 0xC200FF13
10672db53cfeSPrabhakar Kushwaha regs.regs[0] = SIP_PREFETCH_DISABLE_64;
10682db53cfeSPrabhakar Kushwaha regs.regs[1] = mask;
10692db53cfeSPrabhakar Kushwaha smc_call(®s);
10702db53cfeSPrabhakar Kushwaha
10712db53cfeSPrabhakar Kushwaha if (regs.regs[0])
10722db53cfeSPrabhakar Kushwaha printf("Prefetch disable config failed for mask ");
10732db53cfeSPrabhakar Kushwaha else
10742db53cfeSPrabhakar Kushwaha printf("Prefetch disable config passed for mask ");
10752db53cfeSPrabhakar Kushwaha printf("0x%x\n", mask);
10762db53cfeSPrabhakar Kushwaha }
10772db53cfeSPrabhakar Kushwaha }
10782db53cfeSPrabhakar Kushwaha
arch_early_init_r(void)10799f3183d2SMingkai Hu int arch_early_init_r(void)
10809f3183d2SMingkai Hu {
1081b4017364SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1082eea1cb77SPriyanka Jain u32 svr_dev_id;
1083eea1cb77SPriyanka Jain /*
1084eea1cb77SPriyanka Jain * erratum A009635 is valid only for LS2080A SoC and
1085eea1cb77SPriyanka Jain * its personalitiesi
1086eea1cb77SPriyanka Jain */
1087a8f33034SWenbin song svr_dev_id = get_svr();
1088a8f33034SWenbin song if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1089b4017364SPrabhakar Kushwaha erratum_a009635();
1090b4017364SPrabhakar Kushwaha #endif
109102fb2761SShengzhou Liu #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
109202fb2761SShengzhou Liu erratum_a009942_check_cpo();
109302fb2761SShengzhou Liu #endif
1094026f30ecSYuantian Tang if (check_psci()) {
1095026f30ecSYuantian Tang debug("PSCI: PSCI does not exist.\n");
1096026f30ecSYuantian Tang
1097026f30ecSYuantian Tang /* if PSCI does not exist, boot secondary cores here */
1098026f30ecSYuantian Tang if (fsl_layerscape_wake_seconday_cores())
10999f3183d2SMingkai Hu printf("Did not wake secondary cores\n");
1100032d5bb4SHou Zhiqiang }
11019f3183d2SMingkai Hu
11022db53cfeSPrabhakar Kushwaha config_core_prefetch();
11032db53cfeSPrabhakar Kushwaha
11049f3183d2SMingkai Hu #ifdef CONFIG_SYS_HAS_SERDES
11059f3183d2SMingkai Hu fsl_serdes_init();
11069f3183d2SMingkai Hu #endif
1107*2e53759dSPankaj Bansal #ifdef CONFIG_SYS_FSL_HAS_RGMII
1108*2e53759dSPankaj Bansal /* some dpmacs in armv8a based freescale layerscape SOCs can be
1109*2e53759dSPankaj Bansal * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1110*2e53759dSPankaj Bansal * EC*_PMUX(rgmii) bits in RCW.
1111*2e53759dSPankaj Bansal * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1112*2e53759dSPankaj Bansal * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1113*2e53759dSPankaj Bansal * Now if a dpmac is enabled by serdes bits then it takes precedence
1114*2e53759dSPankaj Bansal * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1115*2e53759dSPankaj Bansal * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1116*2e53759dSPankaj Bansal * then the dpmac is SGMII and not RGMII.
1117*2e53759dSPankaj Bansal *
1118*2e53759dSPankaj Bansal * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1119*2e53759dSPankaj Bansal * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1120*2e53759dSPankaj Bansal * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1121*2e53759dSPankaj Bansal * then don't enable it.
1122*2e53759dSPankaj Bansal */
1123*2e53759dSPankaj Bansal fsl_rgmii_init();
1124*2e53759dSPankaj Bansal #endif
1125e8297341SShaohui Xie #ifdef CONFIG_FMAN_ENET
1126e8297341SShaohui Xie fman_enet_init();
1127e8297341SShaohui Xie #endif
112844262327SAhmed Mansour #ifdef CONFIG_SYS_DPAA_QBMAN
112944262327SAhmed Mansour setup_qbman_portals();
113044262327SAhmed Mansour #endif
11319f3183d2SMingkai Hu return 0;
11329f3183d2SMingkai Hu }
11339f3183d2SMingkai Hu
timer_init(void)11349f3183d2SMingkai Hu int timer_init(void)
11359f3183d2SMingkai Hu {
11369f3183d2SMingkai Hu u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
11379f3183d2SMingkai Hu #ifdef CONFIG_FSL_LSCH3
11389f3183d2SMingkai Hu u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
11399f3183d2SMingkai Hu #endif
1140958b2ed5SZhang Ying-22455 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1141a758177fSYunhui Cui u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1142f6b96ff6SPriyanka Jain u32 svr_dev_id;
1143a758177fSYunhui Cui #endif
11449f3183d2SMingkai Hu #ifdef COUNTER_FREQUENCY_REAL
11459f3183d2SMingkai Hu unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
11469f3183d2SMingkai Hu
11479f3183d2SMingkai Hu /* Update with accurate clock frequency */
1148399e2bb6SYork Sun if (current_el() == 3)
11499f3183d2SMingkai Hu asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
11509f3183d2SMingkai Hu #endif
11519f3183d2SMingkai Hu
11529f3183d2SMingkai Hu #ifdef CONFIG_FSL_LSCH3
11539f3183d2SMingkai Hu /* Enable timebase for all clusters.
11549f3183d2SMingkai Hu * It is safe to do so even some clusters are not enabled.
11559f3183d2SMingkai Hu */
11569f3183d2SMingkai Hu out_le32(cltbenr, 0xf);
11579f3183d2SMingkai Hu #endif
11589f3183d2SMingkai Hu
1159958b2ed5SZhang Ying-22455 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1160a758177fSYunhui Cui /*
1161a758177fSYunhui Cui * In certain Layerscape SoCs, the clock for each core's
1162a758177fSYunhui Cui * has an enable bit in the PMU Physical Core Time Base Enable
1163a758177fSYunhui Cui * Register (PCTBENR), which allows the watchdog to operate.
1164a758177fSYunhui Cui */
1165a758177fSYunhui Cui setbits_le32(pctbenr, 0xff);
1166f6b96ff6SPriyanka Jain /*
1167f6b96ff6SPriyanka Jain * For LS2080A SoC and its personalities, timer controller
1168f6b96ff6SPriyanka Jain * offset is different
1169f6b96ff6SPriyanka Jain */
1170a8f33034SWenbin song svr_dev_id = get_svr();
1171a8f33034SWenbin song if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1172f6b96ff6SPriyanka Jain cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1173f6b96ff6SPriyanka Jain
1174a758177fSYunhui Cui #endif
1175a758177fSYunhui Cui
11769f3183d2SMingkai Hu /* Enable clock for timer
11779f3183d2SMingkai Hu * This is a global setting.
11789f3183d2SMingkai Hu */
11799f3183d2SMingkai Hu out_le32(cntcr, 0x1);
11809f3183d2SMingkai Hu
11819f3183d2SMingkai Hu return 0;
11829f3183d2SMingkai Hu }
11839f3183d2SMingkai Hu
118478d57842SAlexander Graf __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
118578d57842SAlexander Graf
reset_cpu(ulong addr)118678d57842SAlexander Graf void __efi_runtime reset_cpu(ulong addr)
11879f3183d2SMingkai Hu {
11889f3183d2SMingkai Hu u32 val;
11899f3183d2SMingkai Hu
11904909b89eSPriyanka Jain #ifdef CONFIG_ARCH_LX2160A
11914909b89eSPriyanka Jain val = in_le32(rstcr);
11924909b89eSPriyanka Jain val |= 0x01;
11934909b89eSPriyanka Jain out_le32(rstcr, val);
11944909b89eSPriyanka Jain #else
11959f3183d2SMingkai Hu /* Raise RESET_REQ_B */
11969f3183d2SMingkai Hu val = scfg_in32(rstcr);
11979f3183d2SMingkai Hu val |= 0x02;
11989f3183d2SMingkai Hu scfg_out32(rstcr, val);
11994909b89eSPriyanka Jain #endif
12009f3183d2SMingkai Hu }
1201c0492141SYork Sun
120278d57842SAlexander Graf #ifdef CONFIG_EFI_LOADER
120378d57842SAlexander Graf
efi_reset_system(enum efi_reset_type reset_type,efi_status_t reset_status,unsigned long data_size,void * reset_data)120478d57842SAlexander Graf void __efi_runtime EFIAPI efi_reset_system(
120578d57842SAlexander Graf enum efi_reset_type reset_type,
120678d57842SAlexander Graf efi_status_t reset_status,
120778d57842SAlexander Graf unsigned long data_size, void *reset_data)
120878d57842SAlexander Graf {
120978d57842SAlexander Graf switch (reset_type) {
121078d57842SAlexander Graf case EFI_RESET_COLD:
121178d57842SAlexander Graf case EFI_RESET_WARM:
1212482fc90cSHeinrich Schuchardt case EFI_RESET_PLATFORM_SPECIFIC:
121378d57842SAlexander Graf reset_cpu(0);
121478d57842SAlexander Graf break;
121578d57842SAlexander Graf case EFI_RESET_SHUTDOWN:
121678d57842SAlexander Graf /* Nothing we can do */
121778d57842SAlexander Graf break;
121878d57842SAlexander Graf }
121978d57842SAlexander Graf
122078d57842SAlexander Graf while (1) { }
122178d57842SAlexander Graf }
122278d57842SAlexander Graf
efi_reset_system_init(void)122322c793e6SHeinrich Schuchardt efi_status_t efi_reset_system_init(void)
122478d57842SAlexander Graf {
122522c793e6SHeinrich Schuchardt return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
122678d57842SAlexander Graf }
122778d57842SAlexander Graf
122878d57842SAlexander Graf #endif
122978d57842SAlexander Graf
1230e9303a41SYork Sun /*
1231e9303a41SYork Sun * Calculate reserved memory with given memory bank
1232e9303a41SYork Sun * Return aligned memory size on success
1233e9303a41SYork Sun * Return (ram_size + needed size) for failure
1234e9303a41SYork Sun */
board_reserve_ram_top(phys_size_t ram_size)1235c0492141SYork Sun phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1236c0492141SYork Sun {
1237c0492141SYork Sun phys_size_t ram_top = ram_size;
1238c0492141SYork Sun
12391f55a938SSantan Kumar #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1240e9303a41SYork Sun ram_top = mc_get_dram_block_size();
1241e9303a41SYork Sun if (ram_top > ram_size)
1242e9303a41SYork Sun return ram_size + ram_top;
1243e9303a41SYork Sun
1244e9303a41SYork Sun ram_top = ram_size - ram_top;
124536cc0de0SYork Sun /* The start address of MC reserved memory needs to be aligned. */
1246c0492141SYork Sun ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1247c0492141SYork Sun #endif
1248c0492141SYork Sun
124936cc0de0SYork Sun return ram_size - ram_top;
1250c0492141SYork Sun }
125136cc0de0SYork Sun
get_effective_memsize(void)125236cc0de0SYork Sun phys_size_t get_effective_memsize(void)
125336cc0de0SYork Sun {
125436cc0de0SYork Sun phys_size_t ea_size, rem = 0;
125536cc0de0SYork Sun
125636cc0de0SYork Sun /*
125736cc0de0SYork Sun * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1258710d0cd7SSumit Garg * first region is 2GB space at 0x8000_0000. Secure memory needs to
1259710d0cd7SSumit Garg * allocated from first region. If the memory extends to the second
1260710d0cd7SSumit Garg * region (or the third region if applicable), Management Complex (MC)
1261710d0cd7SSumit Garg * memory should be put into the highest region, i.e. the end of DDR
1262710d0cd7SSumit Garg * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1263710d0cd7SSumit Garg * U-Boot doesn't relocate itself into higher address. Should DDR be
1264710d0cd7SSumit Garg * configured to skip the first region, this function needs to be
1265710d0cd7SSumit Garg * adjusted.
126636cc0de0SYork Sun */
126736cc0de0SYork Sun if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
126836cc0de0SYork Sun ea_size = CONFIG_MAX_MEM_MAPPED;
126936cc0de0SYork Sun rem = gd->ram_size - ea_size;
127036cc0de0SYork Sun } else {
127136cc0de0SYork Sun ea_size = gd->ram_size;
127236cc0de0SYork Sun }
127336cc0de0SYork Sun
127436cc0de0SYork Sun #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
127536cc0de0SYork Sun /* Check if we have enough space for secure memory */
1276710d0cd7SSumit Garg if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
127736cc0de0SYork Sun ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1278710d0cd7SSumit Garg else
127936cc0de0SYork Sun printf("Error: No enough space for secure memory.\n");
128036cc0de0SYork Sun #endif
128136cc0de0SYork Sun /* Check if we have enough memory for MC */
128236cc0de0SYork Sun if (rem < board_reserve_ram_top(rem)) {
128336cc0de0SYork Sun /* Not enough memory in high region to reserve */
1284e9303a41SYork Sun if (ea_size > board_reserve_ram_top(ea_size))
1285e9303a41SYork Sun ea_size -= board_reserve_ram_top(ea_size);
128636cc0de0SYork Sun else
128736cc0de0SYork Sun printf("Error: No enough space for reserved memory.\n");
128836cc0de0SYork Sun }
128936cc0de0SYork Sun
129036cc0de0SYork Sun return ea_size;
129136cc0de0SYork Sun }
129236cc0de0SYork Sun
1293681d489eSRajesh Bhagat #ifdef CONFIG_TFABOOT
tfa_get_dram_size(void)1294681d489eSRajesh Bhagat phys_size_t tfa_get_dram_size(void)
1295681d489eSRajesh Bhagat {
1296681d489eSRajesh Bhagat struct pt_regs regs;
1297681d489eSRajesh Bhagat phys_size_t dram_size = 0;
1298681d489eSRajesh Bhagat
1299681d489eSRajesh Bhagat regs.regs[0] = SMC_DRAM_BANK_INFO;
1300681d489eSRajesh Bhagat regs.regs[1] = -1;
1301681d489eSRajesh Bhagat
1302681d489eSRajesh Bhagat smc_call(®s);
1303681d489eSRajesh Bhagat if (regs.regs[0])
1304681d489eSRajesh Bhagat return 0;
1305681d489eSRajesh Bhagat
1306681d489eSRajesh Bhagat dram_size = regs.regs[1];
1307681d489eSRajesh Bhagat return dram_size;
1308681d489eSRajesh Bhagat }
1309681d489eSRajesh Bhagat
tfa_dram_init_banksize(void)1310681d489eSRajesh Bhagat static int tfa_dram_init_banksize(void)
1311681d489eSRajesh Bhagat {
1312681d489eSRajesh Bhagat int i = 0, ret = 0;
1313681d489eSRajesh Bhagat struct pt_regs regs;
1314681d489eSRajesh Bhagat phys_size_t dram_size = tfa_get_dram_size();
1315681d489eSRajesh Bhagat
1316681d489eSRajesh Bhagat debug("dram_size %llx\n", dram_size);
1317681d489eSRajesh Bhagat
1318681d489eSRajesh Bhagat if (!dram_size)
1319681d489eSRajesh Bhagat return -EINVAL;
1320681d489eSRajesh Bhagat
1321681d489eSRajesh Bhagat do {
1322681d489eSRajesh Bhagat regs.regs[0] = SMC_DRAM_BANK_INFO;
1323681d489eSRajesh Bhagat regs.regs[1] = i;
1324681d489eSRajesh Bhagat
1325681d489eSRajesh Bhagat smc_call(®s);
1326681d489eSRajesh Bhagat if (regs.regs[0]) {
1327681d489eSRajesh Bhagat ret = -EINVAL;
1328681d489eSRajesh Bhagat break;
1329681d489eSRajesh Bhagat }
1330681d489eSRajesh Bhagat
1331681d489eSRajesh Bhagat debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1332681d489eSRajesh Bhagat regs.regs[2]);
1333681d489eSRajesh Bhagat gd->bd->bi_dram[i].start = regs.regs[1];
1334681d489eSRajesh Bhagat gd->bd->bi_dram[i].size = regs.regs[2];
1335681d489eSRajesh Bhagat
1336681d489eSRajesh Bhagat dram_size -= gd->bd->bi_dram[i].size;
1337681d489eSRajesh Bhagat
1338681d489eSRajesh Bhagat i++;
1339681d489eSRajesh Bhagat } while (dram_size);
1340681d489eSRajesh Bhagat
1341681d489eSRajesh Bhagat if (i > 0)
1342681d489eSRajesh Bhagat ret = 0;
1343681d489eSRajesh Bhagat
1344681d489eSRajesh Bhagat #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1345681d489eSRajesh Bhagat /* Assign memory for MC */
1346681d489eSRajesh Bhagat #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1347681d489eSRajesh Bhagat if (gd->bd->bi_dram[2].size >=
1348681d489eSRajesh Bhagat board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1349681d489eSRajesh Bhagat gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1350681d489eSRajesh Bhagat gd->bd->bi_dram[2].size -
1351681d489eSRajesh Bhagat board_reserve_ram_top(gd->bd->bi_dram[2].size);
1352681d489eSRajesh Bhagat } else
1353681d489eSRajesh Bhagat #endif
1354681d489eSRajesh Bhagat {
1355681d489eSRajesh Bhagat if (gd->bd->bi_dram[1].size >=
1356681d489eSRajesh Bhagat board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1357681d489eSRajesh Bhagat gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1358681d489eSRajesh Bhagat gd->bd->bi_dram[1].size -
1359681d489eSRajesh Bhagat board_reserve_ram_top(gd->bd->bi_dram[1].size);
1360681d489eSRajesh Bhagat } else if (gd->bd->bi_dram[0].size >
1361681d489eSRajesh Bhagat board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1362681d489eSRajesh Bhagat gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1363681d489eSRajesh Bhagat gd->bd->bi_dram[0].size -
1364681d489eSRajesh Bhagat board_reserve_ram_top(gd->bd->bi_dram[0].size);
1365681d489eSRajesh Bhagat }
1366681d489eSRajesh Bhagat }
1367681d489eSRajesh Bhagat #endif /* CONFIG_FSL_MC_ENET */
1368681d489eSRajesh Bhagat
1369681d489eSRajesh Bhagat return ret;
1370681d489eSRajesh Bhagat }
1371681d489eSRajesh Bhagat #endif
1372681d489eSRajesh Bhagat
dram_init_banksize(void)137376b00acaSSimon Glass int dram_init_banksize(void)
137436cc0de0SYork Sun {
137536cc0de0SYork Sun #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
137636cc0de0SYork Sun phys_size_t dp_ddr_size;
137736cc0de0SYork Sun #endif
137836cc0de0SYork Sun
1379681d489eSRajesh Bhagat #ifdef CONFIG_TFABOOT
1380681d489eSRajesh Bhagat if (!tfa_dram_init_banksize())
1381681d489eSRajesh Bhagat return 0;
1382681d489eSRajesh Bhagat #endif
138336cc0de0SYork Sun /*
138436cc0de0SYork Sun * gd->ram_size has the total size of DDR memory, less reserved secure
138536cc0de0SYork Sun * memory. The DDR extends from low region to high region(s) presuming
138636cc0de0SYork Sun * no hole is created with DDR configuration. gd->arch.secure_ram tracks
138736cc0de0SYork Sun * the location of secure memory. gd->arch.resv_ram tracks the location
13887eb40f0fSYork Sun * of reserved memory for Management Complex (MC). Because gd->ram_size
13897eb40f0fSYork Sun * is reduced by this function if secure memory is reserved, checking
13907eb40f0fSYork Sun * gd->arch.secure_ram should be done to avoid running it repeatedly.
139136cc0de0SYork Sun */
13927eb40f0fSYork Sun
13937eb40f0fSYork Sun #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
13947eb40f0fSYork Sun if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
13957eb40f0fSYork Sun debug("No need to run again, skip %s\n", __func__);
13967eb40f0fSYork Sun
13977eb40f0fSYork Sun return 0;
13987eb40f0fSYork Sun }
13997eb40f0fSYork Sun #endif
14007eb40f0fSYork Sun
140136cc0de0SYork Sun gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
140236cc0de0SYork Sun if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
140336cc0de0SYork Sun gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
140436cc0de0SYork Sun gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
140536cc0de0SYork Sun gd->bd->bi_dram[1].size = gd->ram_size -
140636cc0de0SYork Sun CONFIG_SYS_DDR_BLOCK1_SIZE;
140736cc0de0SYork Sun #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
140836cc0de0SYork Sun if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
140936cc0de0SYork Sun gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
141036cc0de0SYork Sun gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
141136cc0de0SYork Sun CONFIG_SYS_DDR_BLOCK2_SIZE;
141236cc0de0SYork Sun gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
141336cc0de0SYork Sun }
141436cc0de0SYork Sun #endif
141536cc0de0SYork Sun } else {
141636cc0de0SYork Sun gd->bd->bi_dram[0].size = gd->ram_size;
141736cc0de0SYork Sun }
141836cc0de0SYork Sun #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1419710d0cd7SSumit Garg if (gd->bd->bi_dram[0].size >
142036cc0de0SYork Sun CONFIG_SYS_MEM_RESERVE_SECURE) {
142136cc0de0SYork Sun gd->bd->bi_dram[0].size -=
142236cc0de0SYork Sun CONFIG_SYS_MEM_RESERVE_SECURE;
142336cc0de0SYork Sun gd->arch.secure_ram = gd->bd->bi_dram[0].start +
142436cc0de0SYork Sun gd->bd->bi_dram[0].size;
142536cc0de0SYork Sun gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
142636cc0de0SYork Sun gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
142736cc0de0SYork Sun }
142836cc0de0SYork Sun #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
142936cc0de0SYork Sun
14301f55a938SSantan Kumar #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
143136cc0de0SYork Sun /* Assign memory for MC */
143236cc0de0SYork Sun #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
143336cc0de0SYork Sun if (gd->bd->bi_dram[2].size >=
143436cc0de0SYork Sun board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
143536cc0de0SYork Sun gd->arch.resv_ram = gd->bd->bi_dram[2].start +
143636cc0de0SYork Sun gd->bd->bi_dram[2].size -
143736cc0de0SYork Sun board_reserve_ram_top(gd->bd->bi_dram[2].size);
143836cc0de0SYork Sun } else
143936cc0de0SYork Sun #endif
144036cc0de0SYork Sun {
144136cc0de0SYork Sun if (gd->bd->bi_dram[1].size >=
144236cc0de0SYork Sun board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
144336cc0de0SYork Sun gd->arch.resv_ram = gd->bd->bi_dram[1].start +
144436cc0de0SYork Sun gd->bd->bi_dram[1].size -
144536cc0de0SYork Sun board_reserve_ram_top(gd->bd->bi_dram[1].size);
144636cc0de0SYork Sun } else if (gd->bd->bi_dram[0].size >
144736cc0de0SYork Sun board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
144836cc0de0SYork Sun gd->arch.resv_ram = gd->bd->bi_dram[0].start +
144936cc0de0SYork Sun gd->bd->bi_dram[0].size -
145036cc0de0SYork Sun board_reserve_ram_top(gd->bd->bi_dram[0].size);
145136cc0de0SYork Sun }
145236cc0de0SYork Sun }
145336cc0de0SYork Sun #endif /* CONFIG_FSL_MC_ENET */
145436cc0de0SYork Sun
145536cc0de0SYork Sun #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
145636cc0de0SYork Sun #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
145736cc0de0SYork Sun #error "This SoC shouldn't have DP DDR"
145836cc0de0SYork Sun #endif
145936cc0de0SYork Sun if (soc_has_dp_ddr()) {
146036cc0de0SYork Sun /* initialize DP-DDR here */
146136cc0de0SYork Sun puts("DP-DDR: ");
146236cc0de0SYork Sun /*
146336cc0de0SYork Sun * DDR controller use 0 as the base address for binding.
146436cc0de0SYork Sun * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
146536cc0de0SYork Sun */
146636cc0de0SYork Sun dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
146736cc0de0SYork Sun CONFIG_DP_DDR_CTRL,
146836cc0de0SYork Sun CONFIG_DP_DDR_NUM_CTRLS,
146936cc0de0SYork Sun CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
147036cc0de0SYork Sun NULL, NULL, NULL);
147136cc0de0SYork Sun if (dp_ddr_size) {
147236cc0de0SYork Sun gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
147336cc0de0SYork Sun gd->bd->bi_dram[2].size = dp_ddr_size;
147436cc0de0SYork Sun } else {
147536cc0de0SYork Sun puts("Not detected");
147636cc0de0SYork Sun }
147736cc0de0SYork Sun }
147836cc0de0SYork Sun #endif
147976b00acaSSimon Glass
14807eb40f0fSYork Sun #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
14817eb40f0fSYork Sun debug("%s is called. gd->ram_size is reduced to %lu\n",
14827eb40f0fSYork Sun __func__, (ulong)gd->ram_size);
14837eb40f0fSYork Sun #endif
14847eb40f0fSYork Sun
148576b00acaSSimon Glass return 0;
148636cc0de0SYork Sun }
148736cc0de0SYork Sun
14889b5e6396SStephen Warren #if CONFIG_IS_ENABLED(EFI_LOADER)
efi_add_known_memory(void)148936cc0de0SYork Sun void efi_add_known_memory(void)
149036cc0de0SYork Sun {
149136cc0de0SYork Sun int i;
149236cc0de0SYork Sun phys_addr_t ram_start, start;
149336cc0de0SYork Sun phys_size_t ram_size;
149436cc0de0SYork Sun u64 pages;
149536cc0de0SYork Sun
149636cc0de0SYork Sun /* Add RAM */
149736cc0de0SYork Sun for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
149836cc0de0SYork Sun #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
149936cc0de0SYork Sun #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
150036cc0de0SYork Sun #error "This SoC shouldn't have DP DDR"
150136cc0de0SYork Sun #endif
150236cc0de0SYork Sun if (i == 2)
150336cc0de0SYork Sun continue; /* skip DP-DDR */
150436cc0de0SYork Sun #endif
150536cc0de0SYork Sun ram_start = gd->bd->bi_dram[i].start;
150636cc0de0SYork Sun ram_size = gd->bd->bi_dram[i].size;
150736cc0de0SYork Sun #ifdef CONFIG_RESV_RAM
150836cc0de0SYork Sun if (gd->arch.resv_ram >= ram_start &&
150936cc0de0SYork Sun gd->arch.resv_ram < ram_start + ram_size)
151036cc0de0SYork Sun ram_size = gd->arch.resv_ram - ram_start;
151136cc0de0SYork Sun #endif
151236cc0de0SYork Sun start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
151336cc0de0SYork Sun pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
151436cc0de0SYork Sun
151536cc0de0SYork Sun efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
151636cc0de0SYork Sun false);
151736cc0de0SYork Sun }
151836cc0de0SYork Sun }
151936cc0de0SYork Sun #endif
15204961eafcSYork Sun
15214961eafcSYork Sun /*
15224961eafcSYork Sun * Before DDR size is known, early MMU table have DDR mapped as device memory
15234961eafcSYork Sun * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
15244961eafcSYork Sun * needs to be set for these mappings.
15254961eafcSYork Sun * If a special case configures DDR with holes in the mapping, the holes need
15264961eafcSYork Sun * to be marked as invalid. This is not implemented in this function.
15274961eafcSYork Sun */
update_early_mmu_table(void)15284961eafcSYork Sun void update_early_mmu_table(void)
15294961eafcSYork Sun {
15304961eafcSYork Sun if (!gd->arch.tlb_addr)
15314961eafcSYork Sun return;
15324961eafcSYork Sun
15334961eafcSYork Sun if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
15344961eafcSYork Sun mmu_change_region_attr(
15354961eafcSYork Sun CONFIG_SYS_SDRAM_BASE,
15364961eafcSYork Sun gd->ram_size,
15374961eafcSYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
15384961eafcSYork Sun PTE_BLOCK_OUTER_SHARE |
15394961eafcSYork Sun PTE_BLOCK_NS |
15404961eafcSYork Sun PTE_TYPE_VALID);
15414961eafcSYork Sun } else {
15424961eafcSYork Sun mmu_change_region_attr(
15434961eafcSYork Sun CONFIG_SYS_SDRAM_BASE,
15444961eafcSYork Sun CONFIG_SYS_DDR_BLOCK1_SIZE,
15454961eafcSYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
15464961eafcSYork Sun PTE_BLOCK_OUTER_SHARE |
15474961eafcSYork Sun PTE_BLOCK_NS |
15484961eafcSYork Sun PTE_TYPE_VALID);
15494961eafcSYork Sun #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
15504961eafcSYork Sun #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
15514961eafcSYork Sun #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
15524961eafcSYork Sun #endif
15534961eafcSYork Sun if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
15544961eafcSYork Sun CONFIG_SYS_DDR_BLOCK2_SIZE) {
15554961eafcSYork Sun mmu_change_region_attr(
15564961eafcSYork Sun CONFIG_SYS_DDR_BLOCK2_BASE,
15574961eafcSYork Sun CONFIG_SYS_DDR_BLOCK2_SIZE,
15584961eafcSYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
15594961eafcSYork Sun PTE_BLOCK_OUTER_SHARE |
15604961eafcSYork Sun PTE_BLOCK_NS |
15614961eafcSYork Sun PTE_TYPE_VALID);
15624961eafcSYork Sun mmu_change_region_attr(
15634961eafcSYork Sun CONFIG_SYS_DDR_BLOCK3_BASE,
15644961eafcSYork Sun gd->ram_size -
15654961eafcSYork Sun CONFIG_SYS_DDR_BLOCK1_SIZE -
15664961eafcSYork Sun CONFIG_SYS_DDR_BLOCK2_SIZE,
15674961eafcSYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
15684961eafcSYork Sun PTE_BLOCK_OUTER_SHARE |
15694961eafcSYork Sun PTE_BLOCK_NS |
15704961eafcSYork Sun PTE_TYPE_VALID);
15714961eafcSYork Sun } else
15724961eafcSYork Sun #endif
15734961eafcSYork Sun {
15744961eafcSYork Sun mmu_change_region_attr(
15754961eafcSYork Sun CONFIG_SYS_DDR_BLOCK2_BASE,
15764961eafcSYork Sun gd->ram_size -
15774961eafcSYork Sun CONFIG_SYS_DDR_BLOCK1_SIZE,
15784961eafcSYork Sun PTE_BLOCK_MEMTYPE(MT_NORMAL) |
15794961eafcSYork Sun PTE_BLOCK_OUTER_SHARE |
15804961eafcSYork Sun PTE_BLOCK_NS |
15814961eafcSYork Sun PTE_TYPE_VALID);
15824961eafcSYork Sun }
15834961eafcSYork Sun }
15844961eafcSYork Sun }
15854961eafcSYork Sun
dram_init(void)15864961eafcSYork Sun __weak int dram_init(void)
15874961eafcSYork Sun {
15883eace37eSSimon Glass fsl_initdram();
1589535d76a1SRajesh Bhagat #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1590535d76a1SRajesh Bhagat defined(CONFIG_SPL_BUILD)
15914961eafcSYork Sun /* This will break-before-make MMU for DDR */
15924961eafcSYork Sun update_early_mmu_table();
15934961eafcSYork Sun #endif
15944961eafcSYork Sun
15954961eafcSYork Sun return 0;
15964961eafcSYork Sun }
1597