1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
87 		if (!gd->bd->bi_dram[i].size)  in mem_map_fill()
90 		zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;  in mem_map_fill()
91 		zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;  in mem_map_fill()
92 		zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;  in mem_map_fill()
120 	gd->arch.tlb_size = PGTABLE_SIZE;  in reserve_mmu()
121 	gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;  in reserve_mmu()
131 	ver = readl(&csu_base->version);  in zynqmp_get_silicon_version_secure()
143 	gd->cpu_clk = get_tbclk();  in zynqmp_get_silicon_version()
145 	switch (gd->cpu_clk) {  in zynqmp_get_silicon_version()
199 			panic("PMUFW is not found - Please load it!\n");  in zynqmp_pmufw_version()
205 static int zynqmp_mmio_rawwrite(const u32 address,  in zynqmp_mmio_rawwrite()  argument
213 	ret = zynqmp_mmio_read(address, &data);  in zynqmp_mmio_rawwrite()
220 	writel(value_local, (ulong)address);  in zynqmp_mmio_rawwrite()
224 static int zynqmp_mmio_rawread(const u32 address, u32 *value)  in zynqmp_mmio_rawread()  argument
226 	*value = readl((ulong)address);  in zynqmp_mmio_rawread()
230 int zynqmp_mmio_write(const u32 address,  in zynqmp_mmio_write()  argument
235 		return zynqmp_mmio_rawwrite(address, mask, value);  in zynqmp_mmio_write()
237 		return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,  in zynqmp_mmio_write()
240 	return -EINVAL;  in zynqmp_mmio_write()
243 int zynqmp_mmio_read(const u32 address, u32 *value)  in zynqmp_mmio_read()  argument
249 		return -EINVAL;  in zynqmp_mmio_read()
252 		ret = zynqmp_mmio_rawread(address, value);  in zynqmp_mmio_read()
254 		ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,  in zynqmp_mmio_read()