Lines Matching +full:bd +full:- +full:address
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
21 /* Default UTBIPAR SMI address */
64 return -EINVAL; in uec_mac_enable()
66 uec_regs = uec->uec_regs; in uec_mac_enable()
68 maccfg1 = in_be32(&uec_regs->maccfg1); in uec_mac_enable()
72 out_be32(&uec_regs->maccfg1, maccfg1); in uec_mac_enable()
73 uec->mac_tx_enabled = 1; in uec_mac_enable()
78 out_be32(&uec_regs->maccfg1, maccfg1); in uec_mac_enable()
79 uec->mac_rx_enabled = 1; in uec_mac_enable()
92 return -EINVAL; in uec_mac_disable()
94 uec_regs = uec->uec_regs; in uec_mac_disable()
96 maccfg1 = in_be32(&uec_regs->maccfg1); in uec_mac_disable()
100 out_be32(&uec_regs->maccfg1, maccfg1); in uec_mac_disable()
101 uec->mac_tx_enabled = 0; in uec_mac_disable()
106 out_be32(&uec_regs->maccfg1, maccfg1); in uec_mac_disable()
107 uec->mac_rx_enabled = 0; in uec_mac_disable()
119 if (!uec || !uec->uccf) { in uec_graceful_stop_tx()
121 return -EINVAL; in uec_graceful_stop_tx()
124 uf_regs = uec->uccf->uf_regs; in uec_graceful_stop_tx()
127 out_be32(&uf_regs->ucce, UCCE_GRA); in uec_graceful_stop_tx()
131 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); in uec_graceful_stop_tx()
137 ucce = in_be32(&uf_regs->ucce); in uec_graceful_stop_tx()
140 uec->grace_stopped_tx = 1; in uec_graceful_stop_tx()
152 return -EINVAL; in uec_graceful_stop_rx()
155 if (!uec->p_rx_glbl_pram) { in uec_graceful_stop_rx()
157 return -EINVAL; in uec_graceful_stop_rx()
161 ack = uec->p_rx_glbl_pram->rxgstpack; in uec_graceful_stop_rx()
163 uec->p_rx_glbl_pram->rxgstpack = ack; in uec_graceful_stop_rx()
169 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); in uec_graceful_stop_rx()
172 ack = uec->p_rx_glbl_pram->rxgstpack; in uec_graceful_stop_rx()
175 uec->grace_stopped_rx = 1; in uec_graceful_stop_rx()
184 if (!uec || !uec->uec_info) { in uec_restart_tx()
186 return -EINVAL; in uec_restart_tx()
190 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); in uec_restart_tx()
194 uec->grace_stopped_tx = 0; in uec_restart_tx()
203 if (!uec || !uec->uec_info) { in uec_restart_rx()
205 return -EINVAL; in uec_restart_rx()
209 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); in uec_restart_rx()
213 uec->grace_stopped_rx = 0; in uec_restart_rx()
222 if (!uec || !uec->uccf) { in uec_open()
224 return -EINVAL; in uec_open()
226 uccf = uec->uccf; in uec_open()
229 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { in uec_open()
231 return -EINVAL; in uec_open()
241 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) { in uec_open()
244 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) { in uec_open()
253 if (!uec || !uec->uccf) { in uec_stop()
255 return -EINVAL; in uec_stop()
259 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { in uec_stop()
261 return -EINVAL; in uec_stop()
264 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) { in uec_stop()
268 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) { in uec_stop()
273 ucc_fast_disable(uec->uccf, mode); in uec_stop()
288 return -EINVAL; in uec_set_mac_duplex()
290 uec_regs = uec->uec_regs; in uec_set_mac_duplex()
293 maccfg2 = in_be32(&uec_regs->maccfg2); in uec_set_mac_duplex()
295 out_be32(&uec_regs->maccfg2, maccfg2); in uec_set_mac_duplex()
299 maccfg2 = in_be32(&uec_regs->maccfg2); in uec_set_mac_duplex()
301 out_be32(&uec_regs->maccfg2, maccfg2); in uec_set_mac_duplex()
317 return -EINVAL; in uec_set_mac_if_mode()
320 uec_regs = uec->uec_regs; in uec_set_mac_if_mode()
323 maccfg2 = in_be32(&uec_regs->maccfg2); in uec_set_mac_if_mode()
326 upsmr = in_be32(&uec->uccf->uf_regs->upsmr); in uec_set_mac_if_mode()
342 return -EINVAL; in uec_set_mac_if_mode()
358 return -EINVAL; in uec_set_mac_if_mode()
383 return -EINVAL; in uec_set_mac_if_mode()
388 return -EINVAL; in uec_set_mac_if_mode()
392 out_be32(&uec_regs->maccfg2, maccfg2); in uec_set_mac_if_mode()
393 out_be32(&uec->uccf->uf_regs->upsmr, upsmr); in uec_set_mac_if_mode()
403 miimcfg = in_be32(&uec_mii_regs->miimcfg); in init_mii_management_configuration()
405 out_be32(&uec_mii_regs->miimcfg, miimcfg); in init_mii_management_configuration()
408 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--); in init_mii_management_configuration()
411 return -ETIMEDOUT; in init_mii_management_configuration()
425 uec = (uec_private_t *)dev->priv; in init_phy()
426 umii_regs = uec->uec_mii_regs; in init_phy()
428 uec->oldlink = 0; in init_phy()
429 uec->oldspeed = 0; in init_phy()
430 uec->oldduplex = -1; in init_phy()
434 printf("%s: Could not allocate mii_info", dev->name); in init_phy()
435 return -ENOMEM; in init_phy()
439 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { in init_phy()
440 mii_info->speed = SPEED_1000; in init_phy()
442 mii_info->speed = SPEED_100; in init_phy()
445 mii_info->duplex = DUPLEX_FULL; in init_phy()
446 mii_info->pause = 0; in init_phy()
447 mii_info->link = 1; in init_phy()
449 mii_info->advertising = (ADVERTISED_10baseT_Half | in init_phy()
454 mii_info->autoneg = 1; in init_phy()
455 mii_info->mii_id = uec->uec_info->phy_address; in init_phy()
456 mii_info->dev = dev; in init_phy()
458 mii_info->mdio_read = &uec_read_phy_reg; in init_phy()
459 mii_info->mdio_write = &uec_write_phy_reg; in init_phy()
461 uec->mii_info = mii_info; in init_phy()
463 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num); in init_phy()
466 printf("%s: The MII Bus is stuck!", dev->name); in init_phy()
467 err = -1; in init_phy()
472 curphy = uec_get_phy_info(uec->mii_info); in init_phy()
474 printf("%s: No PHY found", dev->name); in init_phy()
475 err = -1; in init_phy()
479 mii_info->phyinfo = curphy; in init_phy()
482 if (curphy->init) { in init_phy()
483 err = curphy->init(uec->mii_info); in init_phy()
499 uec_private_t *uec = (uec_private_t *)dev->priv; in adjust_link()
500 struct uec_mii_info *mii_info = uec->mii_info; in adjust_link()
505 if (mii_info->link) { in adjust_link()
507 * If not, we operate in half-duplex mode. */ in adjust_link()
508 if (mii_info->duplex != uec->oldduplex) { in adjust_link()
509 if (!(mii_info->duplex)) { in adjust_link()
511 printf("%s: Half Duplex\n", dev->name); in adjust_link()
514 printf("%s: Full Duplex\n", dev->name); in adjust_link()
516 uec->oldduplex = mii_info->duplex; in adjust_link()
519 if (mii_info->speed != uec->oldspeed) { in adjust_link()
521 uec->uec_info->enet_interface_type; in adjust_link()
522 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { in adjust_link()
523 switch (mii_info->speed) { in adjust_link()
536 dev->name, mii_info->speed); in adjust_link()
542 change_phy_interface_mode(dev, mode, mii_info->speed); in adjust_link()
544 uec_set_mac_if_mode(uec, mode, mii_info->speed); in adjust_link()
546 printf("%s: Speed %dBT\n", dev->name, mii_info->speed); in adjust_link()
547 uec->oldspeed = mii_info->speed; in adjust_link()
550 if (!uec->oldlink) { in adjust_link()
551 printf("%s: Link is up\n", dev->name); in adjust_link()
552 uec->oldlink = 1; in adjust_link()
555 } else { /* if (mii_info->link) */ in adjust_link()
556 if (uec->oldlink) { in adjust_link()
557 printf("%s: Link is down\n", dev->name); in adjust_link()
558 uec->oldlink = 0; in adjust_link()
559 uec->oldspeed = 0; in adjust_link()
560 uec->oldduplex = -1; in adjust_link()
567 uec_private_t *uec = (uec_private_t *)dev->priv; in phy_change()
573 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); in phy_change()
574 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); in phy_change()
578 uec->mii_info->phyinfo->read_status(uec->mii_info); in phy_change()
585 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); in phy_change()
598 * The index where the device is located, -1 on error
605 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) { in uec_miiphy_find_dev_by_name()
610 /* If device cannot be found, returns -1 */ in uec_miiphy_find_dev_by_name()
613 i = -1; in uec_miiphy_find_dev_by_name()
630 if (bus->name == NULL) { in uec_miiphy_read()
633 devindex = uec_miiphy_find_dev_by_name(bus->name); in uec_miiphy_read()
652 if (bus->name == NULL) { in uec_miiphy_write()
655 devindex = uec_miiphy_find_dev_by_name(bus->name); in uec_miiphy_write()
672 return -EINVAL; in uec_set_mac_address()
675 uec_regs = uec->uec_regs; in uec_set_mac_address()
677 /* if a station address of 0x12345678ABCD, perform a write to in uec_set_mac_address()
683 out_be32(&uec_regs->macstnaddr1, mac_addr1); in uec_set_mac_address()
686 out_be32(&uec_regs->macstnaddr2, mac_addr2); in uec_set_mac_address()
715 return -EINVAL; in uec_convert_threads_num()
730 uec_info = uec->uec_info; in uec_init_tx_parameter()
733 uec->tx_glbl_pram_offset = qe_muram_alloc( in uec_init_tx_parameter()
736 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *) in uec_init_tx_parameter()
737 qe_muram_addr(uec->tx_glbl_pram_offset); in uec_init_tx_parameter()
740 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t)); in uec_init_tx_parameter()
745 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); in uec_init_tx_parameter()
748 uec->send_q_mem_reg_offset = qe_muram_alloc( in uec_init_tx_parameter()
751 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *) in uec_init_tx_parameter()
752 qe_muram_addr(uec->send_q_mem_reg_offset); in uec_init_tx_parameter()
753 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); in uec_init_tx_parameter()
756 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) in uec_init_tx_parameter()
758 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, in uec_init_tx_parameter()
759 (u32)(uec->p_tx_bd_ring)); in uec_init_tx_parameter()
760 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, in uec_init_tx_parameter()
764 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); in uec_init_tx_parameter()
767 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); in uec_init_tx_parameter()
771 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); in uec_init_tx_parameter()
775 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); in uec_init_tx_parameter()
780 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); in uec_init_tx_parameter()
784 uec->thread_dat_tx_offset = qe_muram_alloc( in uec_init_tx_parameter()
788 uec->p_thread_data_tx = (uec_thread_data_tx_t *) in uec_init_tx_parameter()
789 qe_muram_addr(uec->thread_dat_tx_offset); in uec_init_tx_parameter()
790 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); in uec_init_tx_parameter()
800 uec->rx_glbl_pram_offset = qe_muram_alloc( in uec_init_rx_parameter()
802 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *) in uec_init_rx_parameter()
803 qe_muram_addr(uec->rx_glbl_pram_offset); in uec_init_rx_parameter()
806 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t)); in uec_init_rx_parameter()
811 Extended address parsing mode disable, One Rx queues, in uec_init_rx_parameter()
813 disable, IP address alignment disable in uec_init_rx_parameter()
815 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); in uec_init_rx_parameter()
818 uec->thread_dat_rx_offset = qe_muram_alloc( in uec_init_rx_parameter()
821 uec->p_thread_data_rx = (uec_thread_data_rx_t *) in uec_init_rx_parameter()
822 qe_muram_addr(uec->thread_dat_rx_offset); in uec_init_rx_parameter()
823 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); in uec_init_rx_parameter()
826 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); in uec_init_rx_parameter()
829 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); in uec_init_rx_parameter()
832 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); in uec_init_rx_parameter()
836 out_8(&uec->p_rx_glbl_pram->rstate, bmrx); in uec_init_rx_parameter()
839 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); in uec_init_rx_parameter()
842 uec->rx_bd_qs_tbl_offset = qe_muram_alloc( in uec_init_rx_parameter()
846 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *) in uec_init_rx_parameter()
847 qe_muram_addr(uec->rx_bd_qs_tbl_offset); in uec_init_rx_parameter()
850 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \ in uec_init_rx_parameter()
852 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); in uec_init_rx_parameter()
853 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, in uec_init_rx_parameter()
854 (u32)uec->p_rx_bd_ring); in uec_init_rx_parameter()
857 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); in uec_init_rx_parameter()
859 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); in uec_init_rx_parameter()
861 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); in uec_init_rx_parameter()
863 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); in uec_init_rx_parameter()
865 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); in uec_init_rx_parameter()
867 out_be32(&uec->p_rx_glbl_pram->l2qt, 0); in uec_init_rx_parameter()
870 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); in uec_init_rx_parameter()
874 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); in uec_init_rx_parameter()
876 out_be16(&uec->p_rx_glbl_pram->vlantci, 0); in uec_init_rx_parameter()
878 /* Clear PQ2 style address filtering hash table */ in uec_init_rx_parameter()
880 uec->p_rx_glbl_pram->addressfiltering; in uec_init_rx_parameter()
882 p_af_pram->iaddr_h = 0; in uec_init_rx_parameter()
883 p_af_pram->iaddr_l = 0; in uec_init_rx_parameter()
884 p_af_pram->gaddr_h = 0; in uec_init_rx_parameter()
885 p_af_pram->gaddr_l = 0; in uec_init_rx_parameter()
901 uec_info = uec->uec_info; in uec_issue_init_enet_rxtx_cmd()
904 uec->init_enet_param_offset = qe_muram_alloc( in uec_issue_init_enet_rxtx_cmd()
906 init_enet_param_offset = uec->init_enet_param_offset; in uec_issue_init_enet_rxtx_cmd()
907 uec->p_init_enet_param = (uec_init_cmd_pram_t *) in uec_issue_init_enet_rxtx_cmd()
908 qe_muram_addr(uec->init_enet_param_offset); in uec_issue_init_enet_rxtx_cmd()
911 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t)); in uec_issue_init_enet_rxtx_cmd()
914 p_init_enet_param = uec->p_init_enet_param; in uec_issue_init_enet_rxtx_cmd()
915 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; in uec_issue_init_enet_rxtx_cmd()
916 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; in uec_issue_init_enet_rxtx_cmd()
917 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; in uec_issue_init_enet_rxtx_cmd()
918 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; in uec_issue_init_enet_rxtx_cmd()
919 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; in uec_issue_init_enet_rxtx_cmd()
920 p_init_enet_param->largestexternallookupkeysize = 0; in uec_issue_init_enet_rxtx_cmd()
922 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) in uec_issue_init_enet_rxtx_cmd()
924 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) in uec_issue_init_enet_rxtx_cmd()
928 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | in uec_issue_init_enet_rxtx_cmd()
929 (u32)uec_info->risc_rx; in uec_issue_init_enet_rxtx_cmd()
935 return -ENOMEM; in uec_issue_init_enet_rxtx_cmd()
947 init_enet_offset | (u32)uec_info->risc_rx; in uec_issue_init_enet_rxtx_cmd()
948 p_init_enet_param->rxthread[i] = entry_val; in uec_issue_init_enet_rxtx_cmd()
952 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | in uec_issue_init_enet_rxtx_cmd()
953 (u32)uec_info->risc_tx; in uec_issue_init_enet_rxtx_cmd()
959 return -ENOMEM; in uec_issue_init_enet_rxtx_cmd()
966 init_enet_offset | (u32)uec_info->risc_tx; in uec_issue_init_enet_rxtx_cmd()
967 p_init_enet_param->txthread[i] = entry_val; in uec_issue_init_enet_rxtx_cmd()
975 uec->uec_info->uf_info.ucc_num); in uec_issue_init_enet_rxtx_cmd()
994 qe_bd_t *bd; in uec_startup() local
998 if (!uec || !uec->uec_info) { in uec_startup()
1000 return -EINVAL; in uec_startup()
1003 uec_info = uec->uec_info; in uec_startup()
1004 uf_info = &(uec_info->uf_info); in uec_startup()
1006 /* Check if Rx BD ring len is illegal */ in uec_startup()
1007 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \ in uec_startup()
1008 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { in uec_startup()
1009 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", in uec_startup()
1011 return -EINVAL; in uec_startup()
1014 /* Check if Tx BD ring len is illegal */ in uec_startup()
1015 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { in uec_startup()
1016 printf("%s: Tx BD ring length must not be smaller than 2.\n", in uec_startup()
1018 return -EINVAL; in uec_startup()
1025 return -EINVAL; in uec_startup()
1029 uec->grace_stopped_rx = 1; in uec_startup()
1030 uec->grace_stopped_tx = 1; in uec_startup()
1035 return -ENOMEM; in uec_startup()
1039 uec->uccf = uccf; in uec_startup()
1042 if (uec_convert_threads_num(uec_info->num_threads_tx, in uec_startup()
1044 return -EINVAL; in uec_startup()
1048 if (uec_convert_threads_num(uec_info->num_threads_rx, in uec_startup()
1050 return -EINVAL; in uec_startup()
1053 uf_regs = uccf->uf_regs; in uec_startup()
1056 uec_regs = (uec_t *)(&uf_regs->ucc_eth); in uec_startup()
1059 uec->uec_regs = uec_regs; in uec_startup()
1062 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); in uec_startup()
1065 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); in uec_startup()
1068 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); in uec_startup()
1071 uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed); in uec_startup()
1075 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); in uec_startup()
1077 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS; in uec_startup()
1081 qe_set_mii_clk_src(uec_info->uf_info.ucc_num); in uec_startup()
1084 utbipar = in_be32(&uec_regs->utbipar); in uec_startup()
1087 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. in uec_startup()
1091 out_be32(&uec_regs->utbipar, utbipar); in uec_startup()
1094 if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) && in uec_startup()
1095 (uec->uec_info->speed == SPEED_1000)) { in uec_startup()
1096 uec_write_phy_reg(uec->dev, uec_regs->utbipar, in uec_startup()
1099 uec_write_phy_reg(uec->dev, uec_regs->utbipar, in uec_startup()
1102 uec_write_phy_reg(uec->dev, uec_regs->utbipar, in uec_startup()
1107 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / in uec_startup()
1110 if ((uec_info->tx_bd_ring_len * SIZEOFBD) % in uec_startup()
1116 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); in uec_startup()
1117 if (uec->tx_bd_ring_offset != 0) { in uec_startup()
1118 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) in uec_startup()
1119 & ~(align - 1)); in uec_startup()
1123 memset((void *)(uec->tx_bd_ring_offset), 0, length + align); in uec_startup()
1126 length = uec_info->rx_bd_ring_len * SIZEOFBD; in uec_startup()
1128 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); in uec_startup()
1129 if (uec->rx_bd_ring_offset != 0) { in uec_startup()
1130 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) in uec_startup()
1131 & ~(align - 1)); in uec_startup()
1135 memset((void *)(uec->rx_bd_ring_offset), 0, length + align); in uec_startup()
1138 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; in uec_startup()
1140 uec->rx_buf_offset = (u32)malloc(length + align); in uec_startup()
1141 if (uec->rx_buf_offset != 0) { in uec_startup()
1142 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) in uec_startup()
1143 & ~(align - 1)); in uec_startup()
1147 memset((void *)(uec->rx_buf_offset), 0, length + align); in uec_startup()
1150 bd = (qe_bd_t *)uec->p_tx_bd_ring; in uec_startup()
1151 uec->txBd = bd; in uec_startup()
1153 for (i = 0; i < uec_info->tx_bd_ring_len; i++) { in uec_startup()
1154 BD_DATA_CLEAR(bd); in uec_startup()
1155 BD_STATUS_SET(bd, 0); in uec_startup()
1156 BD_LENGTH_SET(bd, 0); in uec_startup()
1157 bd ++; in uec_startup()
1159 BD_STATUS_SET((--bd), TxBD_WRAP); in uec_startup()
1162 bd = (qe_bd_t *)uec->p_rx_bd_ring; in uec_startup()
1163 uec->rxBd = bd; in uec_startup()
1164 buf = uec->p_rx_buf; in uec_startup()
1165 for (i = 0; i < uec_info->rx_bd_ring_len; i++) { in uec_startup()
1166 BD_DATA_SET(bd, buf); in uec_startup()
1167 BD_LENGTH_SET(bd, 0); in uec_startup()
1168 BD_STATUS_SET(bd, RxBD_EMPTY); in uec_startup()
1170 bd ++; in uec_startup()
1172 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY); in uec_startup()
1184 return -ENOMEM; in uec_startup()
1190 static int uec_init(struct eth_device* dev, bd_t *bd) in uec_init() argument
1199 uec = (uec_private_t *)dev->priv; in uec_init()
1201 if (uec->the_first_run == 0) { in uec_init()
1204 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); in uec_init()
1205 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); in uec_init()
1211 dev->name); in uec_init()
1215 curphy = uec->mii_info->phyinfo; in uec_init()
1217 if (curphy->config_aneg) { in uec_init()
1218 err = curphy->config_aneg(uec->mii_info); in uec_init()
1220 printf("%s: Can't negotiate PHY\n", dev->name); in uec_init()
1228 err = curphy->read_status(uec->mii_info); in uec_init()
1229 if (!(((i-- > 0) && !uec->mii_info->link) || err)) in uec_init()
1236 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); in uec_init()
1240 printf("warning: %s: timeout on PHY link\n", dev->name); in uec_init()
1243 uec->the_first_run = 1; in uec_init()
1246 /* Set up the MAC address */ in uec_init()
1247 if (dev->enetaddr[0] & 0x01) { in uec_init()
1248 printf("%s: MacAddress is multcast address\n", in uec_init()
1250 return -1; in uec_init()
1252 uec_set_mac_address(uec, dev->enetaddr); in uec_init()
1257 printf("%s: cannot enable UEC device\n", dev->name); in uec_init()
1258 return -1; in uec_init()
1263 return (uec->mii_info->link ? 0 : -1); in uec_init()
1268 uec_private_t *uec = (uec_private_t *)dev->priv; in uec_halt()
1276 volatile qe_bd_t *bd; in uec_send() local
1281 uec = (uec_private_t *)dev->priv; in uec_send()
1282 uccf = uec->uccf; in uec_send()
1283 bd = uec->txBd; in uec_send()
1286 for (i = 0; bd->status & TxBD_READY; i++) { in uec_send()
1288 printf("%s: tx buffer not ready\n", dev->name); in uec_send()
1294 BD_DATA_SET(bd, buf); in uec_send()
1295 BD_LENGTH_SET(bd, len); in uec_send()
1296 status = bd->status; in uec_send()
1299 BD_STATUS_SET(bd, status); in uec_send()
1305 for (i = 0; bd->status & TxBD_READY; i++) { in uec_send()
1307 printf("%s: tx error\n", dev->name); in uec_send()
1313 BD_ADVANCE(bd, status, uec->p_tx_bd_ring); in uec_send()
1314 uec->txBd = bd; in uec_send()
1322 uec_private_t *uec = dev->priv; in uec_recv()
1323 volatile qe_bd_t *bd; in uec_recv() local
1328 bd = uec->rxBd; in uec_recv()
1329 status = bd->status; in uec_recv()
1333 data = BD_DATA(bd); in uec_recv()
1334 len = BD_LENGTH(bd); in uec_recv()
1337 printf("%s: Rx error\n", dev->name); in uec_recv()
1340 BD_LENGTH_SET(bd, 0); in uec_recv()
1341 BD_STATUS_SET(bd, status | RxBD_EMPTY); in uec_recv()
1342 BD_ADVANCE(bd, status, uec->p_rx_bd_ring); in uec_recv()
1343 status = bd->status; in uec_recv()
1345 uec->rxBd = bd; in uec_recv()
1365 return -ENOMEM; in uec_initialize()
1371 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS; in uec_initialize()
1372 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS; in uec_initialize()
1375 devlist[uec_info->uf_info.ucc_num] = dev; in uec_initialize()
1377 uec->uec_info = uec_info; in uec_initialize()
1378 uec->dev = dev; in uec_initialize()
1380 sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num); in uec_initialize()
1381 dev->iobase = 0; in uec_initialize()
1382 dev->priv = (void *)uec; in uec_initialize()
1383 dev->init = uec_init; in uec_initialize()
1384 dev->halt = uec_halt; in uec_initialize()
1385 dev->send = uec_send; in uec_initialize()
1386 dev->recv = uec_recv; in uec_initialize()
1388 /* Clear the ethnet address */ in uec_initialize()
1390 dev->enetaddr[i] = 0; in uec_initialize()
1396 printf("%s: Cannot configure net device, aborting.",dev->name); in uec_initialize()
1404 return -ENOMEM; in uec_initialize()
1405 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); in uec_initialize()
1406 mdiodev->read = uec_miiphy_read; in uec_initialize()
1407 mdiodev->write = uec_miiphy_write; in uec_initialize()