1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
24f1ec4c1SMichal Simek /*
34f1ec4c1SMichal Simek * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
44f1ec4c1SMichal Simek * Copyright (C) 2011 PetaLogix
54f1ec4c1SMichal Simek * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
64f1ec4c1SMichal Simek */
74f1ec4c1SMichal Simek
84f1ec4c1SMichal Simek #include <config.h>
94f1ec4c1SMichal Simek #include <common.h>
1075cc93faSMichal Simek #include <dm.h>
114f1ec4c1SMichal Simek #include <net.h>
124f1ec4c1SMichal Simek #include <malloc.h>
134f1ec4c1SMichal Simek #include <asm/io.h>
144f1ec4c1SMichal Simek #include <phy.h>
154f1ec4c1SMichal Simek #include <miiphy.h>
16d02a0b1fSSiva Durga Prasad Paladugu #include <wait_bit.h>
174f1ec4c1SMichal Simek
1875cc93faSMichal Simek DECLARE_GLOBAL_DATA_PTR;
1975cc93faSMichal Simek
204f1ec4c1SMichal Simek /* Link setup */
214f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
224f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
234f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
244f1ec4c1SMichal Simek #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
254f1ec4c1SMichal Simek
264f1ec4c1SMichal Simek /* Interrupt Status/Enable/Mask Registers bit definitions */
274f1ec4c1SMichal Simek #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
284f1ec4c1SMichal Simek #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
294f1ec4c1SMichal Simek
304f1ec4c1SMichal Simek /* Receive Configuration Word 1 (RCW1) Register bit definitions */
314f1ec4c1SMichal Simek #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
324f1ec4c1SMichal Simek
334f1ec4c1SMichal Simek /* Transmitter Configuration (TC) Register bit definitions */
344f1ec4c1SMichal Simek #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
354f1ec4c1SMichal Simek
364f1ec4c1SMichal Simek #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
374f1ec4c1SMichal Simek
384f1ec4c1SMichal Simek /* MDIO Management Configuration (MC) Register bit definitions */
394f1ec4c1SMichal Simek #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
404f1ec4c1SMichal Simek
414f1ec4c1SMichal Simek /* MDIO Management Control Register (MCR) Register bit definitions */
424f1ec4c1SMichal Simek #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
434f1ec4c1SMichal Simek #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
444f1ec4c1SMichal Simek #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
454f1ec4c1SMichal Simek #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
464f1ec4c1SMichal Simek #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
474f1ec4c1SMichal Simek #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
484f1ec4c1SMichal Simek #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
494f1ec4c1SMichal Simek #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
504f1ec4c1SMichal Simek
514f1ec4c1SMichal Simek #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
524f1ec4c1SMichal Simek
5389ce5a9dSSiva Durga Prasad Paladugu #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
5489ce5a9dSSiva Durga Prasad Paladugu
554f1ec4c1SMichal Simek /* DMA macros */
564f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_CR_OFFSET register */
574f1ec4c1SMichal Simek #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
584f1ec4c1SMichal Simek #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
594f1ec4c1SMichal Simek
604f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_SR_OFFSET register */
614f1ec4c1SMichal Simek #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
624f1ec4c1SMichal Simek
634f1ec4c1SMichal Simek /* Bitmask for interrupts */
644f1ec4c1SMichal Simek #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
654f1ec4c1SMichal Simek #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
664f1ec4c1SMichal Simek #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
674f1ec4c1SMichal Simek
684f1ec4c1SMichal Simek /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
694f1ec4c1SMichal Simek #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
704f1ec4c1SMichal Simek #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
714f1ec4c1SMichal Simek
724f1ec4c1SMichal Simek #define DMAALIGN 128
734f1ec4c1SMichal Simek
744f1ec4c1SMichal Simek static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
754f1ec4c1SMichal Simek
764f1ec4c1SMichal Simek /* Reflect dma offsets */
774f1ec4c1SMichal Simek struct axidma_reg {
784f1ec4c1SMichal Simek u32 control; /* DMACR */
794f1ec4c1SMichal Simek u32 status; /* DMASR */
80047f3bf8SVipul Kumar u32 current; /* CURDESC low 32 bit */
81047f3bf8SVipul Kumar u32 current_hi; /* CURDESC high 32 bit */
82047f3bf8SVipul Kumar u32 tail; /* TAILDESC low 32 bit */
83047f3bf8SVipul Kumar u32 tail_hi; /* TAILDESC high 32 bit */
844f1ec4c1SMichal Simek };
854f1ec4c1SMichal Simek
864f1ec4c1SMichal Simek /* Private driver structures */
874f1ec4c1SMichal Simek struct axidma_priv {
884f1ec4c1SMichal Simek struct axidma_reg *dmatx;
894f1ec4c1SMichal Simek struct axidma_reg *dmarx;
904f1ec4c1SMichal Simek int phyaddr;
916609f35bSMichal Simek struct axi_regs *iobase;
9275cc93faSMichal Simek phy_interface_t interface;
934f1ec4c1SMichal Simek struct phy_device *phydev;
944f1ec4c1SMichal Simek struct mii_dev *bus;
9589ce5a9dSSiva Durga Prasad Paladugu u8 eth_hasnobuf;
964f1ec4c1SMichal Simek };
974f1ec4c1SMichal Simek
984f1ec4c1SMichal Simek /* BD descriptors */
994f1ec4c1SMichal Simek struct axidma_bd {
1004f1ec4c1SMichal Simek u32 next; /* Next descriptor pointer */
1014f1ec4c1SMichal Simek u32 reserved1;
1024f1ec4c1SMichal Simek u32 phys; /* Buffer address */
1034f1ec4c1SMichal Simek u32 reserved2;
1044f1ec4c1SMichal Simek u32 reserved3;
1054f1ec4c1SMichal Simek u32 reserved4;
1064f1ec4c1SMichal Simek u32 cntrl; /* Control */
1074f1ec4c1SMichal Simek u32 status; /* Status */
1084f1ec4c1SMichal Simek u32 app0;
1094f1ec4c1SMichal Simek u32 app1; /* TX start << 16 | insert */
1104f1ec4c1SMichal Simek u32 app2; /* TX csum seed */
1114f1ec4c1SMichal Simek u32 app3;
1124f1ec4c1SMichal Simek u32 app4;
1134f1ec4c1SMichal Simek u32 sw_id_offset;
1144f1ec4c1SMichal Simek u32 reserved5;
1154f1ec4c1SMichal Simek u32 reserved6;
1164f1ec4c1SMichal Simek };
1174f1ec4c1SMichal Simek
1184f1ec4c1SMichal Simek /* Static BDs - driver uses only one BD */
1194f1ec4c1SMichal Simek static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
1204f1ec4c1SMichal Simek static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
1214f1ec4c1SMichal Simek
1224f1ec4c1SMichal Simek struct axi_regs {
1234f1ec4c1SMichal Simek u32 reserved[3];
1244f1ec4c1SMichal Simek u32 is; /* 0xC: Interrupt status */
1254f1ec4c1SMichal Simek u32 reserved2;
1264f1ec4c1SMichal Simek u32 ie; /* 0x14: Interrupt enable */
1274f1ec4c1SMichal Simek u32 reserved3[251];
1284f1ec4c1SMichal Simek u32 rcw1; /* 0x404: Rx Configuration Word 1 */
1294f1ec4c1SMichal Simek u32 tc; /* 0x408: Tx Configuration */
1304f1ec4c1SMichal Simek u32 reserved4;
1314f1ec4c1SMichal Simek u32 emmc; /* 0x410: EMAC mode configuration */
1324f1ec4c1SMichal Simek u32 reserved5[59];
1334f1ec4c1SMichal Simek u32 mdio_mc; /* 0x500: MII Management Config */
1344f1ec4c1SMichal Simek u32 mdio_mcr; /* 0x504: MII Management Control */
1354f1ec4c1SMichal Simek u32 mdio_mwd; /* 0x508: MII Management Write Data */
1364f1ec4c1SMichal Simek u32 mdio_mrd; /* 0x50C: MII Management Read Data */
1374f1ec4c1SMichal Simek u32 reserved6[124];
1384f1ec4c1SMichal Simek u32 uaw0; /* 0x700: Unicast address word 0 */
1394f1ec4c1SMichal Simek u32 uaw1; /* 0x704: Unicast address word 1 */
1404f1ec4c1SMichal Simek };
1414f1ec4c1SMichal Simek
1424f1ec4c1SMichal Simek /* Use MII register 1 (MII status register) to detect PHY */
1434f1ec4c1SMichal Simek #define PHY_DETECT_REG 1
1444f1ec4c1SMichal Simek
1454f1ec4c1SMichal Simek /*
1464f1ec4c1SMichal Simek * Mask used to verify certain PHY features (or register contents)
1474f1ec4c1SMichal Simek * in the register above:
1484f1ec4c1SMichal Simek * 0x1000: 10Mbps full duplex support
1494f1ec4c1SMichal Simek * 0x0800: 10Mbps half duplex support
1504f1ec4c1SMichal Simek * 0x0008: Auto-negotiation support
1514f1ec4c1SMichal Simek */
1524f1ec4c1SMichal Simek #define PHY_DETECT_MASK 0x1808
1534f1ec4c1SMichal Simek
mdio_wait(struct axi_regs * regs)154f36bbcceSMichal Simek static inline int mdio_wait(struct axi_regs *regs)
1554f1ec4c1SMichal Simek {
1564f1ec4c1SMichal Simek u32 timeout = 200;
1574f1ec4c1SMichal Simek
1584f1ec4c1SMichal Simek /* Wait till MDIO interface is ready to accept a new transaction. */
159a04a5daaSSiva Durga Prasad Paladugu while (timeout && (!(readl(®s->mdio_mcr)
1604f1ec4c1SMichal Simek & XAE_MDIO_MCR_READY_MASK))) {
1614f1ec4c1SMichal Simek timeout--;
1624f1ec4c1SMichal Simek udelay(1);
1634f1ec4c1SMichal Simek }
1644f1ec4c1SMichal Simek if (!timeout) {
1654f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__);
1664f1ec4c1SMichal Simek return 1;
1674f1ec4c1SMichal Simek }
1684f1ec4c1SMichal Simek return 0;
1694f1ec4c1SMichal Simek }
1704f1ec4c1SMichal Simek
171047f3bf8SVipul Kumar /**
172047f3bf8SVipul Kumar * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
173047f3bf8SVipul Kumar * @bd: pointer to BD descriptor structure
174047f3bf8SVipul Kumar * @desc: Address offset of DMA descriptors
175047f3bf8SVipul Kumar *
176047f3bf8SVipul Kumar * This function writes the value into the corresponding Axi DMA register.
177047f3bf8SVipul Kumar */
axienet_dma_write(struct axidma_bd * bd,u32 * desc)178047f3bf8SVipul Kumar static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
179047f3bf8SVipul Kumar {
180047f3bf8SVipul Kumar #if defined(CONFIG_PHYS_64BIT)
181047f3bf8SVipul Kumar writeq(bd, desc);
182047f3bf8SVipul Kumar #else
183047f3bf8SVipul Kumar writel((u32)bd, desc);
184047f3bf8SVipul Kumar #endif
185047f3bf8SVipul Kumar }
186047f3bf8SVipul Kumar
phyread(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u16 * val)1870d78abf5SMichal Simek static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
1884f1ec4c1SMichal Simek u16 *val)
1894f1ec4c1SMichal Simek {
1900d78abf5SMichal Simek struct axi_regs *regs = priv->iobase;
1914f1ec4c1SMichal Simek u32 mdioctrlreg = 0;
1924f1ec4c1SMichal Simek
193f36bbcceSMichal Simek if (mdio_wait(regs))
1944f1ec4c1SMichal Simek return 1;
1954f1ec4c1SMichal Simek
1964f1ec4c1SMichal Simek mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
1974f1ec4c1SMichal Simek XAE_MDIO_MCR_PHYAD_MASK) |
1984f1ec4c1SMichal Simek ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
1994f1ec4c1SMichal Simek & XAE_MDIO_MCR_REGAD_MASK) |
2004f1ec4c1SMichal Simek XAE_MDIO_MCR_INITIATE_MASK |
2014f1ec4c1SMichal Simek XAE_MDIO_MCR_OP_READ_MASK;
2024f1ec4c1SMichal Simek
203a04a5daaSSiva Durga Prasad Paladugu writel(mdioctrlreg, ®s->mdio_mcr);
2044f1ec4c1SMichal Simek
205f36bbcceSMichal Simek if (mdio_wait(regs))
2064f1ec4c1SMichal Simek return 1;
2074f1ec4c1SMichal Simek
2084f1ec4c1SMichal Simek /* Read data */
209a04a5daaSSiva Durga Prasad Paladugu *val = readl(®s->mdio_mrd);
2104f1ec4c1SMichal Simek return 0;
2114f1ec4c1SMichal Simek }
2124f1ec4c1SMichal Simek
phywrite(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u32 data)2130d78abf5SMichal Simek static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
2144f1ec4c1SMichal Simek u32 data)
2154f1ec4c1SMichal Simek {
2160d78abf5SMichal Simek struct axi_regs *regs = priv->iobase;
2174f1ec4c1SMichal Simek u32 mdioctrlreg = 0;
2184f1ec4c1SMichal Simek
219f36bbcceSMichal Simek if (mdio_wait(regs))
2204f1ec4c1SMichal Simek return 1;
2214f1ec4c1SMichal Simek
2224f1ec4c1SMichal Simek mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
2234f1ec4c1SMichal Simek XAE_MDIO_MCR_PHYAD_MASK) |
2244f1ec4c1SMichal Simek ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
2254f1ec4c1SMichal Simek & XAE_MDIO_MCR_REGAD_MASK) |
2264f1ec4c1SMichal Simek XAE_MDIO_MCR_INITIATE_MASK |
2274f1ec4c1SMichal Simek XAE_MDIO_MCR_OP_WRITE_MASK;
2284f1ec4c1SMichal Simek
2294f1ec4c1SMichal Simek /* Write data */
230a04a5daaSSiva Durga Prasad Paladugu writel(data, ®s->mdio_mwd);
2314f1ec4c1SMichal Simek
232a04a5daaSSiva Durga Prasad Paladugu writel(mdioctrlreg, ®s->mdio_mcr);
2334f1ec4c1SMichal Simek
234f36bbcceSMichal Simek if (mdio_wait(regs))
2354f1ec4c1SMichal Simek return 1;
2364f1ec4c1SMichal Simek
2374f1ec4c1SMichal Simek return 0;
2384f1ec4c1SMichal Simek }
2394f1ec4c1SMichal Simek
axiemac_phy_init(struct udevice * dev)2405d0449d4SMichal Simek static int axiemac_phy_init(struct udevice *dev)
2414f1ec4c1SMichal Simek {
2424f1ec4c1SMichal Simek u16 phyreg;
2435d0449d4SMichal Simek u32 i, ret;
24475cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
2456609f35bSMichal Simek struct axi_regs *regs = priv->iobase;
2464f1ec4c1SMichal Simek struct phy_device *phydev;
2474f1ec4c1SMichal Simek
2484f1ec4c1SMichal Simek u32 supported = SUPPORTED_10baseT_Half |
2494f1ec4c1SMichal Simek SUPPORTED_10baseT_Full |
2504f1ec4c1SMichal Simek SUPPORTED_100baseT_Half |
2514f1ec4c1SMichal Simek SUPPORTED_100baseT_Full |
2524f1ec4c1SMichal Simek SUPPORTED_1000baseT_Half |
2534f1ec4c1SMichal Simek SUPPORTED_1000baseT_Full;
2544f1ec4c1SMichal Simek
2555d0449d4SMichal Simek /* Set default MDIO divisor */
256a04a5daaSSiva Durga Prasad Paladugu writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
2575d0449d4SMichal Simek
2584f1ec4c1SMichal Simek if (priv->phyaddr == -1) {
2594f1ec4c1SMichal Simek /* Detect the PHY address */
2604f1ec4c1SMichal Simek for (i = 31; i >= 0; i--) {
2610d78abf5SMichal Simek ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
2624f1ec4c1SMichal Simek if (!ret && (phyreg != 0xFFFF) &&
2634f1ec4c1SMichal Simek ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
2644f1ec4c1SMichal Simek /* Found a valid PHY address */
2654f1ec4c1SMichal Simek priv->phyaddr = i;
2664f1ec4c1SMichal Simek debug("axiemac: Found valid phy address, %x\n",
2672652a621SMichal Simek i);
2684f1ec4c1SMichal Simek break;
2694f1ec4c1SMichal Simek }
2704f1ec4c1SMichal Simek }
2714f1ec4c1SMichal Simek }
2724f1ec4c1SMichal Simek
2734f1ec4c1SMichal Simek /* Interface - look at tsec */
2749c0da762SSiva Durga Prasad Paladugu phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
2754f1ec4c1SMichal Simek
2764f1ec4c1SMichal Simek phydev->supported &= supported;
2774f1ec4c1SMichal Simek phydev->advertising = phydev->supported;
2784f1ec4c1SMichal Simek priv->phydev = phydev;
2794f1ec4c1SMichal Simek phy_config(phydev);
2805d0449d4SMichal Simek
2815d0449d4SMichal Simek return 0;
2825d0449d4SMichal Simek }
2835d0449d4SMichal Simek
2845d0449d4SMichal Simek /* Setting axi emac and phy to proper setting */
setup_phy(struct udevice * dev)2855d0449d4SMichal Simek static int setup_phy(struct udevice *dev)
2865d0449d4SMichal Simek {
2878964f241SSiva Durga Prasad Paladugu u16 temp;
2888964f241SSiva Durga Prasad Paladugu u32 speed, emmc_reg, ret;
2895d0449d4SMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
2905d0449d4SMichal Simek struct axi_regs *regs = priv->iobase;
2915d0449d4SMichal Simek struct phy_device *phydev = priv->phydev;
2925d0449d4SMichal Simek
2938964f241SSiva Durga Prasad Paladugu if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
2948964f241SSiva Durga Prasad Paladugu /*
2958964f241SSiva Durga Prasad Paladugu * In SGMII cases the isolate bit might set
2968964f241SSiva Durga Prasad Paladugu * after DMA and ethernet resets and hence
2978964f241SSiva Durga Prasad Paladugu * check and clear if set.
2988964f241SSiva Durga Prasad Paladugu */
2998964f241SSiva Durga Prasad Paladugu ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
3008964f241SSiva Durga Prasad Paladugu if (ret)
3018964f241SSiva Durga Prasad Paladugu return 0;
3028964f241SSiva Durga Prasad Paladugu if (temp & BMCR_ISOLATE) {
3038964f241SSiva Durga Prasad Paladugu temp &= ~BMCR_ISOLATE;
3048964f241SSiva Durga Prasad Paladugu ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
3058964f241SSiva Durga Prasad Paladugu if (ret)
3068964f241SSiva Durga Prasad Paladugu return 0;
3078964f241SSiva Durga Prasad Paladugu }
3088964f241SSiva Durga Prasad Paladugu }
3098964f241SSiva Durga Prasad Paladugu
31011af8d65STimur Tabi if (phy_startup(phydev)) {
31111af8d65STimur Tabi printf("axiemac: could not initialize PHY %s\n",
31211af8d65STimur Tabi phydev->dev->name);
31311af8d65STimur Tabi return 0;
31411af8d65STimur Tabi }
3156f9b9372SMichal Simek if (!phydev->link) {
3166f9b9372SMichal Simek printf("%s: No link.\n", phydev->dev->name);
3176f9b9372SMichal Simek return 0;
3186f9b9372SMichal Simek }
3194f1ec4c1SMichal Simek
3204f1ec4c1SMichal Simek switch (phydev->speed) {
3214f1ec4c1SMichal Simek case 1000:
3224f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_1000;
3234f1ec4c1SMichal Simek break;
3244f1ec4c1SMichal Simek case 100:
3254f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_100;
3264f1ec4c1SMichal Simek break;
3274f1ec4c1SMichal Simek case 10:
3284f1ec4c1SMichal Simek speed = XAE_EMMC_LINKSPD_10;
3294f1ec4c1SMichal Simek break;
3304f1ec4c1SMichal Simek default:
3314f1ec4c1SMichal Simek return 0;
3324f1ec4c1SMichal Simek }
3334f1ec4c1SMichal Simek
3344f1ec4c1SMichal Simek /* Setup the emac for the phy speed */
335a04a5daaSSiva Durga Prasad Paladugu emmc_reg = readl(®s->emmc);
3364f1ec4c1SMichal Simek emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
3374f1ec4c1SMichal Simek emmc_reg |= speed;
3384f1ec4c1SMichal Simek
3394f1ec4c1SMichal Simek /* Write new speed setting out to Axi Ethernet */
340a04a5daaSSiva Durga Prasad Paladugu writel(emmc_reg, ®s->emmc);
3414f1ec4c1SMichal Simek
3424f1ec4c1SMichal Simek /*
3434f1ec4c1SMichal Simek * Setting the operating speed of the MAC needs a delay. There
3444f1ec4c1SMichal Simek * doesn't seem to be register to poll, so please consider this
3454f1ec4c1SMichal Simek * during your application design.
3464f1ec4c1SMichal Simek */
3474f1ec4c1SMichal Simek udelay(1);
3484f1ec4c1SMichal Simek
3494f1ec4c1SMichal Simek return 1;
3504f1ec4c1SMichal Simek }
3514f1ec4c1SMichal Simek
3524f1ec4c1SMichal Simek /* STOP DMA transfers */
axiemac_stop(struct udevice * dev)353ad499e42SMichal Simek static void axiemac_stop(struct udevice *dev)
3544f1ec4c1SMichal Simek {
35575cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
3564f1ec4c1SMichal Simek u32 temp;
3574f1ec4c1SMichal Simek
3584f1ec4c1SMichal Simek /* Stop the hardware */
359a04a5daaSSiva Durga Prasad Paladugu temp = readl(&priv->dmatx->control);
3604f1ec4c1SMichal Simek temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
361a04a5daaSSiva Durga Prasad Paladugu writel(temp, &priv->dmatx->control);
3624f1ec4c1SMichal Simek
363a04a5daaSSiva Durga Prasad Paladugu temp = readl(&priv->dmarx->control);
3644f1ec4c1SMichal Simek temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
365a04a5daaSSiva Durga Prasad Paladugu writel(temp, &priv->dmarx->control);
3664f1ec4c1SMichal Simek
3674f1ec4c1SMichal Simek debug("axiemac: Halted\n");
3684f1ec4c1SMichal Simek }
3694f1ec4c1SMichal Simek
axi_ethernet_init(struct axidma_priv * priv)370f0985481SMichal Simek static int axi_ethernet_init(struct axidma_priv *priv)
3714f1ec4c1SMichal Simek {
372f0985481SMichal Simek struct axi_regs *regs = priv->iobase;
373d02a0b1fSSiva Durga Prasad Paladugu int err;
3744f1ec4c1SMichal Simek
3754f1ec4c1SMichal Simek /*
3764f1ec4c1SMichal Simek * Check the status of the MgtRdy bit in the interrupt status
3774f1ec4c1SMichal Simek * registers. This must be done to allow the MGT clock to become stable
3784f1ec4c1SMichal Simek * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
3794f1ec4c1SMichal Simek * will be valid until this bit is valid.
3804f1ec4c1SMichal Simek * The bit is always a 1 for all other PHY interfaces.
38189ce5a9dSSiva Durga Prasad Paladugu * Interrupt status and enable registers are not available in non
38289ce5a9dSSiva Durga Prasad Paladugu * processor mode and hence bypass in this mode
3834f1ec4c1SMichal Simek */
38489ce5a9dSSiva Durga Prasad Paladugu if (!priv->eth_hasnobuf) {
38548263504SÁlvaro Fernández Rojas err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
38648263504SÁlvaro Fernández Rojas true, 200, false);
387d02a0b1fSSiva Durga Prasad Paladugu if (err) {
3884f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__);
3894f1ec4c1SMichal Simek return 1;
3904f1ec4c1SMichal Simek }
3914f1ec4c1SMichal Simek
39289ce5a9dSSiva Durga Prasad Paladugu /*
39389ce5a9dSSiva Durga Prasad Paladugu * Stop the device and reset HW
39489ce5a9dSSiva Durga Prasad Paladugu * Disable interrupts
39589ce5a9dSSiva Durga Prasad Paladugu */
396a04a5daaSSiva Durga Prasad Paladugu writel(0, ®s->ie);
39789ce5a9dSSiva Durga Prasad Paladugu }
3984f1ec4c1SMichal Simek
3994f1ec4c1SMichal Simek /* Disable the receiver */
400a04a5daaSSiva Durga Prasad Paladugu writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
4014f1ec4c1SMichal Simek
4024f1ec4c1SMichal Simek /*
4034f1ec4c1SMichal Simek * Stopping the receiver in mid-packet causes a dropped packet
4044f1ec4c1SMichal Simek * indication from HW. Clear it.
4054f1ec4c1SMichal Simek */
40689ce5a9dSSiva Durga Prasad Paladugu if (!priv->eth_hasnobuf) {
4074f1ec4c1SMichal Simek /* Set the interrupt status register to clear the interrupt */
408a04a5daaSSiva Durga Prasad Paladugu writel(XAE_INT_RXRJECT_MASK, ®s->is);
40989ce5a9dSSiva Durga Prasad Paladugu }
4104f1ec4c1SMichal Simek
4114f1ec4c1SMichal Simek /* Setup HW */
4124f1ec4c1SMichal Simek /* Set default MDIO divisor */
413a04a5daaSSiva Durga Prasad Paladugu writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
4144f1ec4c1SMichal Simek
4154f1ec4c1SMichal Simek debug("axiemac: InitHw done\n");
4164f1ec4c1SMichal Simek return 0;
4174f1ec4c1SMichal Simek }
4184f1ec4c1SMichal Simek
axiemac_write_hwaddr(struct udevice * dev)419ad499e42SMichal Simek static int axiemac_write_hwaddr(struct udevice *dev)
4204f1ec4c1SMichal Simek {
42175cc93faSMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev);
42275cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
42375cc93faSMichal Simek struct axi_regs *regs = priv->iobase;
4244f1ec4c1SMichal Simek
4254f1ec4c1SMichal Simek /* Set the MAC address */
42675cc93faSMichal Simek int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
42775cc93faSMichal Simek (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
428a04a5daaSSiva Durga Prasad Paladugu writel(val, ®s->uaw0);
4294f1ec4c1SMichal Simek
43075cc93faSMichal Simek val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
431a04a5daaSSiva Durga Prasad Paladugu val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
432a04a5daaSSiva Durga Prasad Paladugu writel(val, ®s->uaw1);
4334f1ec4c1SMichal Simek return 0;
4344f1ec4c1SMichal Simek }
4354f1ec4c1SMichal Simek
4364f1ec4c1SMichal Simek /* Reset DMA engine */
axi_dma_init(struct axidma_priv * priv)437f0985481SMichal Simek static void axi_dma_init(struct axidma_priv *priv)
4384f1ec4c1SMichal Simek {
4394f1ec4c1SMichal Simek u32 timeout = 500;
4404f1ec4c1SMichal Simek
4414f1ec4c1SMichal Simek /* Reset the engine so the hardware starts from a known state */
442a04a5daaSSiva Durga Prasad Paladugu writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
443a04a5daaSSiva Durga Prasad Paladugu writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
4444f1ec4c1SMichal Simek
4454f1ec4c1SMichal Simek /* At the initialization time, hardware should finish reset quickly */
4464f1ec4c1SMichal Simek while (timeout--) {
4474f1ec4c1SMichal Simek /* Check transmit/receive channel */
4484f1ec4c1SMichal Simek /* Reset is done when the reset bit is low */
449a04a5daaSSiva Durga Prasad Paladugu if (!((readl(&priv->dmatx->control) |
450a04a5daaSSiva Durga Prasad Paladugu readl(&priv->dmarx->control))
4513e3f8ba2SMichal Simek & XAXIDMA_CR_RESET_MASK)) {
4524f1ec4c1SMichal Simek break;
4534f1ec4c1SMichal Simek }
4544f1ec4c1SMichal Simek }
4554f1ec4c1SMichal Simek if (!timeout)
4564f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__);
4574f1ec4c1SMichal Simek }
4584f1ec4c1SMichal Simek
axiemac_start(struct udevice * dev)459ad499e42SMichal Simek static int axiemac_start(struct udevice *dev)
4604f1ec4c1SMichal Simek {
46175cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
46275cc93faSMichal Simek struct axi_regs *regs = priv->iobase;
4634f1ec4c1SMichal Simek u32 temp;
4644f1ec4c1SMichal Simek
4654f1ec4c1SMichal Simek debug("axiemac: Init started\n");
4664f1ec4c1SMichal Simek /*
4674f1ec4c1SMichal Simek * Initialize AXIDMA engine. AXIDMA engine must be initialized before
4684f1ec4c1SMichal Simek * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
4694f1ec4c1SMichal Simek * reset, and since AXIDMA reset line is connected to AxiEthernet, this
4704f1ec4c1SMichal Simek * would ensure a reset of AxiEthernet.
4714f1ec4c1SMichal Simek */
472f0985481SMichal Simek axi_dma_init(priv);
4734f1ec4c1SMichal Simek
4744f1ec4c1SMichal Simek /* Initialize AxiEthernet hardware. */
475f0985481SMichal Simek if (axi_ethernet_init(priv))
4764f1ec4c1SMichal Simek return -1;
4774f1ec4c1SMichal Simek
4784f1ec4c1SMichal Simek /* Disable all RX interrupts before RxBD space setup */
479a04a5daaSSiva Durga Prasad Paladugu temp = readl(&priv->dmarx->control);
4804f1ec4c1SMichal Simek temp &= ~XAXIDMA_IRQ_ALL_MASK;
481a04a5daaSSiva Durga Prasad Paladugu writel(temp, &priv->dmarx->control);
4824f1ec4c1SMichal Simek
4834f1ec4c1SMichal Simek /* Start DMA RX channel. Now it's ready to receive data.*/
484047f3bf8SVipul Kumar axienet_dma_write(&rx_bd, &priv->dmarx->current);
4854f1ec4c1SMichal Simek
4864f1ec4c1SMichal Simek /* Setup the BD. */
4874f1ec4c1SMichal Simek memset(&rx_bd, 0, sizeof(rx_bd));
4884f1ec4c1SMichal Simek rx_bd.next = (u32)&rx_bd;
4894f1ec4c1SMichal Simek rx_bd.phys = (u32)&rxframe;
4904f1ec4c1SMichal Simek rx_bd.cntrl = sizeof(rxframe);
4914f1ec4c1SMichal Simek /* Flush the last BD so DMA core could see the updates */
4924f1ec4c1SMichal Simek flush_cache((u32)&rx_bd, sizeof(rx_bd));
4934f1ec4c1SMichal Simek
4944f1ec4c1SMichal Simek /* It is necessary to flush rxframe because if you don't do it
4954f1ec4c1SMichal Simek * then cache can contain uninitialized data */
4964f1ec4c1SMichal Simek flush_cache((u32)&rxframe, sizeof(rxframe));
4974f1ec4c1SMichal Simek
4984f1ec4c1SMichal Simek /* Start the hardware */
499a04a5daaSSiva Durga Prasad Paladugu temp = readl(&priv->dmarx->control);
5004f1ec4c1SMichal Simek temp |= XAXIDMA_CR_RUNSTOP_MASK;
501a04a5daaSSiva Durga Prasad Paladugu writel(temp, &priv->dmarx->control);
5024f1ec4c1SMichal Simek
5034f1ec4c1SMichal Simek /* Rx BD is ready - start */
504047f3bf8SVipul Kumar axienet_dma_write(&rx_bd, &priv->dmarx->tail);
5054f1ec4c1SMichal Simek
5064f1ec4c1SMichal Simek /* Enable TX */
507a04a5daaSSiva Durga Prasad Paladugu writel(XAE_TC_TX_MASK, ®s->tc);
5084f1ec4c1SMichal Simek /* Enable RX */
509a04a5daaSSiva Durga Prasad Paladugu writel(XAE_RCW1_RX_MASK, ®s->rcw1);
5104f1ec4c1SMichal Simek
5114f1ec4c1SMichal Simek /* PHY setup */
5124f1ec4c1SMichal Simek if (!setup_phy(dev)) {
513ad499e42SMichal Simek axiemac_stop(dev);
5144f1ec4c1SMichal Simek return -1;
5154f1ec4c1SMichal Simek }
5164f1ec4c1SMichal Simek
5174f1ec4c1SMichal Simek debug("axiemac: Init complete\n");
5184f1ec4c1SMichal Simek return 0;
5194f1ec4c1SMichal Simek }
5204f1ec4c1SMichal Simek
axiemac_send(struct udevice * dev,void * ptr,int len)52175cc93faSMichal Simek static int axiemac_send(struct udevice *dev, void *ptr, int len)
5224f1ec4c1SMichal Simek {
52375cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
5244f1ec4c1SMichal Simek u32 timeout;
5254f1ec4c1SMichal Simek
5264f1ec4c1SMichal Simek if (len > PKTSIZE_ALIGN)
5274f1ec4c1SMichal Simek len = PKTSIZE_ALIGN;
5284f1ec4c1SMichal Simek
5294f1ec4c1SMichal Simek /* Flush packet to main memory to be trasfered by DMA */
5304f1ec4c1SMichal Simek flush_cache((u32)ptr, len);
5314f1ec4c1SMichal Simek
5324f1ec4c1SMichal Simek /* Setup Tx BD */
5334f1ec4c1SMichal Simek memset(&tx_bd, 0, sizeof(tx_bd));
5344f1ec4c1SMichal Simek /* At the end of the ring, link the last BD back to the top */
5354f1ec4c1SMichal Simek tx_bd.next = (u32)&tx_bd;
5364f1ec4c1SMichal Simek tx_bd.phys = (u32)ptr;
5374f1ec4c1SMichal Simek /* Save len */
5384f1ec4c1SMichal Simek tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
5394f1ec4c1SMichal Simek XAXIDMA_BD_CTRL_TXEOF_MASK;
5404f1ec4c1SMichal Simek
5414f1ec4c1SMichal Simek /* Flush the last BD so DMA core could see the updates */
5424f1ec4c1SMichal Simek flush_cache((u32)&tx_bd, sizeof(tx_bd));
5434f1ec4c1SMichal Simek
544a04a5daaSSiva Durga Prasad Paladugu if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
5454f1ec4c1SMichal Simek u32 temp;
546047f3bf8SVipul Kumar axienet_dma_write(&tx_bd, &priv->dmatx->current);
5474f1ec4c1SMichal Simek /* Start the hardware */
548a04a5daaSSiva Durga Prasad Paladugu temp = readl(&priv->dmatx->control);
5494f1ec4c1SMichal Simek temp |= XAXIDMA_CR_RUNSTOP_MASK;
550a04a5daaSSiva Durga Prasad Paladugu writel(temp, &priv->dmatx->control);
5514f1ec4c1SMichal Simek }
5524f1ec4c1SMichal Simek
5534f1ec4c1SMichal Simek /* Start transfer */
554047f3bf8SVipul Kumar axienet_dma_write(&tx_bd, &priv->dmatx->tail);
5554f1ec4c1SMichal Simek
5564f1ec4c1SMichal Simek /* Wait for transmission to complete */
5574f1ec4c1SMichal Simek debug("axiemac: Waiting for tx to be done\n");
5584f1ec4c1SMichal Simek timeout = 200;
559a04a5daaSSiva Durga Prasad Paladugu while (timeout && (!(readl(&priv->dmatx->status) &
5603e3f8ba2SMichal Simek (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
5614f1ec4c1SMichal Simek timeout--;
5624f1ec4c1SMichal Simek udelay(1);
5634f1ec4c1SMichal Simek }
5644f1ec4c1SMichal Simek if (!timeout) {
5654f1ec4c1SMichal Simek printf("%s: Timeout\n", __func__);
5664f1ec4c1SMichal Simek return 1;
5674f1ec4c1SMichal Simek }
5684f1ec4c1SMichal Simek
5694f1ec4c1SMichal Simek debug("axiemac: Sending complete\n");
5704f1ec4c1SMichal Simek return 0;
5714f1ec4c1SMichal Simek }
5724f1ec4c1SMichal Simek
isrxready(struct axidma_priv * priv)573f0985481SMichal Simek static int isrxready(struct axidma_priv *priv)
5744f1ec4c1SMichal Simek {
5754f1ec4c1SMichal Simek u32 status;
5764f1ec4c1SMichal Simek
5774f1ec4c1SMichal Simek /* Read pending interrupts */
578a04a5daaSSiva Durga Prasad Paladugu status = readl(&priv->dmarx->status);
5794f1ec4c1SMichal Simek
5804f1ec4c1SMichal Simek /* Acknowledge pending interrupts */
581a04a5daaSSiva Durga Prasad Paladugu writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
5824f1ec4c1SMichal Simek
5834f1ec4c1SMichal Simek /*
5844f1ec4c1SMichal Simek * If Reception done interrupt is asserted, call RX call back function
5854f1ec4c1SMichal Simek * to handle the processed BDs and then raise the according flag.
5864f1ec4c1SMichal Simek */
5874f1ec4c1SMichal Simek if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
5884f1ec4c1SMichal Simek return 1;
5894f1ec4c1SMichal Simek
5904f1ec4c1SMichal Simek return 0;
5914f1ec4c1SMichal Simek }
5924f1ec4c1SMichal Simek
axiemac_recv(struct udevice * dev,int flags,uchar ** packetp)59375cc93faSMichal Simek static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
5944f1ec4c1SMichal Simek {
5954f1ec4c1SMichal Simek u32 length;
59675cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
5974f1ec4c1SMichal Simek u32 temp;
5984f1ec4c1SMichal Simek
5994f1ec4c1SMichal Simek /* Wait for an incoming packet */
600f0985481SMichal Simek if (!isrxready(priv))
60175cc93faSMichal Simek return -1;
6024f1ec4c1SMichal Simek
6034f1ec4c1SMichal Simek debug("axiemac: RX data ready\n");
6044f1ec4c1SMichal Simek
6054f1ec4c1SMichal Simek /* Disable IRQ for a moment till packet is handled */
606a04a5daaSSiva Durga Prasad Paladugu temp = readl(&priv->dmarx->control);
6074f1ec4c1SMichal Simek temp &= ~XAXIDMA_IRQ_ALL_MASK;
608a04a5daaSSiva Durga Prasad Paladugu writel(temp, &priv->dmarx->control);
60989ce5a9dSSiva Durga Prasad Paladugu if (!priv->eth_hasnobuf)
6104f1ec4c1SMichal Simek length = rx_bd.app4 & 0xFFFF; /* max length mask */
61189ce5a9dSSiva Durga Prasad Paladugu else
61289ce5a9dSSiva Durga Prasad Paladugu length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
61389ce5a9dSSiva Durga Prasad Paladugu
6144f1ec4c1SMichal Simek #ifdef DEBUG
6154f1ec4c1SMichal Simek print_buffer(&rxframe, &rxframe[0], 1, length, 16);
6164f1ec4c1SMichal Simek #endif
61797d2363dSMichal Simek
61897d2363dSMichal Simek *packetp = rxframe;
61997d2363dSMichal Simek return length;
62097d2363dSMichal Simek }
62197d2363dSMichal Simek
axiemac_free_pkt(struct udevice * dev,uchar * packet,int length)62297d2363dSMichal Simek static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
62397d2363dSMichal Simek {
62497d2363dSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
6254f1ec4c1SMichal Simek
6264f1ec4c1SMichal Simek #ifdef DEBUG
6274f1ec4c1SMichal Simek /* It is useful to clear buffer to be sure that it is consistent */
6284f1ec4c1SMichal Simek memset(rxframe, 0, sizeof(rxframe));
6294f1ec4c1SMichal Simek #endif
6304f1ec4c1SMichal Simek /* Setup RxBD */
6314f1ec4c1SMichal Simek /* Clear the whole buffer and setup it again - all flags are cleared */
6324f1ec4c1SMichal Simek memset(&rx_bd, 0, sizeof(rx_bd));
6334f1ec4c1SMichal Simek rx_bd.next = (u32)&rx_bd;
6344f1ec4c1SMichal Simek rx_bd.phys = (u32)&rxframe;
6354f1ec4c1SMichal Simek rx_bd.cntrl = sizeof(rxframe);
6364f1ec4c1SMichal Simek
6374f1ec4c1SMichal Simek /* Write bd to HW */
6384f1ec4c1SMichal Simek flush_cache((u32)&rx_bd, sizeof(rx_bd));
6394f1ec4c1SMichal Simek
6404f1ec4c1SMichal Simek /* It is necessary to flush rxframe because if you don't do it
6414f1ec4c1SMichal Simek * then cache will contain previous packet */
6424f1ec4c1SMichal Simek flush_cache((u32)&rxframe, sizeof(rxframe));
6434f1ec4c1SMichal Simek
6444f1ec4c1SMichal Simek /* Rx BD is ready - start again */
645047f3bf8SVipul Kumar axienet_dma_write(&rx_bd, &priv->dmarx->tail);
6464f1ec4c1SMichal Simek
6474f1ec4c1SMichal Simek debug("axiemac: RX completed, framelength = %d\n", length);
6484f1ec4c1SMichal Simek
6494f1ec4c1SMichal Simek return 0;
6504f1ec4c1SMichal Simek }
6514f1ec4c1SMichal Simek
axiemac_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)65275cc93faSMichal Simek static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
65375cc93faSMichal Simek int devad, int reg)
6544f1ec4c1SMichal Simek {
65575cc93faSMichal Simek int ret;
65675cc93faSMichal Simek u16 value;
6574f1ec4c1SMichal Simek
65875cc93faSMichal Simek ret = phyread(bus->priv, addr, reg, &value);
65975cc93faSMichal Simek debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
66075cc93faSMichal Simek value, ret);
66175cc93faSMichal Simek return value;
6624f1ec4c1SMichal Simek }
6634f1ec4c1SMichal Simek
axiemac_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)66475cc93faSMichal Simek static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
66575cc93faSMichal Simek int reg, u16 value)
66675cc93faSMichal Simek {
66775cc93faSMichal Simek debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
66875cc93faSMichal Simek return phywrite(bus->priv, addr, reg, value);
66975cc93faSMichal Simek }
6704f1ec4c1SMichal Simek
axi_emac_probe(struct udevice * dev)67175cc93faSMichal Simek static int axi_emac_probe(struct udevice *dev)
67275cc93faSMichal Simek {
67375cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
67475cc93faSMichal Simek int ret;
67575cc93faSMichal Simek
67675cc93faSMichal Simek priv->bus = mdio_alloc();
67775cc93faSMichal Simek priv->bus->read = axiemac_miiphy_read;
67875cc93faSMichal Simek priv->bus->write = axiemac_miiphy_write;
67975cc93faSMichal Simek priv->bus->priv = priv;
68075cc93faSMichal Simek
6816516e3f2SMichal Simek ret = mdio_register_seq(priv->bus, dev->seq);
68275cc93faSMichal Simek if (ret)
68375cc93faSMichal Simek return ret;
68475cc93faSMichal Simek
6855d0449d4SMichal Simek axiemac_phy_init(dev);
6865d0449d4SMichal Simek
68775cc93faSMichal Simek return 0;
68875cc93faSMichal Simek }
68975cc93faSMichal Simek
axi_emac_remove(struct udevice * dev)69075cc93faSMichal Simek static int axi_emac_remove(struct udevice *dev)
69175cc93faSMichal Simek {
69275cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
69375cc93faSMichal Simek
69475cc93faSMichal Simek free(priv->phydev);
69575cc93faSMichal Simek mdio_unregister(priv->bus);
69675cc93faSMichal Simek mdio_free(priv->bus);
69775cc93faSMichal Simek
69875cc93faSMichal Simek return 0;
69975cc93faSMichal Simek }
70075cc93faSMichal Simek
70175cc93faSMichal Simek static const struct eth_ops axi_emac_ops = {
702ad499e42SMichal Simek .start = axiemac_start,
70375cc93faSMichal Simek .send = axiemac_send,
70475cc93faSMichal Simek .recv = axiemac_recv,
70597d2363dSMichal Simek .free_pkt = axiemac_free_pkt,
706ad499e42SMichal Simek .stop = axiemac_stop,
707ad499e42SMichal Simek .write_hwaddr = axiemac_write_hwaddr,
70875cc93faSMichal Simek };
70975cc93faSMichal Simek
axi_emac_ofdata_to_platdata(struct udevice * dev)71075cc93faSMichal Simek static int axi_emac_ofdata_to_platdata(struct udevice *dev)
71175cc93faSMichal Simek {
71275cc93faSMichal Simek struct eth_pdata *pdata = dev_get_platdata(dev);
71375cc93faSMichal Simek struct axidma_priv *priv = dev_get_priv(dev);
714e160f7d4SSimon Glass int node = dev_of_offset(dev);
71575cc93faSMichal Simek int offset = 0;
71675cc93faSMichal Simek const char *phy_mode;
71775cc93faSMichal Simek
718a821c4afSSimon Glass pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
71975cc93faSMichal Simek priv->iobase = (struct axi_regs *)pdata->iobase;
72075cc93faSMichal Simek
721e160f7d4SSimon Glass offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
72275cc93faSMichal Simek "axistream-connected");
72375cc93faSMichal Simek if (offset <= 0) {
72475cc93faSMichal Simek printf("%s: axistream is not found\n", __func__);
72575cc93faSMichal Simek return -EINVAL;
72675cc93faSMichal Simek }
727dc1fcc42SSiva Durga Prasad Paladugu priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
728dc1fcc42SSiva Durga Prasad Paladugu offset, "reg");
72975cc93faSMichal Simek if (!priv->dmatx) {
73075cc93faSMichal Simek printf("%s: axi_dma register space not found\n", __func__);
73175cc93faSMichal Simek return -EINVAL;
73275cc93faSMichal Simek }
7334f1ec4c1SMichal Simek /* RX channel offset is 0x30 */
73475cc93faSMichal Simek priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
7354f1ec4c1SMichal Simek
7364f1ec4c1SMichal Simek priv->phyaddr = -1;
7374f1ec4c1SMichal Simek
738e160f7d4SSimon Glass offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
73975cc93faSMichal Simek if (offset > 0)
74075cc93faSMichal Simek priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
7414f1ec4c1SMichal Simek
742e160f7d4SSimon Glass phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
74375cc93faSMichal Simek if (phy_mode)
74475cc93faSMichal Simek pdata->phy_interface = phy_get_interface_by_name(phy_mode);
74575cc93faSMichal Simek if (pdata->phy_interface == -1) {
746ceb04e1aSMichal Simek printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
74775cc93faSMichal Simek return -EINVAL;
7484f1ec4c1SMichal Simek }
74975cc93faSMichal Simek priv->interface = pdata->phy_interface;
75075cc93faSMichal Simek
75189ce5a9dSSiva Durga Prasad Paladugu priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
75289ce5a9dSSiva Durga Prasad Paladugu "xlnx,eth-hasnobuf");
75389ce5a9dSSiva Durga Prasad Paladugu
75475cc93faSMichal Simek printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
75575cc93faSMichal Simek priv->phyaddr, phy_string_for_interface(priv->interface));
75675cc93faSMichal Simek
75775cc93faSMichal Simek return 0;
75875cc93faSMichal Simek }
75975cc93faSMichal Simek
76075cc93faSMichal Simek static const struct udevice_id axi_emac_ids[] = {
76175cc93faSMichal Simek { .compatible = "xlnx,axi-ethernet-1.00.a" },
76275cc93faSMichal Simek { }
76375cc93faSMichal Simek };
76475cc93faSMichal Simek
76575cc93faSMichal Simek U_BOOT_DRIVER(axi_emac) = {
76675cc93faSMichal Simek .name = "axi_emac",
76775cc93faSMichal Simek .id = UCLASS_ETH,
76875cc93faSMichal Simek .of_match = axi_emac_ids,
76975cc93faSMichal Simek .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
77075cc93faSMichal Simek .probe = axi_emac_probe,
77175cc93faSMichal Simek .remove = axi_emac_remove,
77275cc93faSMichal Simek .ops = &axi_emac_ops,
77375cc93faSMichal Simek .priv_auto_alloc_size = sizeof(struct axidma_priv),
77475cc93faSMichal Simek .platdata_auto_alloc_size = sizeof(struct eth_pdata),
77575cc93faSMichal Simek };
776