Lines Matching +full:bd +full:- +full:address
1 /* SPDX-License-Identifier: GPL-2.0+ */
25 /* Control and status Registers (offset 000-1FF) */
33 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
36 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
39 uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
42 uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
44 uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
46 uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
51 uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
56 uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
62 uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
66 uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
68 /* MIB COUNTERS (Offset 200-2FF) */
100 uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
129 uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
133 uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
135 uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
136 uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
138 uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
207 /* MMI/7-Wire mode */
220 * Note: The first BD must be aligned (see DB_ALIGNMENT)
224 uint16_t status; /* BD's staus (see datasheet) */
225 uint32_t data_pointer; /* payload's buffer address */
230 SEVENWIRE, /* 7-wire */
237 /* @brief i.MX27-FEC private structure */
242 int rbd_index; /* next receive BD to read */
244 int tbd_index; /* next transmit BD to write */
245 bd_t *bd; member
284 * frames in more than one BD. This is nothing to worry about, but the current
289 /* Receive BD status bits */
290 #define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
291 #define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
292 /* Receive BD status: Buffer is last in frame (useless here!) */
294 #define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
295 /* Receive BD status: The received frame is broadcast frame */
297 /* Receive BD status: The received frame is multicast frame */
299 #define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
300 #define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
301 #define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
302 #define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
303 #define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
307 /* Transmit BD status bits */
308 #define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
309 #define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
310 #define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
311 #define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
312 #define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
314 /* MII-related definitios */
318 #define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
323 #define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
324 #define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */