Lines Matching +full:bd +full:- +full:address

1 // SPDX-License-Identifier: GPL-2.0+
42 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
43 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
44 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
45 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
98 /* BD descriptors */
102 u32 phys; /* Buffer address */
118 /* Static BDs - driver uses only one BD */
138 u32 uaw0; /* 0x700: Unicast address word 0 */
139 u32 uaw1; /* 0x704: Unicast address word 1 */
150 * 0x0008: Auto-negotiation support
159 while (timeout && (!(readl(&regs->mdio_mcr) in mdio_wait()
161 timeout--; in mdio_wait()
172 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
173 * @bd: pointer to BD descriptor structure
174 * @desc: Address offset of DMA descriptors
178 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc) in axienet_dma_write() argument
181 writeq(bd, desc); in axienet_dma_write()
183 writel((u32)bd, desc); in axienet_dma_write()
190 struct axi_regs *regs = priv->iobase; in phyread()
203 writel(mdioctrlreg, &regs->mdio_mcr); in phyread()
209 *val = readl(&regs->mdio_mrd); in phyread()
216 struct axi_regs *regs = priv->iobase; in phywrite()
230 writel(data, &regs->mdio_mwd); in phywrite()
232 writel(mdioctrlreg, &regs->mdio_mcr); in phywrite()
245 struct axi_regs *regs = priv->iobase; in axiemac_phy_init()
256 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc); in axiemac_phy_init()
258 if (priv->phyaddr == -1) { in axiemac_phy_init()
259 /* Detect the PHY address */ in axiemac_phy_init()
260 for (i = 31; i >= 0; i--) { in axiemac_phy_init()
264 /* Found a valid PHY address */ in axiemac_phy_init()
265 priv->phyaddr = i; in axiemac_phy_init()
266 debug("axiemac: Found valid phy address, %x\n", in axiemac_phy_init()
273 /* Interface - look at tsec */ in axiemac_phy_init()
274 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); in axiemac_phy_init()
276 phydev->supported &= supported; in axiemac_phy_init()
277 phydev->advertising = phydev->supported; in axiemac_phy_init()
278 priv->phydev = phydev; in axiemac_phy_init()
290 struct axi_regs *regs = priv->iobase; in setup_phy()
291 struct phy_device *phydev = priv->phydev; in setup_phy()
293 if (priv->interface == PHY_INTERFACE_MODE_SGMII) { in setup_phy()
299 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp); in setup_phy()
304 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp); in setup_phy()
312 phydev->dev->name); in setup_phy()
315 if (!phydev->link) { in setup_phy()
316 printf("%s: No link.\n", phydev->dev->name); in setup_phy()
320 switch (phydev->speed) { in setup_phy()
335 emmc_reg = readl(&regs->emmc); in setup_phy()
340 writel(emmc_reg, &regs->emmc); in setup_phy()
359 temp = readl(&priv->dmatx->control); in axiemac_stop()
361 writel(temp, &priv->dmatx->control); in axiemac_stop()
363 temp = readl(&priv->dmarx->control); in axiemac_stop()
365 writel(temp, &priv->dmarx->control); in axiemac_stop()
372 struct axi_regs *regs = priv->iobase; in axi_ethernet_init()
384 if (!priv->eth_hasnobuf) { in axi_ethernet_init()
385 err = wait_for_bit_le32(&regs->is, XAE_INT_MGTRDY_MASK, in axi_ethernet_init()
396 writel(0, &regs->ie); in axi_ethernet_init()
400 writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1); in axi_ethernet_init()
403 * Stopping the receiver in mid-packet causes a dropped packet in axi_ethernet_init()
406 if (!priv->eth_hasnobuf) { in axi_ethernet_init()
408 writel(XAE_INT_RXRJECT_MASK, &regs->is); in axi_ethernet_init()
413 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc); in axi_ethernet_init()
423 struct axi_regs *regs = priv->iobase; in axiemac_write_hwaddr()
425 /* Set the MAC address */ in axiemac_write_hwaddr()
426 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | in axiemac_write_hwaddr()
427 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); in axiemac_write_hwaddr()
428 writel(val, &regs->uaw0); in axiemac_write_hwaddr()
430 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4]; in axiemac_write_hwaddr()
431 val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK; in axiemac_write_hwaddr()
432 writel(val, &regs->uaw1); in axiemac_write_hwaddr()
442 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control); in axi_dma_init()
443 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control); in axi_dma_init()
446 while (timeout--) { in axi_dma_init()
449 if (!((readl(&priv->dmatx->control) | in axi_dma_init()
450 readl(&priv->dmarx->control)) in axi_dma_init()
462 struct axi_regs *regs = priv->iobase; in axiemac_start()
476 return -1; in axiemac_start()
479 temp = readl(&priv->dmarx->control); in axiemac_start()
481 writel(temp, &priv->dmarx->control); in axiemac_start()
484 axienet_dma_write(&rx_bd, &priv->dmarx->current); in axiemac_start()
486 /* Setup the BD. */ in axiemac_start()
491 /* Flush the last BD so DMA core could see the updates */ in axiemac_start()
499 temp = readl(&priv->dmarx->control); in axiemac_start()
501 writel(temp, &priv->dmarx->control); in axiemac_start()
503 /* Rx BD is ready - start */ in axiemac_start()
504 axienet_dma_write(&rx_bd, &priv->dmarx->tail); in axiemac_start()
507 writel(XAE_TC_TX_MASK, &regs->tc); in axiemac_start()
509 writel(XAE_RCW1_RX_MASK, &regs->rcw1); in axiemac_start()
514 return -1; in axiemac_start()
532 /* Setup Tx BD */ in axiemac_send()
534 /* At the end of the ring, link the last BD back to the top */ in axiemac_send()
541 /* Flush the last BD so DMA core could see the updates */ in axiemac_send()
544 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { in axiemac_send()
546 axienet_dma_write(&tx_bd, &priv->dmatx->current); in axiemac_send()
548 temp = readl(&priv->dmatx->control); in axiemac_send()
550 writel(temp, &priv->dmatx->control); in axiemac_send()
554 axienet_dma_write(&tx_bd, &priv->dmatx->tail); in axiemac_send()
559 while (timeout && (!(readl(&priv->dmatx->status) & in axiemac_send()
561 timeout--; in axiemac_send()
578 status = readl(&priv->dmarx->status); in isrxready()
581 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status); in isrxready()
601 return -1; in axiemac_recv()
606 temp = readl(&priv->dmarx->control); in axiemac_recv()
608 writel(temp, &priv->dmarx->control); in axiemac_recv()
609 if (!priv->eth_hasnobuf) in axiemac_recv()
631 /* Clear the whole buffer and setup it again - all flags are cleared */ in axiemac_free_pkt()
637 /* Write bd to HW */ in axiemac_free_pkt()
644 /* Rx BD is ready - start again */ in axiemac_free_pkt()
645 axienet_dma_write(&rx_bd, &priv->dmarx->tail); in axiemac_free_pkt()
658 ret = phyread(bus->priv, addr, reg, &value); in axiemac_miiphy_read()
668 return phywrite(bus->priv, addr, reg, value); in axiemac_miiphy_write()
676 priv->bus = mdio_alloc(); in axi_emac_probe()
677 priv->bus->read = axiemac_miiphy_read; in axi_emac_probe()
678 priv->bus->write = axiemac_miiphy_write; in axi_emac_probe()
679 priv->bus->priv = priv; in axi_emac_probe()
681 ret = mdio_register_seq(priv->bus, dev->seq); in axi_emac_probe()
694 free(priv->phydev); in axi_emac_remove()
695 mdio_unregister(priv->bus); in axi_emac_remove()
696 mdio_free(priv->bus); in axi_emac_remove()
718 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); in axi_emac_ofdata_to_platdata()
719 priv->iobase = (struct axi_regs *)pdata->iobase; in axi_emac_ofdata_to_platdata()
721 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, in axi_emac_ofdata_to_platdata()
722 "axistream-connected"); in axi_emac_ofdata_to_platdata()
725 return -EINVAL; in axi_emac_ofdata_to_platdata()
727 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, in axi_emac_ofdata_to_platdata()
729 if (!priv->dmatx) { in axi_emac_ofdata_to_platdata()
731 return -EINVAL; in axi_emac_ofdata_to_platdata()
734 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30); in axi_emac_ofdata_to_platdata()
736 priv->phyaddr = -1; in axi_emac_ofdata_to_platdata()
738 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); in axi_emac_ofdata_to_platdata()
740 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); in axi_emac_ofdata_to_platdata()
742 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); in axi_emac_ofdata_to_platdata()
744 pdata->phy_interface = phy_get_interface_by_name(phy_mode); in axi_emac_ofdata_to_platdata()
745 if (pdata->phy_interface == -1) { in axi_emac_ofdata_to_platdata()
747 return -EINVAL; in axi_emac_ofdata_to_platdata()
749 priv->interface = pdata->phy_interface; in axi_emac_ofdata_to_platdata()
751 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, in axi_emac_ofdata_to_platdata()
752 "xlnx,eth-hasnobuf"); in axi_emac_ofdata_to_platdata()
754 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, in axi_emac_ofdata_to_platdata()
755 priv->phyaddr, phy_string_for_interface(priv->interface)); in axi_emac_ofdata_to_platdata()
761 { .compatible = "xlnx,axi-ethernet-1.00.a" },