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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
32 the UART's CTS line.
34 dcd-gpios:
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H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
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/openbmc/linux/drivers/extcon/
H A Dextcon-max8997.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max8997.c - MAX8997 extcon driver to support MAX8997 MUIC
8 #include <linux/devm-helpers.h>
18 #include <linux/mfd/max8997-private.h>
19 #include <linux/extcon-provider.h>
22 #define DEV_NAME "max8997-muic"
39 { MAX8997_MUICIRQ_ADCError, "muic-ADCERROR" },
40 { MAX8997_MUICIRQ_ADCLow, "muic-ADCLOW" },
41 { MAX8997_MUICIRQ_ADC, "muic-ADC" },
42 { MAX8997_MUICIRQ_VBVolt, "muic-VBVOLT" },
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H A Dextcon-max77693.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max77693.c - MAX77693 extcon driver to support MAX77693 MUIC
8 #include <linux/devm-helpers.h>
18 #include <linux/mfd/max77693-common.h>
19 #include <linux/mfd/max77693-private.h>
20 #include <linux/extcon-provider.h>
24 #define DEV_NAME "max77693-muic"
30 * extcon-max77693 driver use 'default_init_data' to bring up base operation
35 /* STATUS2 - [3]ChgDetRun */
39 /* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */
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H A Dextcon-max14577.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max14577.c - MAX14577/77836 extcon driver to support MUIC
9 #include <linux/devm-helpers.h>
16 #include <linux/mfd/max14577-private.h>
17 #include <linux/extcon-provider.h>
47 { MAX14577_IRQ_INT1_ADC, "muic-ADC" },
48 { MAX14577_IRQ_INT1_ADCLOW, "muic-ADCLOW" },
49 { MAX14577_IRQ_INT1_ADCERR, "muic-ADCError" },
50 { MAX14577_IRQ_INT2_CHGTYP, "muic-CHGTYP" },
51 { MAX14577_IRQ_INT2_CHGDETRUN, "muic-CHGDETRUN" },
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/openbmc/linux/drivers/iio/imu/bno055/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
9 tristate "Bosch BNO055 attached via UART"
14 Enable this to support Bosch BNO055 IMUs attached via UART.
20 tristate "Bosch BNO055 attached via I2C bus"
25 Enable this to support Bosch BNO055 IMUs attached via I2C bus.
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_parisc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
18 #include <asm/parisc-device.h>
25 struct uart_8250_port uart; in serial_init_chip() local
30 if (!dev->irq && (dev->id.sversion == 0xad)) in serial_init_chip()
31 dev->irq = iosapic_serial_irq(dev); in serial_init_chip()
34 if (!dev->irq) { in serial_init_chip()
40 if (parisc_parent(dev)->id.hw_type != HPHW_IOA) in serial_init_chip()
41 dev_info(&dev->dev, in serial_init_chip()
44 (unsigned long long)dev->hpa.start); in serial_init_chip()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-bluetooth.txt1 MediaTek SoC built-in Bluetooth Devices
4 This device is a serial attached device to BTIF device and thus it must be a
5 child node of the serial node with BTIF. The dt-bindings details for BTIF
10 - compatible: Must be
11 "mediatek,mt7622-bluetooth": for MT7622 SoC
12 - clocks: Should be the clock specifiers corresponding to the entry in
13 clock-names property.
14 - clock-names: Should contain "ref" entries.
15 - power-domains: Phandle to the power domain that the device is part of
20 compatible = "mediatek,mt7622-btif",
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H A Dti,bluetooth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Lechner <david@lechnology.com>
14 attached TI Bluetooth devices. The following chips are included in this
20 TI WiLink devices have a UART interface for providing Bluetooth, FM radio,
27 This bindings follows the UART slave device binding in ../serial/serial.yaml.
32 - ti,cc2560
33 - ti,wl1271-st
34 - ti,wl1273-st
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H A Dbroadcom-bluetooth.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/broadcom-bluetooth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This binding describes Broadcom UART-attached bluetooth chips.
18 - brcm,bcm20702a1
19 - brcm,bcm4329-bt
20 - brcm,bcm4330-bt
21 - brcm,bcm4334-bt
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/openbmc/linux/Documentation/devicetree/bindings/net/bluetooth/
H A Dnxp,88w8987-bt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/nxp,88w8987-bt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This binding describes UART-attached NXP bluetooth chips. These chips
11 are dual-radio chips supporting WiFi and Bluetooth. The bluetooth
12 works on standard H4 protocol over 4-wire UART. The RTS and CTS lines
14 asserts break signal over UART-TX line to put the chip into power save
15 state. De-asserting break wakes up the BT chip.
18 - Neeraj Sanjay Kale <neeraj.sanjaykale@nxp.com>
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/openbmc/linux/drivers/platform/chrome/
H A Dcros_ec_uart.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UART interface for ChromeOS Embedded Controller
5 * Copyright 2020-2022 Google LLC.
23 * EC sends contiguous bytes of response packet on UART AP RX.
40 * struct response_info - Encapsulate EC response related
51 * @status: Re-init to 0 before sending a cmd. Updated to 1 when
67 * struct cros_ec_uart - information about a uart-connected EC
69 * @serdev: serdev uart device we are connected to.
70 * @baudrate: UART baudrate of attached EC device.
71 * @flowcontrol: UART flowcontrol of attached device.
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/openbmc/openbmc/meta-raspberrypi/recipes-connectivity/pi-bluetooth/pi-bluetooth/
H A D0001-bthelper-correct-path-for-hciconfig-under-Yocto.patch3 Date: Wed, 14 Nov 2018 09:19:51 -0600
6 Upstream-Status: Inappropriate [OE-specific]
7 Signed-off-by: Peter A. Bigot <pab@pabigot.com>
8 Signed-off-by: Andrei Gherzan <andrei@gherzan.ro>
10 ---
11 usr/bin/bthelper | 6 +++---
12 1 file changed, 3 insertions(+), 3 deletions(-)
14 diff --git a/usr/bin/bthelper b/usr/bin/bthelper
16 --- a/usr/bin/bthelper
18 @@ -12,8 +12,8 @@ fi
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/openbmc/linux/Documentation/networking/device_drivers/can/
H A Dcan327.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
7 --------
14 -----------
26 -------------
33 order to fake full-duplex operation.
36 enough to implement simple request-response protocols (such as OBD II),
39 Most ELM327s come as nondescript serial devices, attached via USB or
50 -----------
59 ----------------------------------
65 be attached on a command prompt as follows::
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/openbmc/linux/drivers/bluetooth/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
105 tristate "HCI UART driver"
110 Bluetooth HCI UART driver.
113 UART based Bluetooth PCMCIA and CF devices like Xircom Credit Card
116 Say Y here to compile support for Bluetooth UART devices into the
125 bool "UART (H4) protocol support"
128 UART (H4) is serial protocol for communication between Bluetooth
130 with UART interface, including PCMCIA and CF cards.
132 Say Y here to compile support for HCI UART (H4) protocol.
135 tristate "UART Nokia H4+ protocol support"
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/openbmc/u-boot/doc/driver-model/
H A Dpci-info.txt5 ----------------------
17 pci: pci-controller {
40 defined by the IEEE Std 1275-1994 PCI bus binding document v2.1. Compatible
51 #address-cells = <3>;
52 #size-cells = <2>;
53 compatible = "pci-x86";
54 u-boot,dm-pre-reloc;
60 #address-cells = <3>;
61 #size-cells = <2>;
62 compatible = "pci-bridge";
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/openbmc/u-boot/drivers/misc/
H A DKconfig50 bool "Rockchip e-fuse support"
53 Enable (read-only) access for the e-fuse block found in Rockchip
55 or through child-nodes that are generated based on the e-fuse map
74 Enable command-line access to the Chrome OS EC (Embedded
76 a number of sub-commands for performing EC tasks such as
112 keyboard (use the -l flag to enable the LCD), verified boot context,
121 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
129 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
159 disable the legacy UART, the watchdog or other devices
163 bool "Enable power-sequencing drivers"
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/openbmc/linux/Documentation/devicetree/bindings/ptp/
H A Dtimestamper.txt3 This binding supports non-PHY devices that snoop the MII bus and
9 Non-PHY MII time stamping drivers typically talk to the control
10 interface over another bus like I2C, SPI, UART, or via a memory mapped
20 compatible = "ines,ptp-ctrl";
26 ethernet-phy@1 {
34 ethernet-phy@2 {
40 In this example, time stamps from the MII bus attached to phy@1 will
/openbmc/linux/Documentation/devicetree/bindings/gnss/
H A Du-blox,neo-6m.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: U-blox GNSS Receiver
10 - $ref: gnss-common.yaml#
13 - Johan Hovold <johan@kernel.org>
16 The U-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces.
21 - u-blox,neo-6m
22 - u-blox,neo-8
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/openbmc/linux/drivers/gpio/
H A Dgpio-exar.c1 // SPDX-License-Identifier: GPL-2.0-only
25 * The Device Configuration and UART Configuration Registers
26 * for each UART channel take 1KB of memory address space.
50 unsigned int pin = exar_gpio->first_pin + (offset % 16); in exar_offset_to_sel_addr()
54 return addr + (cascaded ? exar_gpio->cascaded_offset : 0); in exar_offset_to_sel_addr()
60 unsigned int pin = exar_gpio->first_pin + (offset % 16); in exar_offset_to_lvl_addr()
64 return addr + (cascaded ? exar_gpio->cascaded_offset : 0); in exar_offset_to_lvl_addr()
70 unsigned int pin = exar_gpio->first_pin + (offset % 16); in exar_offset_to_bit()
81 if (regmap_test_bits(exar_gpio->regmap, addr, BIT(bit))) in exar_get_direction()
93 return !!(regmap_test_bits(exar_gpio->regmap, addr, BIT(bit))); in exar_get_value()
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/openbmc/u-boot/include/
H A Dserial.h122 SERIAL_CHIP_UNKNOWN = -1,
132 * struct serial_device_info - structure to hold serial device info
134 * @type: type of the UART chip
155 * struct struct dm_serial_ops - Driver model serial operations
162 * setbrg() - Set up the baud rate generator
167 * available rate. or return -EINVAL if this is not possible.
171 * @return 0 if OK, -ve on error
175 * getc() - Read a character and return it
177 * If no character is available, this should return -EAGAIN without
181 * @return character (0..255), -ve on error
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
22 - description:
24 const: google,cros-ec-i2c
25 - description:
27 const: google,cros-ec-spi
[all …]
/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_gcr.h25 * 11: System flash attached to BMC
27 * 9:8: Flash UART command route enabled.
29 * 6: HI-Z state control.
70 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
/openbmc/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
31 channels. When an input trigger becomes active, the attached channel will
32 become active. Any output trigger attached to that channel will also
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/openbmc/u-boot/arch/mips/cpu/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for MIPS32 CPU-core
8 #include <asm-offsets.h>
55 li t0, -16
78 PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
83 /* U-Boot entry point */
89 * Store some board-specific boot configuration. This is used by some
101 * if one is attached.
223 /* Earliest point to set up debug uart */
256 /* Earliest point to set up debug uart */
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