1ebd35674SAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ebd35674SAnson Huang%YAML 1.2 3ebd35674SAnson Huang--- 4ebd35674SAnson Huang$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml# 5ebd35674SAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6ebd35674SAnson Huang 7ebd35674SAnson Huangtitle: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART) 8ebd35674SAnson Huang 9ebd35674SAnson Huangmaintainers: 1081004f0bSFabio Estevam - Fabio Estevam <festevam@gmail.com> 11ebd35674SAnson Huang 12ebd35674SAnson HuangallOf: 13eec2c477SKrzysztof Kozlowski - $ref: serial.yaml# 14eec2c477SKrzysztof Kozlowski - $ref: rs485.yaml# 15ebd35674SAnson Huang 16ebd35674SAnson Huangproperties: 17ebd35674SAnson Huang compatible: 18ebd35674SAnson Huang oneOf: 19ebd35674SAnson Huang - const: fsl,imx1-uart 20ebd35674SAnson Huang - const: fsl,imx21-uart 21ebd35674SAnson Huang - items: 22ebd35674SAnson Huang - enum: 23ebd35674SAnson Huang - fsl,imx25-uart 24ebd35674SAnson Huang - fsl,imx27-uart 25ebd35674SAnson Huang - fsl,imx31-uart 26ebd35674SAnson Huang - fsl,imx35-uart 27ebd35674SAnson Huang - fsl,imx50-uart 28ebd35674SAnson Huang - fsl,imx51-uart 297a64ed02SKrzysztof Kozlowski - fsl,imx53-uart 307a64ed02SKrzysztof Kozlowski - fsl,imx6q-uart 31ebd35674SAnson Huang - const: fsl,imx21-uart 32ebd35674SAnson Huang - items: 33ebd35674SAnson Huang - enum: 34ebd35674SAnson Huang - fsl,imx6sl-uart 35ebd35674SAnson Huang - fsl,imx6sll-uart 36ebd35674SAnson Huang - fsl,imx6sx-uart 377a64ed02SKrzysztof Kozlowski - const: fsl,imx6q-uart 387a64ed02SKrzysztof Kozlowski - const: fsl,imx21-uart 397a64ed02SKrzysztof Kozlowski - items: 407a64ed02SKrzysztof Kozlowski - enum: 41ebd35674SAnson Huang - fsl,imx6ul-uart 42ebd35674SAnson Huang - fsl,imx7d-uart 43669e8aa3SKrzysztof Kozlowski - fsl,imx8mm-uart 44669e8aa3SKrzysztof Kozlowski - fsl,imx8mn-uart 45669e8aa3SKrzysztof Kozlowski - fsl,imx8mp-uart 46669e8aa3SKrzysztof Kozlowski - fsl,imx8mq-uart 47ebd35674SAnson Huang - const: fsl,imx6q-uart 48ebd35674SAnson Huang 49ebd35674SAnson Huang reg: 50ebd35674SAnson Huang maxItems: 1 51ebd35674SAnson Huang 52*872eb918SMarek Vasut clocks: 53*872eb918SMarek Vasut maxItems: 2 54*872eb918SMarek Vasut 55*872eb918SMarek Vasut clock-names: 56*872eb918SMarek Vasut items: 57*872eb918SMarek Vasut - const: ipg 58*872eb918SMarek Vasut - const: per 59*872eb918SMarek Vasut 60cf8d4027SMarek Vasut dmas: 61cf8d4027SMarek Vasut items: 62cf8d4027SMarek Vasut - description: DMA controller phandle and request line for RX 63cf8d4027SMarek Vasut - description: DMA controller phandle and request line for TX 64cf8d4027SMarek Vasut 65cf8d4027SMarek Vasut dma-names: 66cf8d4027SMarek Vasut items: 67cf8d4027SMarek Vasut - const: rx 68cf8d4027SMarek Vasut - const: tx 69cf8d4027SMarek Vasut 70ebd35674SAnson Huang interrupts: 71ebd35674SAnson Huang maxItems: 1 72ebd35674SAnson Huang 73ebd35674SAnson Huang fsl,dte-mode: 74ebd35674SAnson Huang $ref: /schemas/types.yaml#/definitions/flag 75ebd35674SAnson Huang description: | 76ebd35674SAnson Huang Indicate the uart works in DTE mode. The uart works in DCE mode by default. 77ebd35674SAnson Huang 78ebd35674SAnson Huang fsl,inverted-tx: 79ebd35674SAnson Huang $ref: /schemas/types.yaml#/definitions/flag 80ebd35674SAnson Huang description: | 81ebd35674SAnson Huang Indicate that the hardware attached to the peripheral inverts the signal 82ebd35674SAnson Huang transmitted, and that the peripheral should invert its output using the 83ebd35674SAnson Huang INVT registers. 84ebd35674SAnson Huang 85ebd35674SAnson Huang fsl,inverted-rx: 86ebd35674SAnson Huang $ref: /schemas/types.yaml#/definitions/flag 87ebd35674SAnson Huang description: | 88ebd35674SAnson Huang Indicate that the hardware attached to the peripheral inverts the signal 89ebd35674SAnson Huang received, and that the peripheral should invert its input using the 90ebd35674SAnson Huang INVR registers. 91ebd35674SAnson Huang 92db0a196bSFabien Lahoudere fsl,dma-info: 93db0a196bSFabien Lahoudere $ref: /schemas/types.yaml#/definitions/uint32-array 94db0a196bSFabien Lahoudere minItems: 2 95db0a196bSFabien Lahoudere maxItems: 2 96db0a196bSFabien Lahoudere description: | 97db0a196bSFabien Lahoudere First cell contains the size of DMA buffer chunks, second cell contains 98db0a196bSFabien Lahoudere the amount of chunks used for the device. Multiplying both numbers is 99db0a196bSFabien Lahoudere the total size of memory used for receiving data. 100db0a196bSFabien Lahoudere When not being configured the system will use default settings, which 101db0a196bSFabien Lahoudere are sensible for most use cases. If you need low latency processing on 102db0a196bSFabien Lahoudere slow connections this needs to be configured appropriately. 103db0a196bSFabien Lahoudere 104ebd35674SAnson Huangrequired: 105ebd35674SAnson Huang - compatible 106ebd35674SAnson Huang - reg 107*872eb918SMarek Vasut - clocks 108*872eb918SMarek Vasut - clock-names 109ebd35674SAnson Huang - interrupts 110ebd35674SAnson Huang 111ebd35674SAnson HuangunevaluatedProperties: false 112ebd35674SAnson Huang 113ebd35674SAnson Huangexamples: 114ebd35674SAnson Huang - | 115*872eb918SMarek Vasut #include <dt-bindings/clock/imx5-clock.h> 116*872eb918SMarek Vasut 117ebd35674SAnson Huang aliases { 118ebd35674SAnson Huang serial0 = &uart1; 119ebd35674SAnson Huang }; 120ebd35674SAnson Huang 121ebd35674SAnson Huang uart1: serial@73fbc000 { 122ebd35674SAnson Huang compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 123ebd35674SAnson Huang reg = <0x73fbc000 0x4000>; 124ebd35674SAnson Huang interrupts = <31>; 125*872eb918SMarek Vasut clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 126*872eb918SMarek Vasut <&clks IMX5_CLK_UART1_PER_GATE>; 127*872eb918SMarek Vasut clock-names = "ipg", "per"; 128cf8d4027SMarek Vasut dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; 129cf8d4027SMarek Vasut dma-names = "rx", "tx"; 130ebd35674SAnson Huang uart-has-rtscts; 131ebd35674SAnson Huang fsl,dte-mode; 132ebd35674SAnson Huang }; 133