Revision tags: v10.0.0, v9.2.3, v9.2.2 |
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f41af4c5 |
| 20-Feb-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-target-arm-20250220' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Fix some incorrect syndrome values in various sysreg traps * Clean up sysre
Merge tag 'pull-target-arm-20250220' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Fix some incorrect syndrome values in various sysreg traps * Clean up sysreg trap code to avoid similar future bugs * Make boards/SoCs using a9mpcore and a15mpcore objects specify number of GIC interrupts explicitly * Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX * target/arm: Use uint32_t in t32_expandimm_imm() * New board model: NPCM845 Evaluation board "npcm845-evb"
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* tag 'pull-target-arm-20250220' of https://git.linaro.org/people/pmaydell/qemu-arm: (41 commits) docs/system/arm: Add Description for NPCM8XX SoC hw/arm: Add NPCM845 Evaluation board hw/arm: Add NPCM8XX SoC hw/net: Add NPCM8XX PCS Module hw/misc: Support NPCM8XX CLK Module Registers hw/misc: Add nr_regs and cold_reset_values to NPCM CLK hw/misc: Move NPCM7XX CLK to NPCM CLK hw/misc: Rename npcm7xx_clk to npcm_clk hw/misc: Support 8-bytes memop in NPCM GCR module hw/misc: Store DRAM size in NPCM8XX GCR Module hw/misc: Add support for NPCM8XX GCR hw/misc: Add nr_regs and cold_reset_values to NPCM GCR hw/misc: Move NPCM7XX GCR to NPCM GCR hw/misc: Rename npcm7xx_gcr to npcm_gcr hw/ssi: Make flash size a property in NPCM7XX FIU pc-bios: Add NPCM8XX vBootrom roms: Update vbootrom to 1287b6e target/arm: Use uint32_t in t32_expandimm_imm() Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX hw/cpu/arm_mpcore: Remove default values for GIC external IRQs ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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0ad46bbb |
| 19-Feb-2025 |
Hao Wu <wuhaotsh@google.com> |
hw/misc: Store DRAM size in NPCM8XX GCR Module
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this
hw/misc: Store DRAM size in NPCM8XX GCR Module
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this information directly similar to the NPCM7XX's INCTR3 register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-9-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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d9ffb75f |
| 19-Feb-2025 |
Hao Wu <wuhaotsh@google.com> |
hw/misc: Add support for NPCM8XX GCR
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-8-wuhaotsh@google.com Signed
hw/misc: Add support for NPCM8XX GCR
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-8-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8ca2021b |
| 19-Feb-2025 |
Hao Wu <wuhaotsh@google.com> |
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
These 2 values are different between NPCM7XX and NPCM8XX GCRs. So we add them to the class and assign different values to them.
Reviewed-by: P
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
These 2 values are different between NPCM7XX and NPCM8XX GCRs. So we add them to the class and assign different values to them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-7-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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c99064e6 |
| 19-Feb-2025 |
Hao Wu <wuhaotsh@google.com> |
hw/misc: Move NPCM7XX GCR to NPCM GCR
A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties.
Reviewed-by: Peter Maydell <p
hw/misc: Move NPCM7XX GCR to NPCM GCR
A lot of NPCM7XX and NPCM8XX GCR modules share the same code, this commit moves the NPCM7XX GCR to NPCM GCR for these properties.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-6-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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506af233 |
| 19-Feb-2025 |
Hao Wu <wuhaotsh@google.com> |
hw/misc: Rename npcm7xx_gcr to npcm_gcr
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module needs to fit both. This commit changes the name of the GCR module. Future commits will add
hw/misc: Rename npcm7xx_gcr to npcm_gcr
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module needs to fit both. This commit changes the name of the GCR module. Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20250219184609.1839281-5-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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