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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_spd.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Based on JEDEC Standard No. 21-C, 4.1.2.L-4:
18 /* block 1: module specific parameters sub-block */
20 /* block 1: hybrid memory parameters sub-block */
171 unsigned char byte_20; /* cas latencies supported, first byte */
172 unsigned char byte_21; /* cas latencies supported, second byte */
173 unsigned char byte_22; /* cas latencies supported, third byte */
174 unsigned char byte_23; /* cas latencies supported, fourth byte */
175 unsigned char byte_24; /* min cas latency time (t aa min), mtb */
176 unsigned char byte_25; /* min ras to cas delay time (t rcd min), mtb */
[all …]
H A Dmv_ddr_topology.h1 /* SPDX-License-Identifier: GPL-2.0 */
99 MV_DDR_CFG_STATIC, /* based on data from user in register-value format */
117 MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
120 MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
122 MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
123 MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
124 MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
125 MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
126 MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
128 MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
[all …]
/openbmc/linux/drivers/edac/
H A Di5000_edac.c12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
102 /* Non-Retry or redundant Retry errors */
276 /* Defines to extract the various fields from the
277 * MTRx - Memory Technology Registers
290 /* enables the report of miscellaneous messages as CE errors - default off */
363 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
364 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
372 * Non-Recoverable Error */
373 u16 nrecmema; /* Non-Recoverable Mem log A */
374 u32 nrecmemb; /* Non-Recoverable Mem log B */
[all …]
H A Di5100_edac.c9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
13 * can not reflect this configuration so instead the chip-select
15 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
70 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
85 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
86 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
127 return a & ((1 << 8) - 1); in i5100_spddata_data()
[all …]
H A Di5400_edac.c18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
23 * 4 dimm's, each with up to 8GB.
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
[all …]
H A Di7300_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
16 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
48 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
49 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
50 * Each channel can have to 8 DIMM sets (called as SLOTS)
115 /* FIXME: Why do we need to have this static? */
150 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
151 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
153 * Each memory slot may have up to 2 AMB interfaces, one for income and another
[all …]
H A Dr82600_edac.c12 * Written with reference to 82600 High Integration Dual PCI System
14 * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15 * references to this document given in []
34 * supports up to four banks of memory. The four banks can support a mix of
36 * each of which can be any size from 16MB to 512MB. Both registered (control
38 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
49 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
74 * 1=Drive ECC bits to 0 during
81 * 2 CAS# Latency 0=3clks 1=2clks
83 * 1 RAS# to CAS# Delay 0=3 1=2
[all …]
H A Di82975x_edac.c34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
37 * 31:7 128 byte cache-line address
50 * More - See Page 65 of Intel DocSheet.
58 * 9 non-DRAM lock error (ndlock)
76 * 9 non-DRAM lock error (ndlock)
105 * 31:14 Base Addr of 16K memory-mapped
108 * 0 mem-mapped config space enable
111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
118 * 7 set to 1 in highest DRB of
122 * 1:0 set to 0
[all …]
/openbmc/u-boot/include/
H A Dddr_spd.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
10 * Format from "JEDEC Standard No. 21-C,
29 unsigned char min_delay; /* 15 for Back to Back Random Address */
32 unsigned char cas_lat; /* 18 CAS# Latencies Supported */
37 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
39 Clk @ CL=X-0.5 (tAC) */
40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
[all …]
H A Dspd.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Serial Presence Detect (SPD) EEPROM format according to the
30 unsigned char min_delay; /* 15 for Back to Back Random Address */
33 unsigned char cas_lat; /* 18 CAS# Latencies Supported */
38 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */
39 unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */
41 unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
22 u32 t_ras; /* Active to precharge command period */
23 u32 t_srex; /* Self-refresh exit time */
26 u32 t_rc; /* Active to active command period */
27 u32 t_rfc; /* Auto-refresh period */
28 u32 t_xsr; /* Exit self-refresh to active command time */
29 u32 t_rrd; /* Active bank A to active bank B latency */
30 u32 t_mrd; /* Load mode register to active command time */
31 u32 t_cdlr; /* Last data in to read command time */
36 u32 rascas0; /* RAS and CAS latencies for the SDRAM */
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dpm-imx6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2014 Freescale Semiconductor, Inc.
13 #include <linux/irqchip/arm-gic.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include <asm/proc-fns.h>
101 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
113 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
125 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
140 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
146 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
52 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
112 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
113 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
116 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry …
135 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
137 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
138 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
139 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
140 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h1 /* SPDX-License-Identifier: Intel */
50 * cl: DRAM CAS Latency in clocks
51 * ras: ACT to PRE command period
52 * wtr: Delay from start of internal write transaction to internal read command
53 * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
54 * faw: Four activate window (JESD79 specific to page size 1K/2K)
56 * ras/wtr/rrd/faw timings are in picoseconds
58 * Refer to JEDEC spec (or DRAM datasheet) when changing these values.
63 uint32_t ras; member
83 /* need to save for the case of frequency change */
[all …]
/openbmc/qemu/hw/i2c/
H A Dsmbus_eeprom.c6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
31 #include "hw/qdev-properties.h"
38 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
55 uint8_t *data = eeprom->data; in eeprom_receive_byte()
56 uint8_t val = data[eeprom->offset++]; in eeprom_receive_byte()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dddr4_dimm_params.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
7 * from ddr3 spd, please refer to the spec
8 * JEDEC standard No.21-C 4_01_02_12R23A.pdf
32 * To simplify each rank size = total DIMM size / Number of Package Ranks
35 * SPD byte4 - sdram density and banks
46 * SPD byte13 - module memory bus width
53 * SPD byte12 - module organization
60 * SPD byte12 - module organization
[all …]
H A Dddr3_dimm_params.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 * from ddr3 spd, please refer to the spec
8 * JEDEC standard No.21-C 4_01_02_11R18.pdf
27 * SPD byte4 - sdram density and banks
37 * SPD byte8 - module memory bus width
44 * SPD byte7 - module organiztion
61 if ((spd->density_banks & 0xf) < 7) in compute_ranksize()
62 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; in compute_ranksize()
63 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
[all …]
H A Dinteractive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
112 printf("trying to write past end of data\n"); in fsl_ddr_generic_edit()
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); in fsl_ddr_spd_edit()
145 sizeof((common_timing_params_t *)0)->x, 0}
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; in lowest_common_dimm_parameters_edit()
210 sizeof((dimm_params_t *)0)->x, 0}
212 sizeof((dimm_params_t *)0)->x, 1}
220 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); in fsl_ddr_dimm_parameters_edit()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
[all …]
/openbmc/u-boot/include/faraday/
H A Dftsdmc021.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 * FTSDMC021 - SDRAM Controller
18 unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */
19 unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */
20 unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */
21 unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */
22 unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */
23 unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */
24 unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */
[all …]
/openbmc/u-boot/cmd/
H A Di2c.c1 // SPDX-License-Identifier: GPL-2.0+
13 * I2C Functions similar to the standard memory functions.
25 * matches at least half of the data sheets :-/.
30 * Many non-memory chips have multiple registers and {addr} is used
31 * as the register index. Some non-memory chips have only one register
38 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
42 * successive reads using the I2C auto-incrementing memory pointer.
44 * If you are manipulating a large memory with 2-byte addresses, use
52 * {addr} field (since .1 is the default, it doesn't actually have to
93 /* If only one I2C bus is present, the list of devices to ignore when
[all …]
/openbmc/u-boot/board/bachmann/ot1200/
H A Dot1200_spl.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/mx6-ddr.h>
12 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
18 /* SDCKE[0:1]: 100k pull-up */
21 /* SDBA2: pull-up disabled */
23 /* SDODT[0:1]: 100k pull-up, 48 ohm */
77 .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
78 .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
89 /* MT41K128M16JT-125 */
115 /* Read Calibration: DQS delay relative to DQ read access */
[all …]
/openbmc/u-boot/board/freescale/mx6memcal/
H A Dspl.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
58 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
64 /* SDCKE[0:1]: 100k pull-up */
67 /* SDBA2: pull-up disabled */
69 /* SDODT[0:1]: 100k pull-up, 40 ohm */
117 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
123 /* SDCKE[0:1]: 100k pull-up */
126 /* SDBA2: pull-up disabled */
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
29 * with RTEMS objects to produce an executable application, does not
30 * by itself cause the resulting executable application to be covered
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
[all …]

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