asm/arch-lpc32xx/emc.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
22 	u32 t_ras;		/* Active to precharge command period        */
23 	u32 t_srex;		/* Self-refresh exit time                    */
26 	u32 t_rc;		/* Active to active command period           */
27 	u32 t_rfc;		/* Auto-refresh period                       */
28 	u32 t_xsr;		/* Exit self-refresh to active command time  */
29 	u32 t_rrd;		/* Active bank A to active bank B latency    */
30 	u32 t_mrd;		/* Load mode register to active command time */
31 	u32 t_cdlr;		/* Last data in to read command time         */
36 	u32 rascas0;		/* RAS and CAS latencies for the SDRAM       */
39 	u32 rascas1;		/* RAS and CAS latencies for the SDRAM       */
43 		u32 waitwen;	/* Delay from chip select to write enable    */
44 		u32 waitoen;	/* Delay to output enable                    */
45 		u32 waitrd;	/* Delay to a read access                    */
47 		u32 waitwr;	/* Delay to a write access                   */
71 #define EMC_STAT_WAITWEN(n)		(((n) - 1) & 0x0F)
73 #define EMC_STAT_WAITRD(n)		(((n) - 1) & 0x1F)
74 #define EMC_STAT_WAITPAGE(n)		(((n) - 1) & 0x1F)
75 #define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
76 #define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)