Lines Matching +full:ras +full:- +full:to +full:- +full:cas
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
112 printf("trying to write past end of data\n"); in fsl_ddr_generic_edit()
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); in fsl_ddr_spd_edit()
145 sizeof((common_timing_params_t *)0)->x, 0}
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; in lowest_common_dimm_parameters_edit()
210 sizeof((dimm_params_t *)0)->x, 0}
212 sizeof((dimm_params_t *)0)->x, 1}
220 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); in fsl_ddr_dimm_parameters_edit()
410 if (pdimm->n_ranks == 0) { in print_dimm_parameters()
415 printf("module part name = %s\n", pdimm->mpart); in print_dimm_parameters()
417 pdimm->rank_density, pdimm->rank_density / 0x100000); in print_dimm_parameters()
419 pdimm->capacity, pdimm->capacity / 0x100000); in print_dimm_parameters()
421 pdimm->burst_lengths_bitmask); in print_dimm_parameters()
423 pdimm->base_address, in print_dimm_parameters()
424 (pdimm->base_address >> 32), in print_dimm_parameters()
425 pdimm->base_address & 0xFFFFFFFF); in print_dimm_parameters()
477 plcd_dimm_params->tckmin_x_ps, in print_lowest_common_dimm_parameters()
478 picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); in print_lowest_common_dimm_parameters()
480 plcd_dimm_params->tckmax_ps, in print_lowest_common_dimm_parameters()
481 picos_to_mhz(plcd_dimm_params->tckmax_ps)); in print_lowest_common_dimm_parameters()
483 plcd_dimm_params->all_dimms_burst_lengths_bitmask); in print_lowest_common_dimm_parameters()
488 plcd_dimm_params->total_mem, in print_lowest_common_dimm_parameters()
489 plcd_dimm_params->total_mem / 0x100000); in print_lowest_common_dimm_parameters()
491 plcd_dimm_params->base_address, in print_lowest_common_dimm_parameters()
492 plcd_dimm_params->base_address / 0x100000); in print_lowest_common_dimm_parameters()
496 sizeof((memctl_options_t *)0)->x, 0}
499 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
506 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); in fsl_ddr_options_edit()
563 * These can probably be changed to 2T_EN and 3T_EN in fsl_ddr_options_edit()
601 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
604 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
689 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); in print_fsl_memctl_config_regs()
785 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); in fsl_ddr_regs_edit()
794 ddr->debug[i] = value; in fsl_ddr_regs_edit()
802 sizeof((memctl_options_t *)0)->x, 1}
857 * These can probably be changed to 2T_EN and 3T_EN in print_memctl_options()
895 printf("%-3d : %02x %s\n", 0, spd->info_size, in ddr1_spd_dump()
896 " spd->info_size, * 0 # bytes written into serial memory *"); in ddr1_spd_dump()
897 printf("%-3d : %02x %s\n", 1, spd->chip_size, in ddr1_spd_dump()
898 " spd->chip_size, * 1 Total # bytes of SPD memory device *"); in ddr1_spd_dump()
899 printf("%-3d : %02x %s\n", 2, spd->mem_type, in ddr1_spd_dump()
900 " spd->mem_type, * 2 Fundamental memory type *"); in ddr1_spd_dump()
901 printf("%-3d : %02x %s\n", 3, spd->nrow_addr, in ddr1_spd_dump()
902 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); in ddr1_spd_dump()
903 printf("%-3d : %02x %s\n", 4, spd->ncol_addr, in ddr1_spd_dump()
904 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); in ddr1_spd_dump()
905 printf("%-3d : %02x %s\n", 5, spd->nrows, in ddr1_spd_dump()
906 " spd->nrows * 5 # of DIMM Banks *"); in ddr1_spd_dump()
907 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, in ddr1_spd_dump()
908 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); in ddr1_spd_dump()
909 printf("%-3d : %02x %s\n", 7, spd->dataw_msb, in ddr1_spd_dump()
910 " spd->dataw_msb, * 7 Data Width msb of this assembly *"); in ddr1_spd_dump()
911 printf("%-3d : %02x %s\n", 8, spd->voltage, in ddr1_spd_dump()
912 " spd->voltage, * 8 Voltage intf std of this assembly *"); in ddr1_spd_dump()
913 printf("%-3d : %02x %s\n", 9, spd->clk_cycle, in ddr1_spd_dump()
914 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); in ddr1_spd_dump()
915 printf("%-3d : %02x %s\n", 10, spd->clk_access, in ddr1_spd_dump()
916 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); in ddr1_spd_dump()
917 printf("%-3d : %02x %s\n", 11, spd->config, in ddr1_spd_dump()
918 " spd->config, * 11 DIMM Configuration type *"); in ddr1_spd_dump()
919 printf("%-3d : %02x %s\n", 12, spd->refresh, in ddr1_spd_dump()
920 " spd->refresh, * 12 Refresh Rate/Type *"); in ddr1_spd_dump()
921 printf("%-3d : %02x %s\n", 13, spd->primw, in ddr1_spd_dump()
922 " spd->primw, * 13 Primary SDRAM Width *"); in ddr1_spd_dump()
923 printf("%-3d : %02x %s\n", 14, spd->ecw, in ddr1_spd_dump()
924 " spd->ecw, * 14 Error Checking SDRAM width *"); in ddr1_spd_dump()
925 printf("%-3d : %02x %s\n", 15, spd->min_delay, in ddr1_spd_dump()
926 " spd->min_delay, * 15 Back to Back Random Access *"); in ddr1_spd_dump()
927 printf("%-3d : %02x %s\n", 16, spd->burstl, in ddr1_spd_dump()
928 " spd->burstl, * 16 Burst Lengths Supported *"); in ddr1_spd_dump()
929 printf("%-3d : %02x %s\n", 17, spd->nbanks, in ddr1_spd_dump()
930 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); in ddr1_spd_dump()
931 printf("%-3d : %02x %s\n", 18, spd->cas_lat, in ddr1_spd_dump()
932 " spd->cas_lat, * 18 CAS# Latencies Supported *"); in ddr1_spd_dump()
933 printf("%-3d : %02x %s\n", 19, spd->cs_lat, in ddr1_spd_dump()
934 " spd->cs_lat, * 19 Chip Select Latency *"); in ddr1_spd_dump()
935 printf("%-3d : %02x %s\n", 20, spd->write_lat, in ddr1_spd_dump()
936 " spd->write_lat, * 20 Write Latency/Recovery *"); in ddr1_spd_dump()
937 printf("%-3d : %02x %s\n", 21, spd->mod_attr, in ddr1_spd_dump()
938 " spd->mod_attr, * 21 SDRAM Module Attributes *"); in ddr1_spd_dump()
939 printf("%-3d : %02x %s\n", 22, spd->dev_attr, in ddr1_spd_dump()
940 " spd->dev_attr, * 22 SDRAM Device Attributes *"); in ddr1_spd_dump()
941 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, in ddr1_spd_dump()
942 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); in ddr1_spd_dump()
943 printf("%-3d : %02x %s\n", 24, spd->clk_access2, in ddr1_spd_dump()
944 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); in ddr1_spd_dump()
945 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, in ddr1_spd_dump()
946 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); in ddr1_spd_dump()
947 printf("%-3d : %02x %s\n", 26, spd->clk_access3, in ddr1_spd_dump()
948 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); in ddr1_spd_dump()
949 printf("%-3d : %02x %s\n", 27, spd->trp, in ddr1_spd_dump()
950 " spd->trp, * 27 Min Row Precharge Time (tRP)*"); in ddr1_spd_dump()
951 printf("%-3d : %02x %s\n", 28, spd->trrd, in ddr1_spd_dump()
952 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); in ddr1_spd_dump()
953 printf("%-3d : %02x %s\n", 29, spd->trcd, in ddr1_spd_dump()
954 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); in ddr1_spd_dump()
955 printf("%-3d : %02x %s\n", 30, spd->tras, in ddr1_spd_dump()
956 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); in ddr1_spd_dump()
957 printf("%-3d : %02x %s\n", 31, spd->bank_dens, in ddr1_spd_dump()
958 " spd->bank_dens, * 31 Density of each bank on module *"); in ddr1_spd_dump()
959 printf("%-3d : %02x %s\n", 32, spd->ca_setup, in ddr1_spd_dump()
960 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); in ddr1_spd_dump()
961 printf("%-3d : %02x %s\n", 33, spd->ca_hold, in ddr1_spd_dump()
962 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); in ddr1_spd_dump()
963 printf("%-3d : %02x %s\n", 34, spd->data_setup, in ddr1_spd_dump()
964 " spd->data_setup, * 34 Data signal input setup time *"); in ddr1_spd_dump()
965 printf("%-3d : %02x %s\n", 35, spd->data_hold, in ddr1_spd_dump()
966 " spd->data_hold, * 35 Data signal input hold time *"); in ddr1_spd_dump()
967 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], in ddr1_spd_dump()
968 " spd->res_36_40[0], * 36 Reserved / tWR *"); in ddr1_spd_dump()
969 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], in ddr1_spd_dump()
970 " spd->res_36_40[1], * 37 Reserved / tWTR *"); in ddr1_spd_dump()
971 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], in ddr1_spd_dump()
972 " spd->res_36_40[2], * 38 Reserved / tRTP *"); in ddr1_spd_dump()
973 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], in ddr1_spd_dump()
974 " spd->res_36_40[3], * 39 Reserved / mem_probe *"); in ddr1_spd_dump()
975 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], in ddr1_spd_dump()
976 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); in ddr1_spd_dump()
977 printf("%-3d : %02x %s\n", 41, spd->trc, in ddr1_spd_dump()
978 " spd->trc, * 41 Min Active to Auto refresh time tRC *"); in ddr1_spd_dump()
979 printf("%-3d : %02x %s\n", 42, spd->trfc, in ddr1_spd_dump()
980 " spd->trfc, * 42 Min Auto to Active period tRFC *"); in ddr1_spd_dump()
981 printf("%-3d : %02x %s\n", 43, spd->tckmax, in ddr1_spd_dump()
982 " spd->tckmax, * 43 Max device cycle time tCKmax *"); in ddr1_spd_dump()
983 printf("%-3d : %02x %s\n", 44, spd->tdqsq, in ddr1_spd_dump()
984 " spd->tdqsq, * 44 Max DQS to DQ skew *"); in ddr1_spd_dump()
985 printf("%-3d : %02x %s\n", 45, spd->tqhs, in ddr1_spd_dump()
986 " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); in ddr1_spd_dump()
987 printf("%-3d : %02x %s\n", 46, spd->res_46, in ddr1_spd_dump()
988 " spd->res_46, * 46 Reserved/ PLL Relock time *"); in ddr1_spd_dump()
989 printf("%-3d : %02x %s\n", 47, spd->dimm_height, in ddr1_spd_dump()
990 " spd->dimm_height * 47 SDRAM DIMM Height *"); in ddr1_spd_dump()
992 printf("%-3d-%3d: ", 48, 61); in ddr1_spd_dump()
995 printf("%02x", spd->res_48_61[i]); in ddr1_spd_dump()
997 printf(" * 48-61 IDD in SPD and Reserved space *\n"); in ddr1_spd_dump()
999 printf("%-3d : %02x %s\n", 62, spd->spd_rev, in ddr1_spd_dump()
1000 " spd->spd_rev, * 62 SPD Data Revision Code *"); in ddr1_spd_dump()
1001 printf("%-3d : %02x %s\n", 63, spd->cksum, in ddr1_spd_dump()
1002 " spd->cksum, * 63 Checksum for bytes 0-62 *"); in ddr1_spd_dump()
1003 printf("%-3d-%3d: ", 64, 71); in ddr1_spd_dump()
1006 printf("%02x", spd->mid[i]); in ddr1_spd_dump()
1008 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); in ddr1_spd_dump()
1009 printf("%-3d : %02x %s\n", 72, spd->mloc, in ddr1_spd_dump()
1010 " spd->mloc, * 72 Manufacturing Location *"); in ddr1_spd_dump()
1012 printf("%-3d-%3d: >>", 73, 90); in ddr1_spd_dump()
1015 printf("%c", spd->mpart[i]); in ddr1_spd_dump()
1019 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], in ddr1_spd_dump()
1021 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], in ddr1_spd_dump()
1023 printf("%-3d-%3d: ", 95, 98); in ddr1_spd_dump()
1026 printf("%02x", spd->sernum[i]); in ddr1_spd_dump()
1030 printf("%-3d-%3d: ", 99, 127); in ddr1_spd_dump()
1033 printf("%02x", spd->mspec[i]); in ddr1_spd_dump()
1044 printf("%-3d : %02x %s\n", 0, spd->info_size, in ddr2_spd_dump()
1045 " spd->info_size, * 0 # bytes written into serial memory *"); in ddr2_spd_dump()
1046 printf("%-3d : %02x %s\n", 1, spd->chip_size, in ddr2_spd_dump()
1047 " spd->chip_size, * 1 Total # bytes of SPD memory device *"); in ddr2_spd_dump()
1048 printf("%-3d : %02x %s\n", 2, spd->mem_type, in ddr2_spd_dump()
1049 " spd->mem_type, * 2 Fundamental memory type *"); in ddr2_spd_dump()
1050 printf("%-3d : %02x %s\n", 3, spd->nrow_addr, in ddr2_spd_dump()
1051 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); in ddr2_spd_dump()
1052 printf("%-3d : %02x %s\n", 4, spd->ncol_addr, in ddr2_spd_dump()
1053 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); in ddr2_spd_dump()
1054 printf("%-3d : %02x %s\n", 5, spd->mod_ranks, in ddr2_spd_dump()
1055 " spd->mod_ranks * 5 # of Module Rows on this assembly *"); in ddr2_spd_dump()
1056 printf("%-3d : %02x %s\n", 6, spd->dataw, in ddr2_spd_dump()
1057 " spd->dataw, * 6 Data Width of this assembly *"); in ddr2_spd_dump()
1058 printf("%-3d : %02x %s\n", 7, spd->res_7, in ddr2_spd_dump()
1059 " spd->res_7, * 7 Reserved *"); in ddr2_spd_dump()
1060 printf("%-3d : %02x %s\n", 8, spd->voltage, in ddr2_spd_dump()
1061 " spd->voltage, * 8 Voltage intf std of this assembly *"); in ddr2_spd_dump()
1062 printf("%-3d : %02x %s\n", 9, spd->clk_cycle, in ddr2_spd_dump()
1063 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); in ddr2_spd_dump()
1064 printf("%-3d : %02x %s\n", 10, spd->clk_access, in ddr2_spd_dump()
1065 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); in ddr2_spd_dump()
1066 printf("%-3d : %02x %s\n", 11, spd->config, in ddr2_spd_dump()
1067 " spd->config, * 11 DIMM Configuration type *"); in ddr2_spd_dump()
1068 printf("%-3d : %02x %s\n", 12, spd->refresh, in ddr2_spd_dump()
1069 " spd->refresh, * 12 Refresh Rate/Type *"); in ddr2_spd_dump()
1070 printf("%-3d : %02x %s\n", 13, spd->primw, in ddr2_spd_dump()
1071 " spd->primw, * 13 Primary SDRAM Width *"); in ddr2_spd_dump()
1072 printf("%-3d : %02x %s\n", 14, spd->ecw, in ddr2_spd_dump()
1073 " spd->ecw, * 14 Error Checking SDRAM width *"); in ddr2_spd_dump()
1074 printf("%-3d : %02x %s\n", 15, spd->res_15, in ddr2_spd_dump()
1075 " spd->res_15, * 15 Reserved *"); in ddr2_spd_dump()
1076 printf("%-3d : %02x %s\n", 16, spd->burstl, in ddr2_spd_dump()
1077 " spd->burstl, * 16 Burst Lengths Supported *"); in ddr2_spd_dump()
1078 printf("%-3d : %02x %s\n", 17, spd->nbanks, in ddr2_spd_dump()
1079 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); in ddr2_spd_dump()
1080 printf("%-3d : %02x %s\n", 18, spd->cas_lat, in ddr2_spd_dump()
1081 " spd->cas_lat, * 18 CAS# Latencies Supported *"); in ddr2_spd_dump()
1082 printf("%-3d : %02x %s\n", 19, spd->mech_char, in ddr2_spd_dump()
1083 " spd->mech_char, * 19 Mechanical Characteristics *"); in ddr2_spd_dump()
1084 printf("%-3d : %02x %s\n", 20, spd->dimm_type, in ddr2_spd_dump()
1085 " spd->dimm_type, * 20 DIMM type *"); in ddr2_spd_dump()
1086 printf("%-3d : %02x %s\n", 21, spd->mod_attr, in ddr2_spd_dump()
1087 " spd->mod_attr, * 21 SDRAM Module Attributes *"); in ddr2_spd_dump()
1088 printf("%-3d : %02x %s\n", 22, spd->dev_attr, in ddr2_spd_dump()
1089 " spd->dev_attr, * 22 SDRAM Device Attributes *"); in ddr2_spd_dump()
1090 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, in ddr2_spd_dump()
1091 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); in ddr2_spd_dump()
1092 printf("%-3d : %02x %s\n", 24, spd->clk_access2, in ddr2_spd_dump()
1093 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); in ddr2_spd_dump()
1094 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, in ddr2_spd_dump()
1095 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); in ddr2_spd_dump()
1096 printf("%-3d : %02x %s\n", 26, spd->clk_access3, in ddr2_spd_dump()
1097 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); in ddr2_spd_dump()
1098 printf("%-3d : %02x %s\n", 27, spd->trp, in ddr2_spd_dump()
1099 " spd->trp, * 27 Min Row Precharge Time (tRP)*"); in ddr2_spd_dump()
1100 printf("%-3d : %02x %s\n", 28, spd->trrd, in ddr2_spd_dump()
1101 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); in ddr2_spd_dump()
1102 printf("%-3d : %02x %s\n", 29, spd->trcd, in ddr2_spd_dump()
1103 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); in ddr2_spd_dump()
1104 printf("%-3d : %02x %s\n", 30, spd->tras, in ddr2_spd_dump()
1105 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); in ddr2_spd_dump()
1106 printf("%-3d : %02x %s\n", 31, spd->rank_dens, in ddr2_spd_dump()
1107 " spd->rank_dens, * 31 Density of each rank on module *"); in ddr2_spd_dump()
1108 printf("%-3d : %02x %s\n", 32, spd->ca_setup, in ddr2_spd_dump()
1109 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); in ddr2_spd_dump()
1110 printf("%-3d : %02x %s\n", 33, spd->ca_hold, in ddr2_spd_dump()
1111 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); in ddr2_spd_dump()
1112 printf("%-3d : %02x %s\n", 34, spd->data_setup, in ddr2_spd_dump()
1113 " spd->data_setup, * 34 Data signal input setup time *"); in ddr2_spd_dump()
1114 printf("%-3d : %02x %s\n", 35, spd->data_hold, in ddr2_spd_dump()
1115 " spd->data_hold, * 35 Data signal input hold time *"); in ddr2_spd_dump()
1116 printf("%-3d : %02x %s\n", 36, spd->twr, in ddr2_spd_dump()
1117 " spd->twr, * 36 Write Recovery time tWR *"); in ddr2_spd_dump()
1118 printf("%-3d : %02x %s\n", 37, spd->twtr, in ddr2_spd_dump()
1119 " spd->twtr, * 37 Int write to read delay tWTR *"); in ddr2_spd_dump()
1120 printf("%-3d : %02x %s\n", 38, spd->trtp, in ddr2_spd_dump()
1121 " spd->trtp, * 38 Int read to precharge delay tRTP *"); in ddr2_spd_dump()
1122 printf("%-3d : %02x %s\n", 39, spd->mem_probe, in ddr2_spd_dump()
1123 " spd->mem_probe, * 39 Mem analysis probe characteristics *"); in ddr2_spd_dump()
1124 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, in ddr2_spd_dump()
1125 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); in ddr2_spd_dump()
1126 printf("%-3d : %02x %s\n", 41, spd->trc, in ddr2_spd_dump()
1127 " spd->trc, * 41 Min Active to Auto refresh time tRC *"); in ddr2_spd_dump()
1128 printf("%-3d : %02x %s\n", 42, spd->trfc, in ddr2_spd_dump()
1129 " spd->trfc, * 42 Min Auto to Active period tRFC *"); in ddr2_spd_dump()
1130 printf("%-3d : %02x %s\n", 43, spd->tckmax, in ddr2_spd_dump()
1131 " spd->tckmax, * 43 Max device cycle time tCKmax *"); in ddr2_spd_dump()
1132 printf("%-3d : %02x %s\n", 44, spd->tdqsq, in ddr2_spd_dump()
1133 " spd->tdqsq, * 44 Max DQS to DQ skew *"); in ddr2_spd_dump()
1134 printf("%-3d : %02x %s\n", 45, spd->tqhs, in ddr2_spd_dump()
1135 " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); in ddr2_spd_dump()
1136 printf("%-3d : %02x %s\n", 46, spd->pll_relock, in ddr2_spd_dump()
1137 " spd->pll_relock, * 46 PLL Relock time *"); in ddr2_spd_dump()
1138 printf("%-3d : %02x %s\n", 47, spd->t_casemax, in ddr2_spd_dump()
1139 " spd->t_casemax, * 47 t_casemax *"); in ddr2_spd_dump()
1140 printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, in ddr2_spd_dump()
1141 " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " in ddr2_spd_dump()
1142 "from Top (Case) to Ambient (Psi T-A DRAM) *"); in ddr2_spd_dump()
1143 printf("%-3d : %02x %s\n", 49, spd->dt0_mode, in ddr2_spd_dump()
1144 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1145 "Ambient due to Activate-Precharge/Mode Bits " in ddr2_spd_dump()
1147 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, in ddr2_spd_dump()
1148 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1149 "Ambient due to Precharge/Quiet Standby " in ddr2_spd_dump()
1151 printf("%-3d : %02x %s\n", 51, spd->dt2p, in ddr2_spd_dump()
1152 " spd->dt2p, * 51 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1153 "Ambient due to Precharge Power-Down (DT2P) *"); in ddr2_spd_dump()
1154 printf("%-3d : %02x %s\n", 52, spd->dt3n, in ddr2_spd_dump()
1155 " spd->dt3n, * 52 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1156 "Ambient due to Active Standby (DT3N) *"); in ddr2_spd_dump()
1157 printf("%-3d : %02x %s\n", 53, spd->dt3pfast, in ddr2_spd_dump()
1158 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1159 "Ambient due to Active Power-Down with Fast PDN Exit " in ddr2_spd_dump()
1161 printf("%-3d : %02x %s\n", 54, spd->dt3pslow, in ddr2_spd_dump()
1162 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1163 "Ambient due to Active Power-Down with Slow PDN Exit " in ddr2_spd_dump()
1165 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, in ddr2_spd_dump()
1166 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1167 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " in ddr2_spd_dump()
1169 printf("%-3d : %02x %s\n", 56, spd->dt5b, in ddr2_spd_dump()
1170 " spd->dt5b, * 56 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1171 "Ambient due to Burst Refresh (DT5B) *"); in ddr2_spd_dump()
1172 printf("%-3d : %02x %s\n", 57, spd->dt7, in ddr2_spd_dump()
1173 " spd->dt7, * 57 DRAM Case Temperature Rise from " in ddr2_spd_dump()
1174 "Ambient due to Bank Interleave Reads with " in ddr2_spd_dump()
1175 "Auto-Precharge (DT7) *"); in ddr2_spd_dump()
1176 printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, in ddr2_spd_dump()
1177 " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" in ddr2_spd_dump()
1178 " Top (Case) to Ambient (Psi T-A PLL) *"); in ddr2_spd_dump()
1179 printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, in ddr2_spd_dump()
1180 " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" in ddr2_spd_dump()
1181 " from Top (Case) to Ambient (Psi T-A Register) *"); in ddr2_spd_dump()
1182 printf("%-3d : %02x %s\n", 60, spd->dtpllactive, in ddr2_spd_dump()
1183 " spd->dtpllactive, * 60 PLL Case Temperature Rise from " in ddr2_spd_dump()
1184 "Ambient due to PLL Active (DT PLL Active) *"); in ddr2_spd_dump()
1185 printf("%-3d : %02x %s\n", 61, spd->dtregact, in ddr2_spd_dump()
1186 " spd->dtregact, " in ddr2_spd_dump()
1187 "* 61 Register Case Temperature Rise from Ambient due to " in ddr2_spd_dump()
1189 printf("%-3d : %02x %s\n", 62, spd->spd_rev, in ddr2_spd_dump()
1190 " spd->spd_rev, * 62 SPD Data Revision Code *"); in ddr2_spd_dump()
1191 printf("%-3d : %02x %s\n", 63, spd->cksum, in ddr2_spd_dump()
1192 " spd->cksum, * 63 Checksum for bytes 0-62 *"); in ddr2_spd_dump()
1194 printf("%-3d-%3d: ", 64, 71); in ddr2_spd_dump()
1197 printf("%02x", spd->mid[i]); in ddr2_spd_dump()
1199 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); in ddr2_spd_dump()
1201 printf("%-3d : %02x %s\n", 72, spd->mloc, in ddr2_spd_dump()
1202 " spd->mloc, * 72 Manufacturing Location *"); in ddr2_spd_dump()
1204 printf("%-3d-%3d: >>", 73, 90); in ddr2_spd_dump()
1206 printf("%c", spd->mpart[i]); in ddr2_spd_dump()
1211 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], in ddr2_spd_dump()
1213 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], in ddr2_spd_dump()
1215 printf("%-3d-%3d: ", 95, 98); in ddr2_spd_dump()
1218 printf("%02x", spd->sernum[i]); in ddr2_spd_dump()
1222 printf("%-3d-%3d: ", 99, 127); in ddr2_spd_dump()
1224 printf("%02x", spd->mspec[i]); in ddr2_spd_dump()
1236 /* General Section: Bytes 0-59 */ in ddr3_spd_dump()
1238 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); in ddr3_spd_dump()
1240 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); in ddr3_spd_dump()
1242 PRINT_NXS(0, spd->info_size_crc, in ddr3_spd_dump()
1245 PRINT_NXS(1, spd->spd_rev, in ddr3_spd_dump()
1247 PRINT_NXS(2, spd->mem_type, in ddr3_spd_dump()
1249 PRINT_NXS(3, spd->module_type, in ddr3_spd_dump()
1251 PRINT_NXS(4, spd->density_banks, in ddr3_spd_dump()
1253 PRINT_NXS(5, spd->addressing, in ddr3_spd_dump()
1255 PRINT_NXS(6, spd->module_vdd, in ddr3_spd_dump()
1257 PRINT_NXS(7, spd->organization, in ddr3_spd_dump()
1259 PRINT_NXS(8, spd->bus_width, in ddr3_spd_dump()
1261 PRINT_NXS(9, spd->ftb_div, in ddr3_spd_dump()
1263 PRINT_NXS(10, spd->mtb_dividend, in ddr3_spd_dump()
1265 PRINT_NXS(11, spd->mtb_divisor, in ddr3_spd_dump()
1267 PRINT_NXS(12, spd->tck_min, in ddr3_spd_dump()
1269 PRINT_NXS(13, spd->res_13, in ddr3_spd_dump()
1271 PRINT_NXS(14, spd->caslat_lsb, in ddr3_spd_dump()
1272 "caslat_lsb CAS Latencies Supported, LSB"); in ddr3_spd_dump()
1273 PRINT_NXS(15, spd->caslat_msb, in ddr3_spd_dump()
1274 "caslat_msb CAS Latencies Supported, MSB"); in ddr3_spd_dump()
1275 PRINT_NXS(16, spd->taa_min, in ddr3_spd_dump()
1276 "taa_min Min CAS Latency Time"); in ddr3_spd_dump()
1277 PRINT_NXS(17, spd->twr_min, in ddr3_spd_dump()
1279 PRINT_NXS(18, spd->trcd_min, in ddr3_spd_dump()
1280 "trcd_min Min RAS# to CAS# Delay Time"); in ddr3_spd_dump()
1281 PRINT_NXS(19, spd->trrd_min, in ddr3_spd_dump()
1282 "trrd_min Min Row Active to Row Active Delay Time"); in ddr3_spd_dump()
1283 PRINT_NXS(20, spd->trp_min, in ddr3_spd_dump()
1285 PRINT_NXS(21, spd->tras_trc_ext, in ddr3_spd_dump()
1287 PRINT_NXS(22, spd->tras_min_lsb, in ddr3_spd_dump()
1288 "tras_min_lsb Min Active to Precharge Delay Time, LSB"); in ddr3_spd_dump()
1289 PRINT_NXS(23, spd->trc_min_lsb, in ddr3_spd_dump()
1290 "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); in ddr3_spd_dump()
1291 PRINT_NXS(24, spd->trfc_min_lsb, in ddr3_spd_dump()
1293 PRINT_NXS(25, spd->trfc_min_msb, in ddr3_spd_dump()
1295 PRINT_NXS(26, spd->twtr_min, in ddr3_spd_dump()
1296 "twtr_min Min Internal Write to Read Command Delay Time"); in ddr3_spd_dump()
1297 PRINT_NXS(27, spd->trtp_min, in ddr3_spd_dump()
1299 "Min Internal Read to Precharge Command Delay Time"); in ddr3_spd_dump()
1300 PRINT_NXS(28, spd->tfaw_msb, in ddr3_spd_dump()
1302 PRINT_NXS(29, spd->tfaw_min, in ddr3_spd_dump()
1304 PRINT_NXS(30, spd->opt_features, in ddr3_spd_dump()
1306 PRINT_NXS(31, spd->therm_ref_opt, in ddr3_spd_dump()
1308 PRINT_NXS(32, spd->therm_sensor, in ddr3_spd_dump()
1310 PRINT_NXS(33, spd->device_type, in ddr3_spd_dump()
1312 PRINT_NXS(34, spd->fine_tck_min, in ddr3_spd_dump()
1314 PRINT_NXS(35, spd->fine_taa_min, in ddr3_spd_dump()
1316 PRINT_NXS(36, spd->fine_trcd_min, in ddr3_spd_dump()
1318 PRINT_NXS(37, spd->fine_trp_min, in ddr3_spd_dump()
1320 PRINT_NXS(38, spd->fine_trc_min, in ddr3_spd_dump()
1323 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ in ddr3_spd_dump()
1326 printf("%02x ", spd->res_39_59[i - 39]); in ddr3_spd_dump()
1330 switch (spd->module_type) { in ddr3_spd_dump()
1332 case 0x03: /* SO-DIMM */ in ddr3_spd_dump()
1333 case 0x04: /* Micro-DIMM */ in ddr3_spd_dump()
1334 case 0x06: /* Mini-UDIMM */ in ddr3_spd_dump()
1335 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, in ddr3_spd_dump()
1337 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, in ddr3_spd_dump()
1339 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, in ddr3_spd_dump()
1341 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, in ddr3_spd_dump()
1343 "Edge Connector to DRAM"); in ddr3_spd_dump()
1346 case 0x05: /* Mini-RDIMM */ in ddr3_spd_dump()
1347 PRINT_NXS(60, spd->mod_section.registered.mod_height, in ddr3_spd_dump()
1349 PRINT_NXS(61, spd->mod_section.registered.mod_thickness, in ddr3_spd_dump()
1351 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, in ddr3_spd_dump()
1353 PRINT_NXS(63, spd->mod_section.registered.modu_attr, in ddr3_spd_dump()
1355 PRINT_NXS(64, spd->mod_section.registered.thermal, in ddr3_spd_dump()
1358 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, in ddr3_spd_dump()
1361 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, in ddr3_spd_dump()
1364 PRINT_NXS(67, spd->mod_section.registered.reg_rev, in ddr3_spd_dump()
1367 PRINT_NXS(68, spd->mod_section.registered.reg_type, in ddr3_spd_dump()
1370 printf("%-3d : %02x rcw[%d]\n", i, in ddr3_spd_dump()
1371 spd->mod_section.registered.rcw[i-69], i-69); in ddr3_spd_dump()
1375 /* Module-specific Section, Unsupported Module Type */ in ddr3_spd_dump()
1376 printf("%-3d-%3d: ", 60, 116); in ddr3_spd_dump()
1379 printf("%02x", spd->mod_section.uc[i - 60]); in ddr3_spd_dump()
1384 /* Unique Module ID: Bytes 117-125 */ in ddr3_spd_dump()
1385 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); in ddr3_spd_dump()
1386 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); in ddr3_spd_dump()
1387 PRINT_NXS(119, spd->mloc, "Mfg Location"); in ddr3_spd_dump()
1388 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); in ddr3_spd_dump()
1390 printf("%-3d-%3d: ", 122, 125); in ddr3_spd_dump()
1393 printf("%02x ", spd->sernum[i - 122]); in ddr3_spd_dump()
1396 /* CRC: Bytes 126-127 */ in ddr3_spd_dump()
1397 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); in ddr3_spd_dump()
1399 /* Other Manufacturer Fields and User Space: Bytes 128-255 */ in ddr3_spd_dump()
1400 printf("%-3d-%3d: ", 128, 145); in ddr3_spd_dump()
1402 printf("%02x ", spd->mpart[i - 128]); in ddr3_spd_dump()
1405 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], in ddr3_spd_dump()
1408 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); in ddr3_spd_dump()
1409 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); in ddr3_spd_dump()
1411 printf("%-3d-%3d: ", 150, 175); in ddr3_spd_dump()
1413 printf("%02x ", spd->msd[i - 150]); in ddr3_spd_dump()
1416 printf("%-3d-%3d: ", 176, 255); in ddr3_spd_dump()
1418 printf("%02x", spd->cust[i - 176]); in ddr3_spd_dump()
1429 /* General Section: Bytes 0-127 */ in ddr4_spd_dump()
1431 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); in ddr4_spd_dump()
1433 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); in ddr4_spd_dump()
1435 PRINT_NXS(0, spd->info_size_crc, in ddr4_spd_dump()
1437 PRINT_NXS(1, spd->spd_rev, in ddr4_spd_dump()
1439 PRINT_NXS(2, spd->mem_type, in ddr4_spd_dump()
1441 PRINT_NXS(3, spd->module_type, in ddr4_spd_dump()
1443 PRINT_NXS(4, spd->density_banks, in ddr4_spd_dump()
1445 PRINT_NXS(5, spd->addressing, in ddr4_spd_dump()
1447 PRINT_NXS(6, spd->package_type, in ddr4_spd_dump()
1449 PRINT_NXS(7, spd->opt_feature, in ddr4_spd_dump()
1451 PRINT_NXS(8, spd->thermal_ref, in ddr4_spd_dump()
1453 PRINT_NXS(9, spd->oth_opt_features, in ddr4_spd_dump()
1455 PRINT_NXS(10, spd->res_10, in ddr4_spd_dump()
1457 PRINT_NXS(11, spd->module_vdd, in ddr4_spd_dump()
1459 PRINT_NXS(12, spd->organization, in ddr4_spd_dump()
1461 PRINT_NXS(13, spd->bus_width, in ddr4_spd_dump()
1463 PRINT_NXS(14, spd->therm_sensor, in ddr4_spd_dump()
1465 PRINT_NXS(15, spd->ext_type, in ddr4_spd_dump()
1467 PRINT_NXS(16, spd->res_16, in ddr4_spd_dump()
1469 PRINT_NXS(17, spd->timebases, in ddr4_spd_dump()
1471 PRINT_NXS(18, spd->tck_min, in ddr4_spd_dump()
1473 PRINT_NXS(19, spd->tck_max, in ddr4_spd_dump()
1475 PRINT_NXS(20, spd->caslat_b1, in ddr4_spd_dump()
1476 "caslat_b1 CAS latencies, 1st byte"); in ddr4_spd_dump()
1477 PRINT_NXS(21, spd->caslat_b2, in ddr4_spd_dump()
1478 "caslat_b2 CAS latencies, 2nd byte"); in ddr4_spd_dump()
1479 PRINT_NXS(22, spd->caslat_b3, in ddr4_spd_dump()
1480 "caslat_b3 CAS latencies, 3rd byte "); in ddr4_spd_dump()
1481 PRINT_NXS(23, spd->caslat_b4, in ddr4_spd_dump()
1482 "caslat_b4 CAS latencies, 4th byte"); in ddr4_spd_dump()
1483 PRINT_NXS(24, spd->taa_min, in ddr4_spd_dump()
1484 "taa_min Min CAS Latency Time"); in ddr4_spd_dump()
1485 PRINT_NXS(25, spd->trcd_min, in ddr4_spd_dump()
1486 "trcd_min Min RAS# to CAS# Delay Time"); in ddr4_spd_dump()
1487 PRINT_NXS(26, spd->trp_min, in ddr4_spd_dump()
1489 PRINT_NXS(27, spd->tras_trc_ext, in ddr4_spd_dump()
1491 PRINT_NXS(28, spd->tras_min_lsb, in ddr4_spd_dump()
1493 PRINT_NXS(29, spd->trc_min_lsb, in ddr4_spd_dump()
1495 PRINT_NXS(30, spd->trfc1_min_lsb, in ddr4_spd_dump()
1497 PRINT_NXS(31, spd->trfc1_min_msb, in ddr4_spd_dump()
1499 PRINT_NXS(32, spd->trfc2_min_lsb, in ddr4_spd_dump()
1501 PRINT_NXS(33, spd->trfc2_min_msb, in ddr4_spd_dump()
1503 PRINT_NXS(34, spd->trfc4_min_lsb, in ddr4_spd_dump()
1505 PRINT_NXS(35, spd->trfc4_min_msb, in ddr4_spd_dump()
1507 PRINT_NXS(36, spd->tfaw_msb, in ddr4_spd_dump()
1509 PRINT_NXS(37, spd->tfaw_min, in ddr4_spd_dump()
1511 PRINT_NXS(38, spd->trrds_min, in ddr4_spd_dump()
1513 PRINT_NXS(39, spd->trrdl_min, in ddr4_spd_dump()
1515 PRINT_NXS(40, spd->tccdl_min, in ddr4_spd_dump()
1518 printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */ in ddr4_spd_dump()
1520 printf("%02x ", spd->res_41[i - 41]); in ddr4_spd_dump()
1523 printf("%-3d-%3d: ", 60, 77); in ddr4_spd_dump()
1525 printf("%02x ", spd->mapping[i - 60]); in ddr4_spd_dump()
1526 puts(" mapping[] Connector to SDRAM bit map\n"); in ddr4_spd_dump()
1528 PRINT_NXS(117, spd->fine_tccdl_min, in ddr4_spd_dump()
1530 PRINT_NXS(118, spd->fine_trrdl_min, in ddr4_spd_dump()
1532 PRINT_NXS(119, spd->fine_trrds_min, in ddr4_spd_dump()
1534 PRINT_NXS(120, spd->fine_trc_min, in ddr4_spd_dump()
1536 PRINT_NXS(121, spd->fine_trp_min, in ddr4_spd_dump()
1538 PRINT_NXS(122, spd->fine_trcd_min, in ddr4_spd_dump()
1540 PRINT_NXS(123, spd->fine_taa_min, in ddr4_spd_dump()
1542 PRINT_NXS(124, spd->fine_tck_max, in ddr4_spd_dump()
1544 PRINT_NXS(125, spd->fine_tck_min, in ddr4_spd_dump()
1547 /* CRC: Bytes 126-127 */ in ddr4_spd_dump()
1548 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); in ddr4_spd_dump()
1550 switch (spd->module_type) { in ddr4_spd_dump()
1552 case 0x03: /* SO-DIMM */ in ddr4_spd_dump()
1553 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height, in ddr4_spd_dump()
1555 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness, in ddr4_spd_dump()
1557 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card, in ddr4_spd_dump()
1559 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping, in ddr4_spd_dump()
1560 "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM"); in ddr4_spd_dump()
1561 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0], in ddr4_spd_dump()
1562 spd->mod_section.unbuffered.crc[1], " Module CRC"); in ddr4_spd_dump()
1565 PRINT_NXS(128, spd->mod_section.registered.mod_height, in ddr4_spd_dump()
1567 PRINT_NXS(129, spd->mod_section.registered.mod_thickness, in ddr4_spd_dump()
1569 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card, in ddr4_spd_dump()
1571 PRINT_NXS(131, spd->mod_section.registered.modu_attr, in ddr4_spd_dump()
1573 PRINT_NXS(132, spd->mod_section.registered.thermal, in ddr4_spd_dump()
1575 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo, in ddr4_spd_dump()
1577 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi, in ddr4_spd_dump()
1579 PRINT_NXS(135, spd->mod_section.registered.reg_rev, in ddr4_spd_dump()
1581 PRINT_NXS(136, spd->mod_section.registered.reg_map, in ddr4_spd_dump()
1583 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0], in ddr4_spd_dump()
1584 spd->mod_section.registered.crc[1], " Module CRC"); in ddr4_spd_dump()
1587 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height, in ddr4_spd_dump()
1589 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness, in ddr4_spd_dump()
1591 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card, in ddr4_spd_dump()
1593 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr, in ddr4_spd_dump()
1595 PRINT_NXS(132, spd->mod_section.loadreduced.thermal, in ddr4_spd_dump()
1597 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo, in ddr4_spd_dump()
1599 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi, in ddr4_spd_dump()
1601 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev, in ddr4_spd_dump()
1603 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map, in ddr4_spd_dump()
1605 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv, in ddr4_spd_dump()
1607 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck, in ddr4_spd_dump()
1609 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev, in ddr4_spd_dump()
1611 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0, in ddr4_spd_dump()
1613 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1, in ddr4_spd_dump()
1615 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2, in ddr4_spd_dump()
1617 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3, in ddr4_spd_dump()
1619 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf, in ddr4_spd_dump()
1621 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866, in ddr4_spd_dump()
1623 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400, in ddr4_spd_dump()
1625 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200, in ddr4_spd_dump()
1627 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv, in ddr4_spd_dump()
1629 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866, in ddr4_spd_dump()
1631 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400, in ddr4_spd_dump()
1633 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200, in ddr4_spd_dump()
1635 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866, in ddr4_spd_dump()
1637 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400, in ddr4_spd_dump()
1639 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200, in ddr4_spd_dump()
1641 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0], in ddr4_spd_dump()
1642 spd->mod_section.loadreduced.crc[1], in ddr4_spd_dump()
1646 /* Module-specific Section, Unsupported Module Type */ in ddr4_spd_dump()
1647 printf("%-3d-%3d: ", 128, 255); in ddr4_spd_dump()
1650 printf("%02x", spd->mod_section.uc[i - 128]); in ddr4_spd_dump()
1655 /* Unique Module ID: Bytes 320-383 */ in ddr4_spd_dump()
1656 PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); in ddr4_spd_dump()
1657 PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); in ddr4_spd_dump()
1658 PRINT_NXS(322, spd->mloc, "Mfg Location"); in ddr4_spd_dump()
1659 PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date"); in ddr4_spd_dump()
1661 printf("%-3d-%3d: ", 325, 328); in ddr4_spd_dump()
1664 printf("%02x ", spd->sernum[i - 325]); in ddr4_spd_dump()
1667 printf("%-3d-%3d: ", 329, 348); in ddr4_spd_dump()
1669 printf("%02x ", spd->mpart[i - 329]); in ddr4_spd_dump()
1672 PRINT_NXS(349, spd->mrev, "Module Revision code"); in ddr4_spd_dump()
1673 PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); in ddr4_spd_dump()
1674 PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); in ddr4_spd_dump()
1675 PRINT_NXS(352, spd->stepping, "DRAM stepping"); in ddr4_spd_dump()
1677 printf("%-3d-%3d: ", 353, 381); in ddr4_spd_dump()
1679 printf("%02x ", spd->msd[i - 353]); in ddr4_spd_dump()
1717 &(pinfo->spd_installed_dimms[i][j])); in fsl_ddr_printinfo()
1736 &(pinfo->dimm_params[i][j])); in fsl_ddr_printinfo()
1752 &pinfo->common_timing_params[i]); in fsl_ddr_printinfo()
1764 print_memctl_options(&pinfo->memctl_opts[i]); in fsl_ddr_printinfo()
1792 &pinfo->fsl_ddr_config_reg[i]); in fsl_ddr_printinfo()
1794 &pinfo->fsl_ddr_config_reg[i]); in fsl_ddr_printinfo()
1854 *pctlr_mask |= 1 << (c - '0'); in fsl_ddr_parse_interactive_cmd()
1861 *pdimm_mask |= 1 << (c - '0'); in fsl_ddr_parse_interactive_cmd()
1898 "recompute reload SPD and options to default and recompute regs\n" in fsl_ddr_interactive()
1900 "compute recompute registers from current next_step to end\n" in fsl_ddr_interactive()
1904 "go program the memory controller and continue with u-boot\n" in fsl_ddr_interactive()
1916 * The strategy for next_step is that it points to the next in fsl_ddr_interactive()
1917 * step in the computation process that needs to be done. in fsl_ddr_interactive()
1923 /* found command separator, copy sub-command */ in fsl_ddr_interactive()
1935 * No need to worry for buffer overflow here in in fsl_ddr_interactive()
1966 unsigned int dst_ctlr_num = -1; in fsl_ddr_interactive()
1967 unsigned int dst_dimm_num = -1; in fsl_ddr_interactive()
1998 src_ctlr_num = (c - '0'); in fsl_ddr_interactive()
2008 src_dimm_num = (c - '0'); in fsl_ddr_interactive()
2016 for (i = argc - 1; i >= argc - num_dest_parms; i--) { in fsl_ddr_interactive()
2020 dst_ctlr_num = (c - '0'); in fsl_ddr_interactive()
2026 for (i = argc - 1; i >= argc - num_dest_parms; i--) { in fsl_ddr_interactive()
2030 dst_dimm_num = (c - '0'); in fsl_ddr_interactive()
2045 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), in fsl_ddr_interactive()
2046 &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), in fsl_ddr_interactive()
2047 sizeof(pinfo->spd_installed_dimms[0][0])); in fsl_ddr_interactive()
2051 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), in fsl_ddr_interactive()
2052 &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), in fsl_ddr_interactive()
2053 sizeof(pinfo->dimm_params[0][0])); in fsl_ddr_interactive()
2057 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), in fsl_ddr_interactive()
2058 &(pinfo->common_timing_params[src_ctlr_num]), in fsl_ddr_interactive()
2059 sizeof(pinfo->common_timing_params[0])); in fsl_ddr_interactive()
2063 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), in fsl_ddr_interactive()
2064 &(pinfo->memctl_opts[src_ctlr_num]), in fsl_ddr_interactive()
2065 sizeof(pinfo->memctl_opts[0])); in fsl_ddr_interactive()
2068 /* someday be able to have addresses to copy addresses... */ in fsl_ddr_interactive()
2071 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), in fsl_ddr_interactive()
2072 &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), in fsl_ddr_interactive()
2073 sizeof(pinfo->memctl_opts[0])); in fsl_ddr_interactive()
2106 argv, argc - 2, in fsl_ddr_interactive()
2127 if (step_mask & (step_mask - 1)) { in fsl_ddr_interactive()
2141 if (ctlr_mask & (ctlr_mask - 1)) { in fsl_ddr_interactive()
2155 if (dimm_mask & (dimm_mask - 1)) { in fsl_ddr_interactive()
2160 p_element = argv[argc - 2]; in fsl_ddr_interactive()
2161 p_value = argv[argc - 1]; in fsl_ddr_interactive()
2231 * Args don't seem to matter because this in fsl_ddr_interactive()