asm/arch-quark/mrc.h

1 /* SPDX-License-Identifier: Intel */
50  * cl: DRAM CAS Latency in clocks
51  * ras: ACT to PRE command period
52  * wtr: Delay from start of internal write transaction to internal read command
53  * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
54  * faw: Four activate window (JESD79 specific to page size 1K/2K)
56  * ras/wtr/rrd/faw timings are in picoseconds
58  * Refer to JEDEC spec (or DRAM datasheet) when changing these values.
63 	uint32_t ras;  member
83 	/* need to save for the case of frequency change */
104  * - input parameters like boot mode and DRAM parameters
105  * - context parameters for MRC internal state
106  * - output parameters like initialization result and memory size
115 	uint8_t ecc_enables;		/* 0, 1 (memory size reduced to 7/8) */
117 	/* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
160  * post_code: a 16-bit post code of a specific initialization routine
174 /* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
176 /* If set ODR signal is asserted to DRAM devices on writes */
180  * mrc_init - Memory Reference Code initialization entry routine