1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 20f2cbe3fSJames Yang /* 334e026f9SYork Sun * Copyright 2008-2014 Freescale Semiconductor, Inc. 40f2cbe3fSJames Yang */ 50f2cbe3fSJames Yang 60f2cbe3fSJames Yang #ifndef _DDR_SPD_H_ 70f2cbe3fSJames Yang #define _DDR_SPD_H_ 80f2cbe3fSJames Yang 90f2cbe3fSJames Yang /* 100f2cbe3fSJames Yang * Format from "JEDEC Standard No. 21-C, 110f2cbe3fSJames Yang * Appendix D: Rev 1.0: SPD's for DDR SDRAM 120f2cbe3fSJames Yang */ 130f2cbe3fSJames Yang typedef struct ddr1_spd_eeprom_s { 140f2cbe3fSJames Yang unsigned char info_size; /* 0 # bytes written into serial memory */ 150f2cbe3fSJames Yang unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 160f2cbe3fSJames Yang unsigned char mem_type; /* 2 Fundamental memory type */ 170f2cbe3fSJames Yang unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 180f2cbe3fSJames Yang unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 190f2cbe3fSJames Yang unsigned char nrows; /* 5 Number of DIMM Banks */ 200f2cbe3fSJames Yang unsigned char dataw_lsb; /* 6 Data Width of this assembly */ 210f2cbe3fSJames Yang unsigned char dataw_msb; /* 7 ... Data Width continuation */ 220f2cbe3fSJames Yang unsigned char voltage; /* 8 Voltage intf std of this assembly */ 230f2cbe3fSJames Yang unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 240f2cbe3fSJames Yang unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 250f2cbe3fSJames Yang unsigned char config; /* 11 DIMM Configuration type */ 260f2cbe3fSJames Yang unsigned char refresh; /* 12 Refresh Rate/Type */ 270f2cbe3fSJames Yang unsigned char primw; /* 13 Primary SDRAM Width */ 280f2cbe3fSJames Yang unsigned char ecw; /* 14 Error Checking SDRAM width */ 290f2cbe3fSJames Yang unsigned char min_delay; /* 15 for Back to Back Random Address */ 300f2cbe3fSJames Yang unsigned char burstl; /* 16 Burst Lengths Supported */ 310f2cbe3fSJames Yang unsigned char nbanks; /* 17 # of Banks on SDRAM Device */ 320f2cbe3fSJames Yang unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 330f2cbe3fSJames Yang unsigned char cs_lat; /* 19 CS# Latency */ 340f2cbe3fSJames Yang unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ 350f2cbe3fSJames Yang unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 360f2cbe3fSJames Yang unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 370f2cbe3fSJames Yang unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ 380f2cbe3fSJames Yang unsigned char clk_access2; /* 24 SDRAM Access from 390f2cbe3fSJames Yang Clk @ CL=X-0.5 (tAC) */ 400f2cbe3fSJames Yang unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ 410f2cbe3fSJames Yang unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ 420f2cbe3fSJames Yang unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 430f2cbe3fSJames Yang unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 440f2cbe3fSJames Yang unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 450f2cbe3fSJames Yang unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 460f2cbe3fSJames Yang unsigned char bank_dens; /* 31 Density of each bank on module */ 470f2cbe3fSJames Yang unsigned char ca_setup; /* 32 Addr + Cmd Setup Time Before Clk */ 480f2cbe3fSJames Yang unsigned char ca_hold; /* 33 Addr + Cmd Hold Time After Clk */ 490f2cbe3fSJames Yang unsigned char data_setup; /* 34 Data Input Setup Time Before Strobe */ 500f2cbe3fSJames Yang unsigned char data_hold; /* 35 Data Input Hold Time After Strobe */ 510f2cbe3fSJames Yang unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */ 520f2cbe3fSJames Yang unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 530f2cbe3fSJames Yang unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 540f2cbe3fSJames Yang unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 550f2cbe3fSJames Yang unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ 560f2cbe3fSJames Yang unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ 570f2cbe3fSJames Yang unsigned char res_46; /* 46 Reserved */ 580f2cbe3fSJames Yang unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */ 590f2cbe3fSJames Yang unsigned char res_48_61[14]; /* 48-61 Reserved */ 600f2cbe3fSJames Yang unsigned char spd_rev; /* 62 SPD Data Revision Code */ 610f2cbe3fSJames Yang unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 620f2cbe3fSJames Yang unsigned char mid[8]; /* 64-71 Mfr's JEDEC ID code per JEP-106 */ 630f2cbe3fSJames Yang unsigned char mloc; /* 72 Manufacturing Location */ 640f2cbe3fSJames Yang unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 650f2cbe3fSJames Yang unsigned char rev[2]; /* 91 Revision Code */ 660f2cbe3fSJames Yang unsigned char mdate[2]; /* 93 Manufacturing Date */ 670f2cbe3fSJames Yang unsigned char sernum[4]; /* 95 Assembly Serial Number */ 680f2cbe3fSJames Yang unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ 690f2cbe3fSJames Yang 700f2cbe3fSJames Yang } ddr1_spd_eeprom_t; 710f2cbe3fSJames Yang 720f2cbe3fSJames Yang /* 730f2cbe3fSJames Yang * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM", 740f2cbe3fSJames Yang * SPD Revision 1.2 750f2cbe3fSJames Yang */ 760f2cbe3fSJames Yang typedef struct ddr2_spd_eeprom_s { 770f2cbe3fSJames Yang unsigned char info_size; /* 0 # bytes written into serial memory */ 780f2cbe3fSJames Yang unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ 790f2cbe3fSJames Yang unsigned char mem_type; /* 2 Fundamental memory type */ 800f2cbe3fSJames Yang unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ 810f2cbe3fSJames Yang unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ 820f2cbe3fSJames Yang unsigned char mod_ranks; /* 5 Number of DIMM Ranks */ 830f2cbe3fSJames Yang unsigned char dataw; /* 6 Module Data Width */ 840f2cbe3fSJames Yang unsigned char res_7; /* 7 Reserved */ 850f2cbe3fSJames Yang unsigned char voltage; /* 8 Voltage intf std of this assembly */ 860f2cbe3fSJames Yang unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 870f2cbe3fSJames Yang unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 880f2cbe3fSJames Yang unsigned char config; /* 11 DIMM Configuration type */ 890f2cbe3fSJames Yang unsigned char refresh; /* 12 Refresh Rate/Type */ 900f2cbe3fSJames Yang unsigned char primw; /* 13 Primary SDRAM Width */ 910f2cbe3fSJames Yang unsigned char ecw; /* 14 Error Checking SDRAM width */ 920f2cbe3fSJames Yang unsigned char res_15; /* 15 Reserved */ 930f2cbe3fSJames Yang unsigned char burstl; /* 16 Burst Lengths Supported */ 940f2cbe3fSJames Yang unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ 950f2cbe3fSJames Yang unsigned char cas_lat; /* 18 CAS# Latencies Supported */ 960f2cbe3fSJames Yang unsigned char mech_char; /* 19 DIMM Mechanical Characteristics */ 970f2cbe3fSJames Yang unsigned char dimm_type; /* 20 DIMM type information */ 980f2cbe3fSJames Yang unsigned char mod_attr; /* 21 SDRAM Module Attributes */ 990f2cbe3fSJames Yang unsigned char dev_attr; /* 22 SDRAM Device Attributes */ 1000f2cbe3fSJames Yang unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */ 1010f2cbe3fSJames Yang unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */ 1020f2cbe3fSJames Yang unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */ 1030f2cbe3fSJames Yang unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */ 1040f2cbe3fSJames Yang unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ 1050f2cbe3fSJames Yang unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ 1060f2cbe3fSJames Yang unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ 1070f2cbe3fSJames Yang unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ 1080f2cbe3fSJames Yang unsigned char rank_dens; /* 31 Density of each rank on module */ 1090f2cbe3fSJames Yang unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */ 1100f2cbe3fSJames Yang unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */ 1110f2cbe3fSJames Yang unsigned char data_setup; /* 34 Data Input Setup Time 1120f2cbe3fSJames Yang Before Strobe (tDS) */ 1130f2cbe3fSJames Yang unsigned char data_hold; /* 35 Data Input Hold Time 1140f2cbe3fSJames Yang After Strobe (tDH) */ 1150f2cbe3fSJames Yang unsigned char twr; /* 36 Write Recovery time tWR */ 1160f2cbe3fSJames Yang unsigned char twtr; /* 37 Int write to read delay tWTR */ 1170f2cbe3fSJames Yang unsigned char trtp; /* 38 Int read to precharge delay tRTP */ 1180f2cbe3fSJames Yang unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ 1190f2cbe3fSJames Yang unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ 1200f2cbe3fSJames Yang unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ 1210f2cbe3fSJames Yang unsigned char trfc; /* 42 Min Auto to Active period tRFC */ 1220f2cbe3fSJames Yang unsigned char tckmax; /* 43 Max device cycle time tCKmax */ 1230f2cbe3fSJames Yang unsigned char tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */ 1240f2cbe3fSJames Yang unsigned char tqhs; /* 45 Max Read DataHold skew (tQHS) */ 1250f2cbe3fSJames Yang unsigned char pll_relock; /* 46 PLL Relock time */ 1260dd38a35SPriyanka Jain unsigned char t_casemax; /* 47 Tcasemax */ 1270dd38a35SPriyanka Jain unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from 1280f2cbe3fSJames Yang Top (Case) to Ambient (Psi T-A DRAM) */ 1290f2cbe3fSJames Yang unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient 1300f2cbe3fSJames Yang due to Activate-Precharge/Mode Bits 1310f2cbe3fSJames Yang (DT0/Mode Bits) */ 1320f2cbe3fSJames Yang unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient 1330f2cbe3fSJames Yang due to Precharge/Quiet Standby 1340f2cbe3fSJames Yang (DT2N/DT2Q) */ 1350f2cbe3fSJames Yang unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient 1360f2cbe3fSJames Yang due to Precharge Power-Down (DT2P) */ 1370f2cbe3fSJames Yang unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient 1380f2cbe3fSJames Yang due to Active Standby (DT3N) */ 1390f2cbe3fSJames Yang unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient 1400f2cbe3fSJames Yang due to Active Power-Down with 1410f2cbe3fSJames Yang Fast PDN Exit (DT3Pfast) */ 1420f2cbe3fSJames Yang unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient 1430f2cbe3fSJames Yang due to Active Power-Down with Slow 1440f2cbe3fSJames Yang PDN Exit (DT3Pslow) */ 1450f2cbe3fSJames Yang unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient 1460f2cbe3fSJames Yang due to Page Open Burst Read/DT4R4W 1470f2cbe3fSJames Yang Mode Bit (DT4R/DT4R4W Mode Bit) */ 1480f2cbe3fSJames Yang unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient 1490f2cbe3fSJames Yang due to Burst Refresh (DT5B) */ 1500f2cbe3fSJames Yang unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient 1510f2cbe3fSJames Yang due to Bank Interleave Reads with 1520f2cbe3fSJames Yang Auto-Precharge (DT7) */ 1530dd38a35SPriyanka Jain unsigned char psi_ta_pll; /* 58 Thermal Resistance of PLL Package form 1540f2cbe3fSJames Yang Top (Case) to Ambient (Psi T-A PLL) */ 1550dd38a35SPriyanka Jain unsigned char psi_ta_reg; /* 59 Thermal Reisitance of Register Package 1560f2cbe3fSJames Yang from Top (Case) to Ambient 1570f2cbe3fSJames Yang (Psi T-A Register) */ 1580f2cbe3fSJames Yang unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient 1590f2cbe3fSJames Yang due to PLL Active (DT PLL Active) */ 1600f2cbe3fSJames Yang unsigned char dtregact; /* 61 Register Case Temperature Rise from 1610f2cbe3fSJames Yang Ambient due to Register Active/Mode Bit 1620f2cbe3fSJames Yang (DT Register Active/Mode Bit) */ 1630f2cbe3fSJames Yang unsigned char spd_rev; /* 62 SPD Data Revision Code */ 1640f2cbe3fSJames Yang unsigned char cksum; /* 63 Checksum for bytes 0-62 */ 1650f2cbe3fSJames Yang unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */ 1660f2cbe3fSJames Yang unsigned char mloc; /* 72 Manufacturing Location */ 1670f2cbe3fSJames Yang unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ 1680f2cbe3fSJames Yang unsigned char rev[2]; /* 91 Revision Code */ 1690f2cbe3fSJames Yang unsigned char mdate[2]; /* 93 Manufacturing Date */ 1700f2cbe3fSJames Yang unsigned char sernum[4]; /* 95 Assembly Serial Number */ 1710f2cbe3fSJames Yang unsigned char mspec[27]; /* 99-127 Manufacturer Specific Data */ 1720f2cbe3fSJames Yang 1730f2cbe3fSJames Yang } ddr2_spd_eeprom_t; 1740f2cbe3fSJames Yang 1750f2cbe3fSJames Yang typedef struct ddr3_spd_eeprom_s { 1760f2cbe3fSJames Yang /* General Section: Bytes 0-59 */ 1770f2cbe3fSJames Yang unsigned char info_size_crc; /* 0 # bytes written into serial memory, 1780f2cbe3fSJames Yang CRC coverage */ 1790f2cbe3fSJames Yang unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */ 1800f2cbe3fSJames Yang unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */ 1810f2cbe3fSJames Yang unsigned char module_type; /* 3 Key Byte / Module Type */ 1820f2cbe3fSJames Yang unsigned char density_banks; /* 4 SDRAM Density and Banks */ 1830f2cbe3fSJames Yang unsigned char addressing; /* 5 SDRAM Addressing */ 184c360ceacSDave Liu unsigned char module_vdd; /* 6 Module nominal voltage, VDD */ 1850f2cbe3fSJames Yang unsigned char organization; /* 7 Module Organization */ 1860f2cbe3fSJames Yang unsigned char bus_width; /* 8 Module Memory Bus Width */ 1870f2cbe3fSJames Yang unsigned char ftb_div; /* 9 Fine Timebase (FTB) 1880f2cbe3fSJames Yang Dividend / Divisor */ 1890f2cbe3fSJames Yang unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */ 1900f2cbe3fSJames Yang unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */ 1910dd38a35SPriyanka Jain unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */ 1920f2cbe3fSJames Yang unsigned char res_13; /* 13 Reserved */ 1930f2cbe3fSJames Yang unsigned char caslat_lsb; /* 14 CAS Latencies Supported, 1940f2cbe3fSJames Yang Least Significant Byte */ 1950f2cbe3fSJames Yang unsigned char caslat_msb; /* 15 CAS Latencies Supported, 1960f2cbe3fSJames Yang Most Significant Byte */ 1970dd38a35SPriyanka Jain unsigned char taa_min; /* 16 Min CAS Latency Time */ 1980dd38a35SPriyanka Jain unsigned char twr_min; /* 17 Min Write REcovery Time */ 1990dd38a35SPriyanka Jain unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */ 2000dd38a35SPriyanka Jain unsigned char trrd_min; /* 19 Min Row Active to 2010f2cbe3fSJames Yang Row Active Delay Time */ 2020dd38a35SPriyanka Jain unsigned char trp_min; /* 20 Min Row Precharge Delay Time */ 2030dd38a35SPriyanka Jain unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */ 2040dd38a35SPriyanka Jain unsigned char tras_min_lsb; /* 22 Min Active to Precharge 2050f2cbe3fSJames Yang Delay Time */ 2060dd38a35SPriyanka Jain unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh 2070f2cbe3fSJames Yang Delay Time, LSB */ 2080dd38a35SPriyanka Jain unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */ 2090dd38a35SPriyanka Jain unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */ 2100dd38a35SPriyanka Jain unsigned char twtr_min; /* 26 Min Internal Write to 2110f2cbe3fSJames Yang Read Command Delay Time */ 2120dd38a35SPriyanka Jain unsigned char trtp_min; /* 27 Min Internal Read to Precharge 2130f2cbe3fSJames Yang Command Delay Time */ 2140dd38a35SPriyanka Jain unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */ 2150dd38a35SPriyanka Jain unsigned char tfaw_min; /* 29 Min Four Activate Window 2160f2cbe3fSJames Yang Delay Time*/ 2170f2cbe3fSJames Yang unsigned char opt_features; /* 30 SDRAM Optional Features */ 2180f2cbe3fSJames Yang unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */ 219c49290cdSYork Sun unsigned char therm_sensor; /* 32 Module Thermal Sensor */ 220c49290cdSYork Sun unsigned char device_type; /* 33 SDRAM device type */ 2210dd38a35SPriyanka Jain int8_t fine_tck_min; /* 34 Fine offset for tCKmin */ 2220dd38a35SPriyanka Jain int8_t fine_taa_min; /* 35 Fine offset for tAAmin */ 2230dd38a35SPriyanka Jain int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */ 2240dd38a35SPriyanka Jain int8_t fine_trp_min; /* 37 Fine offset for tRPmin */ 2250dd38a35SPriyanka Jain int8_t fine_trc_min; /* 38 Fine offset for tRCmin */ 22673b5396bSYork Sun unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */ 2270f2cbe3fSJames Yang 2280f2cbe3fSJames Yang /* Module-Specific Section: Bytes 60-116 */ 2290f2cbe3fSJames Yang union { 2300f2cbe3fSJames Yang struct { 2310f2cbe3fSJames Yang /* 60 (Unbuffered) Module Nominal Height */ 2320f2cbe3fSJames Yang unsigned char mod_height; 2330f2cbe3fSJames Yang /* 61 (Unbuffered) Module Maximum Thickness */ 2340f2cbe3fSJames Yang unsigned char mod_thickness; 2350f2cbe3fSJames Yang /* 62 (Unbuffered) Reference Raw Card Used */ 2360f2cbe3fSJames Yang unsigned char ref_raw_card; 2370f2cbe3fSJames Yang /* 63 (Unbuffered) Address Mapping from 2380f2cbe3fSJames Yang Edge Connector to DRAM */ 2390f2cbe3fSJames Yang unsigned char addr_mapping; 2400f2cbe3fSJames Yang /* 64-116 (Unbuffered) Reserved */ 2410f2cbe3fSJames Yang unsigned char res_64_116[53]; 2420f2cbe3fSJames Yang } unbuffered; 2430f2cbe3fSJames Yang struct { 2440f2cbe3fSJames Yang /* 60 (Registered) Module Nominal Height */ 2450f2cbe3fSJames Yang unsigned char mod_height; 2460f2cbe3fSJames Yang /* 61 (Registered) Module Maximum Thickness */ 2470f2cbe3fSJames Yang unsigned char mod_thickness; 2480f2cbe3fSJames Yang /* 62 (Registered) Reference Raw Card Used */ 2490f2cbe3fSJames Yang unsigned char ref_raw_card; 2509490ff48Syork /* 63 DIMM Module Attributes */ 2519490ff48Syork unsigned char modu_attr; 2529490ff48Syork /* 64 RDIMM Thermal Heat Spreader Solution */ 2539490ff48Syork unsigned char thermal; 2549490ff48Syork /* 65 Register Manufacturer ID Code, Least Significant Byte */ 2559490ff48Syork unsigned char reg_id_lo; 2569490ff48Syork /* 66 Register Manufacturer ID Code, Most Significant Byte */ 2579490ff48Syork unsigned char reg_id_hi; 2589490ff48Syork /* 67 Register Revision Number */ 2599490ff48Syork unsigned char reg_rev; 2609490ff48Syork /* 68 Register Type */ 2619490ff48Syork unsigned char reg_type; 2629490ff48Syork /* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */ 2639490ff48Syork unsigned char rcw[8]; 2640f2cbe3fSJames Yang } registered; 2650f2cbe3fSJames Yang unsigned char uc[57]; /* 60-116 Module-Specific Section */ 2660f2cbe3fSJames Yang } mod_section; 2670f2cbe3fSJames Yang 2680f2cbe3fSJames Yang /* Unique Module ID: Bytes 117-125 */ 2690f2cbe3fSJames Yang unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */ 2700f2cbe3fSJames Yang unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */ 2710f2cbe3fSJames Yang unsigned char mloc; /* 119 Mfg Location */ 2720f2cbe3fSJames Yang unsigned char mdate[2]; /* 120-121 Mfg Date */ 2730f2cbe3fSJames Yang unsigned char sernum[4]; /* 122-125 Module Serial Number */ 2740f2cbe3fSJames Yang 2750f2cbe3fSJames Yang /* CRC: Bytes 126-127 */ 2760f2cbe3fSJames Yang unsigned char crc[2]; /* 126-127 SPD CRC */ 2770f2cbe3fSJames Yang 2780f2cbe3fSJames Yang /* Other Manufacturer Fields and User Space: Bytes 128-255 */ 2790f2cbe3fSJames Yang unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */ 2800f2cbe3fSJames Yang unsigned char mrev[2]; /* 146-147 Module Revision Code */ 2810f2cbe3fSJames Yang 2820f2cbe3fSJames Yang unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */ 2830f2cbe3fSJames Yang unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */ 2840f2cbe3fSJames Yang 2850f2cbe3fSJames Yang unsigned char msd[26]; /* 150-175 Mfg's Specific Data */ 2860f2cbe3fSJames Yang unsigned char cust[80]; /* 176-255 Open for Customer Use */ 2870f2cbe3fSJames Yang 2880f2cbe3fSJames Yang } ddr3_spd_eeprom_t; 2890f2cbe3fSJames Yang 29034e026f9SYork Sun /* From JEEC Standard No. 21-C release 23A */ 29134e026f9SYork Sun struct ddr4_spd_eeprom_s { 29234e026f9SYork Sun /* General Section: Bytes 0-127 */ 29334e026f9SYork Sun uint8_t info_size_crc; /* 0 # bytes */ 29434e026f9SYork Sun uint8_t spd_rev; /* 1 Total # bytes of SPD */ 29534e026f9SYork Sun uint8_t mem_type; /* 2 Key Byte / mem type */ 29634e026f9SYork Sun uint8_t module_type; /* 3 Key Byte / Module Type */ 29734e026f9SYork Sun uint8_t density_banks; /* 4 Density and Banks */ 29834e026f9SYork Sun uint8_t addressing; /* 5 Addressing */ 29934e026f9SYork Sun uint8_t package_type; /* 6 Package type */ 30034e026f9SYork Sun uint8_t opt_feature; /* 7 Optional features */ 30134e026f9SYork Sun uint8_t thermal_ref; /* 8 Thermal and refresh */ 30234e026f9SYork Sun uint8_t oth_opt_features; /* 9 Other optional features */ 30334e026f9SYork Sun uint8_t res_10; /* 10 Reserved */ 30434e026f9SYork Sun uint8_t module_vdd; /* 11 Module nominal voltage */ 30534e026f9SYork Sun uint8_t organization; /* 12 Module Organization */ 30634e026f9SYork Sun uint8_t bus_width; /* 13 Module Memory Bus Width */ 30734e026f9SYork Sun uint8_t therm_sensor; /* 14 Module Thermal Sensor */ 30834e026f9SYork Sun uint8_t ext_type; /* 15 Extended module type */ 30934e026f9SYork Sun uint8_t res_16; 31034e026f9SYork Sun uint8_t timebases; /* 17 MTb and FTB */ 31134e026f9SYork Sun uint8_t tck_min; /* 18 tCKAVGmin */ 31234e026f9SYork Sun uint8_t tck_max; /* 19 TCKAVGmax */ 31334e026f9SYork Sun uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */ 31434e026f9SYork Sun uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */ 31534e026f9SYork Sun uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */ 31634e026f9SYork Sun uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */ 31734e026f9SYork Sun uint8_t taa_min; /* 24 Min CAS Latency Time */ 31834e026f9SYork Sun uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */ 31934e026f9SYork Sun uint8_t trp_min; /* 26 Min Row Precharge Delay Time */ 32034e026f9SYork Sun uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ 32134e026f9SYork Sun uint8_t tras_min_lsb; /* 28 tRASmin, lsb */ 32234e026f9SYork Sun uint8_t trc_min_lsb; /* 29 tRCmin, lsb */ 32334e026f9SYork Sun uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ 32434e026f9SYork Sun uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ 32534e026f9SYork Sun uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ 32634e026f9SYork Sun uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ 32734e026f9SYork Sun uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ 32834e026f9SYork Sun uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ 32934e026f9SYork Sun uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */ 33034e026f9SYork Sun uint8_t tfaw_min; /* 37 tFAW, lsb */ 33134e026f9SYork Sun uint8_t trrds_min; /* 38 tRRD_Smin, MTB */ 33234e026f9SYork Sun uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */ 33334e026f9SYork Sun uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */ 33434e026f9SYork Sun uint8_t res_41[60-41]; /* 41 Rserved */ 33534e026f9SYork Sun uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ 33634e026f9SYork Sun uint8_t res_78[117-78]; /* 78~116, Reserved */ 33734e026f9SYork Sun int8_t fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ 33834e026f9SYork Sun int8_t fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ 33934e026f9SYork Sun int8_t fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ 34034e026f9SYork Sun int8_t fine_trc_min; /* 120 Fine offset for tRCmin */ 34134e026f9SYork Sun int8_t fine_trp_min; /* 121 Fine offset for tRPmin */ 34234e026f9SYork Sun int8_t fine_trcd_min; /* 122 Fine offset for tRCDmin */ 34334e026f9SYork Sun int8_t fine_taa_min; /* 123 Fine offset for tAAmin */ 34434e026f9SYork Sun int8_t fine_tck_max; /* 124 Fine offset for tCKAVGmax */ 34534e026f9SYork Sun int8_t fine_tck_min; /* 125 Fine offset for tCKAVGmin */ 34634e026f9SYork Sun /* CRC: Bytes 126-127 */ 34734e026f9SYork Sun uint8_t crc[2]; /* 126-127 SPD CRC */ 34834e026f9SYork Sun 34934e026f9SYork Sun /* Module-Specific Section: Bytes 128-255 */ 35034e026f9SYork Sun union { 35134e026f9SYork Sun struct { 35234e026f9SYork Sun /* 128 (Unbuffered) Module Nominal Height */ 35334e026f9SYork Sun uint8_t mod_height; 35434e026f9SYork Sun /* 129 (Unbuffered) Module Maximum Thickness */ 35534e026f9SYork Sun uint8_t mod_thickness; 35634e026f9SYork Sun /* 130 (Unbuffered) Reference Raw Card Used */ 35734e026f9SYork Sun uint8_t ref_raw_card; 35834e026f9SYork Sun /* 131 (Unbuffered) Address Mapping from 35934e026f9SYork Sun Edge Connector to DRAM */ 36034e026f9SYork Sun uint8_t addr_mapping; 36134e026f9SYork Sun /* 132~253 (Unbuffered) Reserved */ 36234e026f9SYork Sun uint8_t res_132[254-132]; 36334e026f9SYork Sun /* 254~255 CRC */ 36434e026f9SYork Sun uint8_t crc[2]; 36534e026f9SYork Sun } unbuffered; 36634e026f9SYork Sun struct { 36734e026f9SYork Sun /* 128 (Registered) Module Nominal Height */ 36834e026f9SYork Sun uint8_t mod_height; 36934e026f9SYork Sun /* 129 (Registered) Module Maximum Thickness */ 37034e026f9SYork Sun uint8_t mod_thickness; 37134e026f9SYork Sun /* 130 (Registered) Reference Raw Card Used */ 37234e026f9SYork Sun uint8_t ref_raw_card; 37334e026f9SYork Sun /* 131 DIMM Module Attributes */ 37434e026f9SYork Sun uint8_t modu_attr; 37534e026f9SYork Sun /* 132 RDIMM Thermal Heat Spreader Solution */ 37634e026f9SYork Sun uint8_t thermal; 37734e026f9SYork Sun /* 133 Register Manufacturer ID Code, LSB */ 37834e026f9SYork Sun uint8_t reg_id_lo; 37934e026f9SYork Sun /* 134 Register Manufacturer ID Code, MSB */ 38034e026f9SYork Sun uint8_t reg_id_hi; 38134e026f9SYork Sun /* 135 Register Revision Number */ 38234e026f9SYork Sun uint8_t reg_rev; 38334e026f9SYork Sun /* 136 Address mapping from register to DRAM */ 384564e9383SYork Sun u8 reg_map; 385564e9383SYork Sun u8 ca_stren; 386564e9383SYork Sun u8 clk_stren; 387564e9383SYork Sun /* 139~253 Reserved */ 388564e9383SYork Sun u8 res_137[254 - 139]; 38934e026f9SYork Sun /* 254~255 CRC */ 39034e026f9SYork Sun uint8_t crc[2]; 39134e026f9SYork Sun } registered; 39234e026f9SYork Sun struct { 39334e026f9SYork Sun /* 128 (Loadreduced) Module Nominal Height */ 39434e026f9SYork Sun uint8_t mod_height; 39534e026f9SYork Sun /* 129 (Loadreduced) Module Maximum Thickness */ 39634e026f9SYork Sun uint8_t mod_thickness; 39734e026f9SYork Sun /* 130 (Loadreduced) Reference Raw Card Used */ 39834e026f9SYork Sun uint8_t ref_raw_card; 39934e026f9SYork Sun /* 131 DIMM Module Attributes */ 40034e026f9SYork Sun uint8_t modu_attr; 40134e026f9SYork Sun /* 132 RDIMM Thermal Heat Spreader Solution */ 40234e026f9SYork Sun uint8_t thermal; 40334e026f9SYork Sun /* 133 Register Manufacturer ID Code, LSB */ 40434e026f9SYork Sun uint8_t reg_id_lo; 40534e026f9SYork Sun /* 134 Register Manufacturer ID Code, MSB */ 40634e026f9SYork Sun uint8_t reg_id_hi; 40734e026f9SYork Sun /* 135 Register Revision Number */ 40834e026f9SYork Sun uint8_t reg_rev; 40934e026f9SYork Sun /* 136 Address mapping from register to DRAM */ 41034e026f9SYork Sun uint8_t reg_map; 41134e026f9SYork Sun /* 137 Register Output Drive Strength for CMD/Add*/ 41234e026f9SYork Sun uint8_t reg_drv; 41334e026f9SYork Sun /* 138 Register Output Drive Strength for CK */ 41434e026f9SYork Sun uint8_t reg_drv_ck; 41534e026f9SYork Sun /* 139 Data Buffer Revision Number */ 41634e026f9SYork Sun uint8_t data_buf_rev; 41734e026f9SYork Sun /* 140 DRAM VrefDQ for Package Rank 0 */ 41834e026f9SYork Sun uint8_t vrefqe_r0; 41934e026f9SYork Sun /* 141 DRAM VrefDQ for Package Rank 1 */ 42034e026f9SYork Sun uint8_t vrefqe_r1; 42134e026f9SYork Sun /* 142 DRAM VrefDQ for Package Rank 2 */ 42234e026f9SYork Sun uint8_t vrefqe_r2; 42334e026f9SYork Sun /* 143 DRAM VrefDQ for Package Rank 3 */ 42434e026f9SYork Sun uint8_t vrefqe_r3; 42534e026f9SYork Sun /* 144 Data Buffer VrefDQ for DRAM Interface */ 42634e026f9SYork Sun uint8_t data_intf; 42734e026f9SYork Sun /* 42834e026f9SYork Sun * 145 Data Buffer MDQ Drive Strength and RTT 42934e026f9SYork Sun * for data rate <= 1866 43034e026f9SYork Sun */ 43134e026f9SYork Sun uint8_t data_drv_1866; 43234e026f9SYork Sun /* 43334e026f9SYork Sun * 146 Data Buffer MDQ Drive Strength and RTT 43434e026f9SYork Sun * for 1866 < data rate <= 2400 43534e026f9SYork Sun */ 43634e026f9SYork Sun uint8_t data_drv_2400; 43734e026f9SYork Sun /* 43834e026f9SYork Sun * 147 Data Buffer MDQ Drive Strength and RTT 43934e026f9SYork Sun * for 2400 < data rate <= 3200 44034e026f9SYork Sun */ 44134e026f9SYork Sun uint8_t data_drv_3200; 44234e026f9SYork Sun /* 148 DRAM Drive Strength */ 44334e026f9SYork Sun uint8_t dram_drv; 44434e026f9SYork Sun /* 44534e026f9SYork Sun * 149 DRAM ODT (RTT_WR, RTT_NOM) 44634e026f9SYork Sun * for data rate <= 1866 44734e026f9SYork Sun */ 44834e026f9SYork Sun uint8_t dram_odt_1866; 44934e026f9SYork Sun /* 45034e026f9SYork Sun * 150 DRAM ODT (RTT_WR, RTT_NOM) 45134e026f9SYork Sun * for 1866 < data rate <= 2400 45234e026f9SYork Sun */ 45334e026f9SYork Sun uint8_t dram_odt_2400; 45434e026f9SYork Sun /* 45534e026f9SYork Sun * 151 DRAM ODT (RTT_WR, RTT_NOM) 45634e026f9SYork Sun * for 2400 < data rate <= 3200 45734e026f9SYork Sun */ 45834e026f9SYork Sun uint8_t dram_odt_3200; 45934e026f9SYork Sun /* 46034e026f9SYork Sun * 152 DRAM ODT (RTT_PARK) 46134e026f9SYork Sun * for data rate <= 1866 46234e026f9SYork Sun */ 46334e026f9SYork Sun uint8_t dram_odt_park_1866; 46434e026f9SYork Sun /* 46534e026f9SYork Sun * 153 DRAM ODT (RTT_PARK) 46634e026f9SYork Sun * for 1866 < data rate <= 2400 46734e026f9SYork Sun */ 46834e026f9SYork Sun uint8_t dram_odt_park_2400; 46934e026f9SYork Sun /* 47034e026f9SYork Sun * 154 DRAM ODT (RTT_PARK) 47134e026f9SYork Sun * for 2400 < data rate <= 3200 47234e026f9SYork Sun */ 47334e026f9SYork Sun uint8_t dram_odt_park_3200; 47434e026f9SYork Sun uint8_t res_155[254-155]; /* Reserved */ 47534e026f9SYork Sun /* 254~255 CRC */ 47634e026f9SYork Sun uint8_t crc[2]; 47734e026f9SYork Sun } loadreduced; 47834e026f9SYork Sun uint8_t uc[128]; /* 128-255 Module-Specific Section */ 47934e026f9SYork Sun } mod_section; 48034e026f9SYork Sun 48134e026f9SYork Sun uint8_t res_256[320-256]; /* 256~319 Reserved */ 48234e026f9SYork Sun 48334e026f9SYork Sun /* Module supplier's data: Byte 320~383 */ 48434e026f9SYork Sun uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */ 48534e026f9SYork Sun uint8_t mmid_msb; /* 321 Module MfgID Code MSB */ 48634e026f9SYork Sun uint8_t mloc; /* 322 Mfg Location */ 48734e026f9SYork Sun uint8_t mdate[2]; /* 323~324 Mfg Date */ 48834e026f9SYork Sun uint8_t sernum[4]; /* 325~328 Module Serial Number */ 48934e026f9SYork Sun uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */ 49034e026f9SYork Sun uint8_t mrev; /* 349 Module Revision Code */ 49134e026f9SYork Sun uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */ 49234e026f9SYork Sun uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */ 49334e026f9SYork Sun uint8_t stepping; /* 352 DRAM stepping */ 49434e026f9SYork Sun uint8_t msd[29]; /* 353~381 Mfg's Specific Data */ 49534e026f9SYork Sun uint8_t res_382[2]; /* 382~383 Reserved */ 49634e026f9SYork Sun 49734e026f9SYork Sun uint8_t user[512-384]; /* 384~511 End User Programmable */ 49834e026f9SYork Sun }; 49934e026f9SYork Sun 5000f2cbe3fSJames Yang extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd); 5010f2cbe3fSJames Yang extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd); 5020f2cbe3fSJames Yang extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd); 5030f2cbe3fSJames Yang extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd); 504c360ceacSDave Liu extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); 50534e026f9SYork Sun unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd); 5060f2cbe3fSJames Yang 5070f2cbe3fSJames Yang /* 5080f2cbe3fSJames Yang * Byte 2 Fundamental Memory Types. 5090f2cbe3fSJames Yang */ 5100f2cbe3fSJames Yang #define SPD_MEMTYPE_FPM (0x01) 5110f2cbe3fSJames Yang #define SPD_MEMTYPE_EDO (0x02) 5120f2cbe3fSJames Yang #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) 5130f2cbe3fSJames Yang #define SPD_MEMTYPE_SDRAM (0x04) 5140f2cbe3fSJames Yang #define SPD_MEMTYPE_ROM (0x05) 5150f2cbe3fSJames Yang #define SPD_MEMTYPE_SGRAM (0x06) 5160f2cbe3fSJames Yang #define SPD_MEMTYPE_DDR (0x07) 5170f2cbe3fSJames Yang #define SPD_MEMTYPE_DDR2 (0x08) 5180f2cbe3fSJames Yang #define SPD_MEMTYPE_DDR2_FBDIMM (0x09) 5190f2cbe3fSJames Yang #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) 5200f2cbe3fSJames Yang #define SPD_MEMTYPE_DDR3 (0x0B) 52134e026f9SYork Sun #define SPD_MEMTYPE_DDR4 (0x0C) 5220f2cbe3fSJames Yang 523c7fd27ccSKyle Moffett /* DIMM Type for DDR2 SPD (according to v1.3) */ 524c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) 525c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_RDIMM (0x01) 526c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_UDIMM (0x02) 527c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) 528c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) 529c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) 530c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) 531c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) 532c7fd27ccSKyle Moffett #define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) 533c7fd27ccSKyle Moffett 534c7fd27ccSKyle Moffett /* Byte 3 Key Byte / Module Type for DDR3 SPD */ 535c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_MASK (0x0f) 536c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_RDIMM (0x01) 537c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_UDIMM (0x02) 538c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) 539c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) 540c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) 541c7fd27ccSKyle Moffett #define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) 5422f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07) 5432f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08) 5442f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09) 5452f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A) 5462f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_LRDIMM (0x0B) 5472f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C) 5482f3a71f2SIra W. Snyder #define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D) 549c360ceacSDave Liu 55034e026f9SYork Sun /* DIMM Type for DDR4 SPD */ 55134e026f9SYork Sun #define DDR4_SPD_MODULETYPE_MASK (0x0f) 55234e026f9SYork Sun #define DDR4_SPD_MODULETYPE_EXT (0x00) 55334e026f9SYork Sun #define DDR4_SPD_MODULETYPE_RDIMM (0x01) 55434e026f9SYork Sun #define DDR4_SPD_MODULETYPE_UDIMM (0x02) 55534e026f9SYork Sun #define DDR4_SPD_MODULETYPE_SO_DIMM (0x03) 55634e026f9SYork Sun #define DDR4_SPD_MODULETYPE_LRDIMM (0x04) 55734e026f9SYork Sun #define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05) 55834e026f9SYork Sun #define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06) 55934e026f9SYork Sun #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) 56034e026f9SYork Sun #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) 56134e026f9SYork Sun #define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C) 56234e026f9SYork Sun #define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D) 56334e026f9SYork Sun 5640f2cbe3fSJames Yang #endif /* _DDR_SPD_H_ */ 565