6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
31 #include "hw/qdev-properties.h"
38 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
55     uint8_t *data = eeprom->data;  in eeprom_receive_byte()
56     uint8_t val = data[eeprom->offset++];  in eeprom_receive_byte()
58     eeprom->accessed = true;  in eeprom_receive_byte()
61            dev->i2c.address, val);  in eeprom_receive_byte()
69     uint8_t *data = eeprom->data;  in eeprom_write_data()
71     eeprom->accessed = true;  in eeprom_write_data()
74            dev->i2c.address, buf[0], buf[1]);  in eeprom_write_data()
76     /* len is guaranteed to be > 0 */  in eeprom_write_data()
77     eeprom->offset = buf[0];  in eeprom_write_data()
79     len--;  in eeprom_write_data()
81     for (; len > 0; len--) {  in eeprom_write_data()
82         data[eeprom->offset] = *buf++;  in eeprom_write_data()
83         eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE;  in eeprom_write_data()
94     return (eeprom->accessed || smbus_vmstate_needed(&eeprom->smbusdev)) &&  in smbus_eeprom_vmstate_needed()
95         !mc->smbus_no_migration_support;  in smbus_eeprom_vmstate_needed()
99     .name = "smbus-eeprom",
113  * Reset the EEPROM contents to the initial state on a reset.  This
115  * principle of QEMU is to restore function on reset to what it would
118  * The proper thing to do would be to have a backing blockdev to hold
126     memcpy(eeprom->data, eeprom->init_data, SMBUS_EEPROM_SIZE);  in smbus_eeprom_reset()
127     eeprom->offset = 0;  in smbus_eeprom_reset()
135     if (eeprom->init_data == NULL) {  in smbus_eeprom_realize()
145     dc->realize = smbus_eeprom_realize;  in smbus_eeprom_class_initfn()
147     sc->receive_byte = eeprom_receive_byte;  in smbus_eeprom_class_initfn()
148     sc->write_data = eeprom_write_data;  in smbus_eeprom_class_initfn()
149     dc->vmsd = &vmstate_smbus_eeprom;  in smbus_eeprom_class_initfn()
151     dc->user_creatable = false;  in smbus_eeprom_class_initfn()
172     SMBUS_EEPROM(dev)->init_data = eeprom_buf;  in DEFINE_TYPES()
221     sz_log2 = 31 - clz32(size);  in spd_data_generate()
228         sz_log2--;  in spd_data_generate()
234     /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */  in spd_data_generate()
236         sz_log2--;  in spd_data_generate()
240     density = 1ULL << (sz_log2 - 2);  in spd_data_generate()
260     spd[5] = (type == DDR2 ? nbanks - 1 : nbanks);  in spd_data_generate()
264     spd[9] = 0x25;  /* highest CAS latency */  in spd_data_generate()
266                     /* DIMM configuration 0 = non-ECC */  in spd_data_generate()
273     spd[18] = 12;   /* ~CAS latencies supported */  in spd_data_generate()
278     spd[23] = 0x12; /* clock cycle time @ medium CAS latency */  in spd_data_generate()
280                     /* clock cycle time @ short CAS latency */  in spd_data_generate()
284     spd[29] = 20;   /* min. ~RAS to ~CAS delay */  in spd_data_generate()
285     spd[30] = 45;   /* min. active to precharge time */  in spd_data_generate()