Lines Matching +full:ras +full:- +full:to +full:- +full:cas
2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
29 * with RTEMS objects to produce an executable application, does not
30 * by itself cause the resulting executable application to be covered
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
75 #define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */
76 #define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */
78 #define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */
79 #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */
80 #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode */
81 #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode */
83 /* (0 - page not cacheable) */
84 #define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been */
85 /* performed to a page) */
86 #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are */
88 #define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the */
90 /* 0 - Copy-back mode */
91 /* 1 - Write-through mode */
93 /* Page Table Entry Assistance register - PTEA */
98 /* 0 - use area 5 wait states */
99 /* 1 - use area 6 wait states */
101 #define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */
102 #define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */
103 #define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */
104 #define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */
105 #define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space */
106 #define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space */
107 #define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */
108 #define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */
116 /* TLB exception address register - TEA */
121 /* MMU control register - MMUCR */
141 * IC -- instructions cache
142 * OC -- operand cache
145 /* Cache Control Register - CCR */
152 /* set it to clear IC */
159 #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
160 #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */
163 /* Queue address control register 0 - QACR0 */
168 /* Queue address control register 1 - QACR1 */
175 * Exception-related registers
178 /* Immediate data for TRAPA instruction - TRA */
186 /* Exception event register - EXPEVT */
207 #define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */
209 #define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */
235 #define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */
252 /* Peripheral Module Interrupts - Timer Unit (TMU) */
258 /* Peripheral Module Interrupts - Real-Time Clock (RTC) */
263 /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
269 /* Peripheral Module Interrupts - Watchdog Timer (WDT) */
274 /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
275 #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */
279 /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
282 /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
285 /* Peripheral Module Interrupts - DMA Controller (DMAC) */
306 #define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: */
307 /* 0 Transition to SLEEP mode on SLEEP */
308 /* 1 Transition to STANDBY mode on SLEEP */
312 /* 1 high-impendance state */
314 #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls */
315 #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */
317 #define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */
319 #define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */
321 #define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */
323 #define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */
333 #define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode */
334 /* 0 transition to sleep or standby mode */
336 /* 1 transition to deep sleep mode on */
338 #define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to the */
341 #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the */
353 /* 0 - CKIO pin goes to HiZ/pullup */
354 /* 1 - Clock is output from CKIO */
359 #define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */
360 #define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */
361 #define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */
362 #define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */
363 #define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */
364 #define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */
367 #define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */
368 #define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */
369 #define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */
370 #define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */
371 #define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */
372 #define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */
376 #define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */
377 #define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */
378 #define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */
379 #define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */
380 #define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */
386 /* Watchdog Timer Counter register - WTCNT */
391 /* have to set the upper byte to 0x5A */
393 /* Watchdog Timer Control/Status register - WTCSR */
398 /* have to set the upper byte to 0xA5 */
399 #define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */
405 #define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */
419 * Real-Time Clock (RTC)
421 /* 64-Hz Counter Register (byte, read-only) - R64CNT */
426 /* Second Counter Register (byte, BCD-coded) - RSECCNT */
431 /* Minute Counter Register (byte, BCD-coded) - RMINCNT */
436 /* Hour Counter Register (byte, BCD-coded) - RHRCNT */
441 /* Day-of-Week Counter Register (byte) - RWKCNT */
454 /* Day Counter Register (byte, BCD-coded) - RDAYCNT */
459 /* Month Counter Register (byte, BCD-coded) - RMONCNT */
464 /* Year Counter Register (half, BCD-coded) - RYRCNT */
469 /* Second Alarm Register (byte, BCD-coded) - RSECAR */
475 /* Minute Alarm Register (byte, BCD-coded) - RMINAR */
481 /* Hour Alarm Register (byte, BCD-coded) - RHRAR */
487 /* Day-of-Week Alarm Register (byte) - RWKAR */
491 #define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */
501 /* Day Alarm Register (byte, BCD-coded) - RDAYAR */
507 /* Month Counter Register (byte, BCD-coded) - RMONAR */
513 /* RTC Control Register 1 (byte) - RCR1 */
522 /* RTC Control Register 2 (byte) - RCR2 */
537 #define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */
539 #define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, */
541 /* 1 - sec, min, hr, day-of-week, month, */
544 * Bus State Controller - BSC
546 /* Bus Control Register 1 - BCR1 */
550 #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */
551 #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */
552 #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */
553 #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: */
554 /* 0 - pull-up resistor is on for */
556 /* 1 - pull-up resistor is off */
557 #define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: */
558 /* 0 - pull-up resistor is on for */
560 /* 1 - pull-up resistor is off */
562 /* 0 - Area 1 SRAM is set to */
564 /* 1 - Area 1 SRAM is set to byte */
567 /* 0 - Area 4 SRAM is set to */
569 /* 1 - Area 4 SRAM is set to byte */
572 /* 0 - External requests are not */
574 /* 1 - External requests are */
577 /* 0 - Master Mode */
578 /* 1 - Partial-sharing Mode */
579 #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: */
580 /* 0 - SRAM/burst ROM interface */
581 /* 1 - MPX interface */
587 /* 0 - signals go to High-Z mode */
588 /* 1 - signals driven */
591 /* RAS\, RAS2\, WEn\, CASn\, DQMn, */
595 /* 0 - signals go to High-Z mode */
596 /* 1 - signals driven */
633 #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 */
637 #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 */
643 /* 0 - SRAM interface */
644 /* 1 - PCMCIA interface */
646 /* Bus Control Register 2 (half) - BCR2 */
670 /* 0 - D51-D32 are not used as a port */
671 /* 1 - D51-D32 are used as a port */
673 /* Wait Control Register 1 - WCR1 */
677 #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle */
680 #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */
682 #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */
684 #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */
686 #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */
688 #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */
690 #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */
692 #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */
695 /* Wait Control Register 2 - WCR2 */
739 /* DRAM CAS\ Assertion Delay (area 3,2) */
749 /* SDRAM CAS\ Latency Cycles */
756 /* Wait Control Register 3 - WCR3 */
792 #define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */
795 #define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of */
806 #define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */
810 #define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period */
824 #define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay */
826 /* SDRAM: bank active-read/write */
843 #define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS */
873 #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */
874 #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */
875 #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */
876 #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */
877 #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */
883 #define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */
895 /* PCMCIA Control Register (half) - PCR */
900 #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait */
901 /* states to be added to the number of */
903 /* low-speed PCMCIA wait cycle */
909 #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait */
910 /* states to be added to the number of */
912 /* low-speed PCMCIA wait cycle */
918 #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Addr-OE\/WE\ Assertion Delay */
919 /* delay time from address output to */
923 #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Addr-OE\/WE\ Assertion Delay */
953 /* Refresh Timer Control/Status Register (half) - RTSCR */
959 #define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a */
962 #define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */
980 /* Refresh Timer Counter (half) - RTCNT */
987 /* Refresh Time Constant Register (half) - RTCOR */
994 /* Refresh Count Register (half) - RFCR */
1001 /* Synchronous DRAM mode registers - SDMR */
1016 /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
1029 /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
1042 /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
1055 /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
1071 #define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */
1072 #define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */
1073 #define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */
1074 #define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */
1075 #define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */
1076 #define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */
1085 #define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */
1086 #define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */
1087 #define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */
1088 #define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */
1089 #define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */
1090 #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */
1126 /* -> External Addr Space) */
1129 /* Space -> External Device) */
1132 /* Device -> External Addr */
1134 #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr */
1135 /* Space -> Ext. Addr Space) */
1137 #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr */
1138 /* Space -> On-chip */
1140 #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip */
1141 /* Peripheral Module -> */
1143 #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr */
1145 /* address space -> SCTDR1) */
1146 #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr */
1148 /* -> External Addr Space) */
1149 #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF TX-Data-Empty intr */
1151 /* address space -> SCFTDR1) */
1152 #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr */
1154 /* -> External Addr Space) */
1157 /* address space -> external */
1161 /* address space -> on-chip */
1164 /* interrupt), (on-chip */
1165 /* peripheral module -> */
1177 #define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */
1183 /* DMA Operation Register - DMAOR */
1188 #define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */
1194 #define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */
1204 /* Port Control Register A - PCTRA */
1214 /* Port Data Register A - PDTRA(half) */
1221 /* Port Control Register B - PCTRB */
1227 #define SH7750_PCTRB_PBNPUP(n) (1 << ((n - 16) * 2 + 1)) /* Bit n is not pulled up */
1229 #define SH7750_PCTRB_PBOUT(n) (1 << ((n - 16) * 2)) /* Bit n is an output */
1231 /* Port Data Register B - PDTRB(half) */
1236 #define SH7750_PDTRB_BIT(n) (1 << ((n) - 16))
1238 /* GPIO Interrupt Control Register - GPIOIC(half) */
1246 * Interrupt Controller - INTC
1248 /* Interrupt Control Register - ICR (half) */
1258 /* SR.BL bit is set to 1 */
1260 /* bit set to 1 */
1269 #define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded */