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/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c31 #define SPEAR1340_GEN_SYNT_CLK_MASK 2
33 #define SPEAR1340_PLL_CLK_MASK 2
56 #define SPEAR1340_UART_CLK_MASK 2
59 #define SPEAR1340_CLCD_CLK_MASK 2
60 #define SPEAR1340_CLCD_CLK_SHIFT 2
66 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
67 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
84 #define SPEAR1340_I2S_REF_SHIFT 2
85 #define SPEAR1340_I2S_SRC_CLK_MASK 2
127 #define SPEAR1340_SYSRAM1_CLK_ENB 2
[all …]
H A Dspear1310_clock.c23 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
25 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
27 #define SPEAR1310_PLL_CLK_MASK 2
51 #define SPEAR1310_UART_CLK_SYNT_VAL 2
52 #define SPEAR1310_UART_CLK_MASK 2
57 #define SPEAR1310_CLCD_CLK_MASK 2
58 #define SPEAR1310_CLCD_CLK_SHIFT 2
67 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
84 #define SPEAR1310_I2S_REF_SHIFT 2
85 #define SPEAR1310_I2S_SRC_CLK_MASK 2
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h70 #define R1_CLKSEL_L4 (2 << 5)
75 #define R1_CLKSEL_MPU (2 << 0)
77 #define R1_CLKSEL_DSP (2 << 0)
78 #define R1_CLKSEL_DSP_IF (2 << 5)
80 #define R1_CLKSEL_GFX (2 << 0)
85 /* 2430-Ratio Config 2 */
87 #define R2_CLKSEL_L4 (2 << 5)
88 #define R2_CLKSEL_USB (2 << 25)
92 #define R2_CLKSEL_MPU (2 << 0)
94 #define R2_CLKSEL_DSP (2 << 0)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h24 u32 pmucru_clkfrac_con[2];
28 u32 pmucru_softrst_con[2];
29 u32 reserved4[2];
30 u32 pmucru_rstnhold_con[2];
31 u32 reserved5[2];
32 u32 pmucru_gatedis_con[2];
38 u32 reserved[2];
40 u32 reserved1[2];
42 u32 reserved2[2];
44 u32 reserved3[2];
[all …]
H A Dcru_rk3328.h27 u32 reserved5[2];
41 u32 sdmmc_con[2];
42 u32 sdio_con[2];
43 u32 emmc_con[2];
44 u32 sdmmc_ext_con[2];
47 #define MHz 1000000 macro
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
97 static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
102 static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
[all …]
H A Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
56 2Gbyte DDR3 (on board DDR), Dual Ranki
58 128Mbyte 2K page size NAND Flash
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
82 2. NAND Flash
[all …]
/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.h22 SERDES_REFCLK_100, /* refclk 100Mhz */
23 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
24 SERDES_REFCLK_125, /* refclk 125Mhz */
25 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
30 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
32 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
42 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
44 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
54 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
57 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
[all …]
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
94 UNIPHIER_LD4_SYS_CLK_NAND(2),
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
30 0f 2c ?
57 2a 13 ?
58 2b 01 ?
59 2c ea ?
60 2d 00 ?
61 2e 00 ? not used?
[all …]
/openbmc/linux/drivers/media/usb/dvb-usb-v2/
H A Daf9035.h58 u8 af9033_i2c_addr[2];
60 struct af9033_config af9033_config[2];
65 struct platform_device *platform_device_tuner[2];
81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h28 #define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
34 #define RADAR_TYPE_STG2 8 /* staggered-2 radar */
49 #define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
50 #define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
55 #define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
60 #define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
63 #define WL_ANT_IDX_2 1 /* antenna index 2 */
68 #define BRCMS_N_PREAMBLE_GF_BRCM 2
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h50 #define WL12XX_NUM_MAC_ADDRESSES 2
73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
57 uint8_t Padding[2];
124 //Freq in MHz
125 //Voltage in milli volts with 2 fractional bits
150 uint8_t spare[2];
157 #define THROTTLER_STATUS_BIT_SPPT 2
168 uint16_t GfxclkFrequency; //[MHz]
169 uint16_t SocclkFrequency; //[MHz]
[all …]
H A Dsmu13_driver_if_yellow_carp.h45 uint16_t Freq; // in MHz
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
57 uint8_t Padding[2];
119 //Freq in MHz
120 //Voltage in milli volts with 2 fractional bits
146 #define THROTTLER_STATUS_BIT_SPPT 2
159 uint16_t GfxclkFrequency; //[MHz]
160 uint16_t SocclkFrequency; //[MHz]
161 uint16_t VclkFrequency; //[MHz]
[all …]
/openbmc/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos3250.c99 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
233 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
234 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
349 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
460 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
502 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
513 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
541 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
552 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
569 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c28 return 2; in get_num_cpus()
55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
72 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
75 { /* 24 MHz */
76 {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
81 {125, 2, 1, -1, -1, -1, -1} /* OPP NT */
83 { /* 25 MHz */
84 {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
91 { /* 26 MHz */
92 {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt15 2 - CPU capacity definition
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
69 #address-cells = <2>;
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