105491d2cSKalle Valo /* 205491d2cSKalle Valo * Copyright (c) 2010 Broadcom Corporation 305491d2cSKalle Valo * 405491d2cSKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 505491d2cSKalle Valo * purpose with or without fee is hereby granted, provided that the above 605491d2cSKalle Valo * copyright notice and this permission notice appear in all copies. 705491d2cSKalle Valo * 805491d2cSKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 905491d2cSKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1005491d2cSKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 1105491d2cSKalle Valo * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1205491d2cSKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 1305491d2cSKalle Valo * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 1405491d2cSKalle Valo * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1505491d2cSKalle Valo */ 1605491d2cSKalle Valo 1705491d2cSKalle Valo /* 1805491d2cSKalle Valo * phy_shim.h: stuff defined in phy_shim.c and included only by the phy 1905491d2cSKalle Valo */ 2005491d2cSKalle Valo 2105491d2cSKalle Valo #ifndef _BRCM_PHY_SHIM_H_ 2205491d2cSKalle Valo #define _BRCM_PHY_SHIM_H_ 2305491d2cSKalle Valo 2405491d2cSKalle Valo #include "types.h" 2505491d2cSKalle Valo 2605491d2cSKalle Valo #define RADAR_TYPE_NONE 0 /* Radar type None */ 2705491d2cSKalle Valo #define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */ 2805491d2cSKalle Valo #define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */ 2905491d2cSKalle Valo #define RADAR_TYPE_ETSI_3 3 /* ETSI 3 Radar type */ 3005491d2cSKalle Valo #define RADAR_TYPE_ITU_E 4 /* ITU E Radar type */ 3105491d2cSKalle Valo #define RADAR_TYPE_ITU_K 5 /* ITU K Radar type */ 3205491d2cSKalle Valo #define RADAR_TYPE_UNCLASSIFIED 6 /* Unclassified Radar type */ 3305491d2cSKalle Valo #define RADAR_TYPE_BIN5 7 /* long pulse radar type */ 3405491d2cSKalle Valo #define RADAR_TYPE_STG2 8 /* staggered-2 radar */ 3505491d2cSKalle Valo #define RADAR_TYPE_STG3 9 /* staggered-3 radar */ 3605491d2cSKalle Valo #define RADAR_TYPE_FRA 10 /* French radar */ 3705491d2cSKalle Valo 3805491d2cSKalle Valo /* French radar pulse widths */ 3905491d2cSKalle Valo #define FRA_T1_20MHZ 52770 4005491d2cSKalle Valo #define FRA_T2_20MHZ 61538 4105491d2cSKalle Valo #define FRA_T3_20MHZ 66002 4205491d2cSKalle Valo #define FRA_T1_40MHZ 105541 4305491d2cSKalle Valo #define FRA_T2_40MHZ 123077 4405491d2cSKalle Valo #define FRA_T3_40MHZ 132004 4505491d2cSKalle Valo #define FRA_ERR_20MHZ 60 4605491d2cSKalle Valo #define FRA_ERR_40MHZ 120 4705491d2cSKalle Valo 4805491d2cSKalle Valo #define ANTSEL_NA 0 /* No boardlevel selection available */ 4905491d2cSKalle Valo #define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */ 5005491d2cSKalle Valo #define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */ 5105491d2cSKalle Valo 5205491d2cSKalle Valo /* Rx Antenna diversity control values */ 5305491d2cSKalle Valo #define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */ 5405491d2cSKalle Valo #define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */ 5505491d2cSKalle Valo #define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */ 5605491d2cSKalle Valo #define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */ 5705491d2cSKalle Valo #define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */ 5805491d2cSKalle Valo #define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */ 5905491d2cSKalle Valo 6005491d2cSKalle Valo #define WL_ANT_RX_MAX 2 /* max 2 receive antennas */ 6105491d2cSKalle Valo #define WL_ANT_HT_RX_MAX 3 /* max 3 receive antennas/cores */ 6205491d2cSKalle Valo #define WL_ANT_IDX_1 0 /* antenna index 1 */ 6305491d2cSKalle Valo #define WL_ANT_IDX_2 1 /* antenna index 2 */ 6405491d2cSKalle Valo 6505491d2cSKalle Valo /* values for n_preamble_type */ 6605491d2cSKalle Valo #define BRCMS_N_PREAMBLE_MIXEDMODE 0 6705491d2cSKalle Valo #define BRCMS_N_PREAMBLE_GF 1 6805491d2cSKalle Valo #define BRCMS_N_PREAMBLE_GF_BRCM 2 6905491d2cSKalle Valo 7005491d2cSKalle Valo #define WL_TX_POWER_RATES_LEGACY 45 7105491d2cSKalle Valo #define WL_TX_POWER_MCS20_FIRST 12 7205491d2cSKalle Valo #define WL_TX_POWER_MCS20_NUM 16 7305491d2cSKalle Valo #define WL_TX_POWER_MCS40_FIRST 28 7405491d2cSKalle Valo #define WL_TX_POWER_MCS40_NUM 17 7505491d2cSKalle Valo 7605491d2cSKalle Valo 7705491d2cSKalle Valo #define WL_TX_POWER_RATES 101 7805491d2cSKalle Valo #define WL_TX_POWER_CCK_FIRST 0 7905491d2cSKalle Valo #define WL_TX_POWER_CCK_NUM 4 8005491d2cSKalle Valo /* Index for first 20MHz OFDM SISO rate */ 8105491d2cSKalle Valo #define WL_TX_POWER_OFDM_FIRST 4 8205491d2cSKalle Valo /* Index for first 20MHz OFDM CDD rate */ 8305491d2cSKalle Valo #define WL_TX_POWER_OFDM20_CDD_FIRST 12 8405491d2cSKalle Valo /* Index for first 40MHz OFDM SISO rate */ 8505491d2cSKalle Valo #define WL_TX_POWER_OFDM40_SISO_FIRST 52 8605491d2cSKalle Valo /* Index for first 40MHz OFDM CDD rate */ 8705491d2cSKalle Valo #define WL_TX_POWER_OFDM40_CDD_FIRST 60 8805491d2cSKalle Valo #define WL_TX_POWER_OFDM_NUM 8 8905491d2cSKalle Valo /* Index for first 20MHz MCS SISO rate */ 9005491d2cSKalle Valo #define WL_TX_POWER_MCS20_SISO_FIRST 20 9105491d2cSKalle Valo /* Index for first 20MHz MCS CDD rate */ 9205491d2cSKalle Valo #define WL_TX_POWER_MCS20_CDD_FIRST 28 9305491d2cSKalle Valo /* Index for first 20MHz MCS STBC rate */ 9405491d2cSKalle Valo #define WL_TX_POWER_MCS20_STBC_FIRST 36 9505491d2cSKalle Valo /* Index for first 20MHz MCS SDM rate */ 9605491d2cSKalle Valo #define WL_TX_POWER_MCS20_SDM_FIRST 44 9705491d2cSKalle Valo /* Index for first 40MHz MCS SISO rate */ 9805491d2cSKalle Valo #define WL_TX_POWER_MCS40_SISO_FIRST 68 9905491d2cSKalle Valo /* Index for first 40MHz MCS CDD rate */ 10005491d2cSKalle Valo #define WL_TX_POWER_MCS40_CDD_FIRST 76 10105491d2cSKalle Valo /* Index for first 40MHz MCS STBC rate */ 10205491d2cSKalle Valo #define WL_TX_POWER_MCS40_STBC_FIRST 84 10305491d2cSKalle Valo /* Index for first 40MHz MCS SDM rate */ 10405491d2cSKalle Valo #define WL_TX_POWER_MCS40_SDM_FIRST 92 10505491d2cSKalle Valo #define WL_TX_POWER_MCS_1_STREAM_NUM 8 10605491d2cSKalle Valo #define WL_TX_POWER_MCS_2_STREAM_NUM 8 10705491d2cSKalle Valo /* Index for 40MHz rate MCS 32 */ 10805491d2cSKalle Valo #define WL_TX_POWER_MCS_32 100 10905491d2cSKalle Valo #define WL_TX_POWER_MCS_32_NUM 1 11005491d2cSKalle Valo 11105491d2cSKalle Valo /* sslpnphy specifics */ 11205491d2cSKalle Valo /* Index for first 20MHz MCS SISO rate */ 11305491d2cSKalle Valo #define WL_TX_POWER_MCS20_SISO_FIRST_SSN 12 11405491d2cSKalle Valo 11505491d2cSKalle Valo /* struct tx_power::flags bits */ 11605491d2cSKalle Valo #define WL_TX_POWER_F_ENABLED 1 11705491d2cSKalle Valo #define WL_TX_POWER_F_HW 2 11805491d2cSKalle Valo #define WL_TX_POWER_F_MIMO 4 11905491d2cSKalle Valo #define WL_TX_POWER_F_SISO 8 12005491d2cSKalle Valo 12105491d2cSKalle Valo /* values to force tx/rx chain */ 12205491d2cSKalle Valo #define BRCMS_N_TXRX_CHAIN0 0 12305491d2cSKalle Valo #define BRCMS_N_TXRX_CHAIN1 1 12405491d2cSKalle Valo 12505491d2cSKalle Valo struct brcms_phy; 12605491d2cSKalle Valo 12705491d2cSKalle Valo struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw, 12805491d2cSKalle Valo struct brcms_info *wl, 12905491d2cSKalle Valo struct brcms_c_info *wlc); 13005491d2cSKalle Valo void wlc_phy_shim_detach(struct phy_shim_info *physhim); 13105491d2cSKalle Valo 13205491d2cSKalle Valo /* PHY to WL utility functions */ 13305491d2cSKalle Valo struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim, 134*f8e360c7SArnd Bergmann void (*fn)(void *pi), 13505491d2cSKalle Valo void *arg, const char *name); 13605491d2cSKalle Valo void wlapi_free_timer(struct wlapi_timer *t); 13705491d2cSKalle Valo void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic); 13805491d2cSKalle Valo bool wlapi_del_timer(struct wlapi_timer *t); 13905491d2cSKalle Valo void wlapi_intrson(struct phy_shim_info *physhim); 14005491d2cSKalle Valo u32 wlapi_intrsoff(struct phy_shim_info *physhim); 14105491d2cSKalle Valo void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask); 14205491d2cSKalle Valo 14305491d2cSKalle Valo void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v); 14405491d2cSKalle Valo u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset); 14505491d2cSKalle Valo void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val, 14605491d2cSKalle Valo int bands); 14705491d2cSKalle Valo void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags); 14805491d2cSKalle Valo void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim); 14905491d2cSKalle Valo void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode); 15005491d2cSKalle Valo void wlapi_enable_mac(struct phy_shim_info *physhim); 15105491d2cSKalle Valo void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val); 15205491d2cSKalle Valo void wlapi_bmac_phy_reset(struct phy_shim_info *physhim); 15305491d2cSKalle Valo void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw); 15405491d2cSKalle Valo void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk); 15505491d2cSKalle Valo void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk); 15605491d2cSKalle Valo void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on); 15705491d2cSKalle Valo void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim); 15805491d2cSKalle Valo void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim); 15905491d2cSKalle Valo void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim); 16005491d2cSKalle Valo void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o, 16105491d2cSKalle Valo int len, void *buf); 16205491d2cSKalle Valo u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate); 16305491d2cSKalle Valo void wlapi_ucode_sample_init(struct phy_shim_info *physhim); 16405491d2cSKalle Valo void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint, void *buf, 16505491d2cSKalle Valo int, u32 sel); 16605491d2cSKalle Valo void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint, const void *buf, 16705491d2cSKalle Valo int, u32); 16805491d2cSKalle Valo 16905491d2cSKalle Valo void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, u32 phy_mode); 17005491d2cSKalle Valo u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim); 17105491d2cSKalle Valo 17205491d2cSKalle Valo #endif /* _BRCM_PHY_SHIM_H_ */ 173