Lines Matching +full:2 +full:mhz
28 return 2; in get_num_cpus()
55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
76 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
77 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
78 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
81 * T30: 600 MHz
91 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
92 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
93 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
94 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
95 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
96 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
99 * T114: 700 MHz
108 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
109 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
110 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
111 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
112 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
113 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
117 * T124: 700 MHz
126 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
127 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
128 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
129 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
130 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
131 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
135 * T210: 700 MHz
144 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
145 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
146 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
147 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
148 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
149 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
164 udelay(2); in pllx_set_iddq()
201 /* Set dccon to PLLX_MISC if freq > 600MHz */ in pllx_set_rate()
379 u32 rst, src = 2; in clock_enable_coresight()
389 * Clock divider request would setup CSITE clock as 144MHz in clock_enable_coresight()
390 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz in clock_enable_coresight()