1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2d8a94458SPaul Walmsley /* 3d8a94458SPaul Walmsley * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions 4d8a94458SPaul Walmsley * 5d8a94458SPaul Walmsley * Copyright (C) 2005-2009 Texas Instruments, Inc. 6d8a94458SPaul Walmsley * Copyright (C) 2004-2009 Nokia Corporation 7d8a94458SPaul Walmsley * 8d8a94458SPaul Walmsley * Richard Woodruff <r-woodruff2@ti.com> 9d8a94458SPaul Walmsley * 10d8a94458SPaul Walmsley * The OMAP2 processor can be run at several discrete 'PRCM configurations'. 11d8a94458SPaul Walmsley * These configurations are characterized by voltage and speed for clocks. 12d8a94458SPaul Walmsley * The device is only validated for certain combinations. One way to express 13d8a94458SPaul Walmsley * these combinations is via the 'ratio's' which the clocks operate with 14d8a94458SPaul Walmsley * respect to each other. These ratio sets are for a given voltage/DPLL 15d8a94458SPaul Walmsley * setting. All configurations can be described by a DPLL setting and a ratio 16d8a94458SPaul Walmsley * There are 3 ratio sets for the 2430 and X ratio sets for 2420. 17d8a94458SPaul Walmsley * 18d8a94458SPaul Walmsley * 2430 differs from 2420 in that there are no more phase synchronizers used. 19d8a94458SPaul Walmsley * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs 20d8a94458SPaul Walmsley * 2430 (iva2.1, NOdsp, mdm) 21d8a94458SPaul Walmsley * 22d8a94458SPaul Walmsley * XXX Missing voltage data. 23d8a94458SPaul Walmsley * 24d8a94458SPaul Walmsley * THe format described in this file is deprecated. Once a reasonable 25d8a94458SPaul Walmsley * OPP API exists, the data in this file should be converted to use it. 26d8a94458SPaul Walmsley * 27d8a94458SPaul Walmsley * This is technically part of the OMAP2xxx clock code. 28d8a94458SPaul Walmsley */ 29d8a94458SPaul Walmsley 30d8a94458SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 31d8a94458SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H 32d8a94458SPaul Walmsley 33d8a94458SPaul Walmsley /** 34d8a94458SPaul Walmsley * struct prcm_config - define clock rates on a per-OPP basis (24xx) 35d8a94458SPaul Walmsley * 36d8a94458SPaul Walmsley * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 37d8a94458SPaul Walmsley * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 38d8a94458SPaul Walmsley * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 39d8a94458SPaul Walmsley * 40d8a94458SPaul Walmsley * This is deprecated. As soon as we have a decent OPP API, we should 41d8a94458SPaul Walmsley * move all this stuff to it. 42d8a94458SPaul Walmsley */ 43d8a94458SPaul Walmsley struct prcm_config { 44d8a94458SPaul Walmsley unsigned long xtal_speed; /* crystal rate */ 45d8a94458SPaul Walmsley unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ 46d8a94458SPaul Walmsley unsigned long mpu_speed; /* speed of MPU */ 47d8a94458SPaul Walmsley unsigned long cm_clksel_mpu; /* mpu divider */ 48d8a94458SPaul Walmsley unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ 49d8a94458SPaul Walmsley unsigned long cm_clksel_gfx; /* gfx dividers */ 50d8a94458SPaul Walmsley unsigned long cm_clksel1_core; /* major subsystem dividers */ 51d8a94458SPaul Walmsley unsigned long cm_clksel1_pll; /* m,n */ 52d8a94458SPaul Walmsley unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ 53d8a94458SPaul Walmsley unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ 54d8a94458SPaul Walmsley unsigned long base_sdrc_rfr; /* base refresh timing for a set */ 5599541195SAfzal Mohammed unsigned short flags; 56d8a94458SPaul Walmsley }; 57d8a94458SPaul Walmsley 58d8a94458SPaul Walmsley 59d8a94458SPaul Walmsley /* Core fields for cm_clksel, not ratio governed */ 60d8a94458SPaul Walmsley #define RX_CLKSEL_DSS1 (0x10 << 8) 61d8a94458SPaul Walmsley #define RX_CLKSEL_DSS2 (0x0 << 13) 62d8a94458SPaul Walmsley #define RX_CLKSEL_SSI (0x5 << 20) 63d8a94458SPaul Walmsley 64d8a94458SPaul Walmsley /*------------------------------------------------------------------------- 65d8a94458SPaul Walmsley * Voltage/DPLL ratios 66d8a94458SPaul Walmsley *-------------------------------------------------------------------------*/ 67d8a94458SPaul Walmsley 68d8a94458SPaul Walmsley /* 2430 Ratio's, 2430-Ratio Config 1 */ 69d8a94458SPaul Walmsley #define R1_CLKSEL_L3 (4 << 0) 70d8a94458SPaul Walmsley #define R1_CLKSEL_L4 (2 << 5) 71d8a94458SPaul Walmsley #define R1_CLKSEL_USB (4 << 25) 72d8a94458SPaul Walmsley #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \ 73d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 74d8a94458SPaul Walmsley R1_CLKSEL_L4 | R1_CLKSEL_L3) 75d8a94458SPaul Walmsley #define R1_CLKSEL_MPU (2 << 0) 76d8a94458SPaul Walmsley #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU 77d8a94458SPaul Walmsley #define R1_CLKSEL_DSP (2 << 0) 78d8a94458SPaul Walmsley #define R1_CLKSEL_DSP_IF (2 << 5) 79d8a94458SPaul Walmsley #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) 80d8a94458SPaul Walmsley #define R1_CLKSEL_GFX (2 << 0) 81d8a94458SPaul Walmsley #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX 82d8a94458SPaul Walmsley #define R1_CLKSEL_MDM (4 << 0) 83d8a94458SPaul Walmsley #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM 84d8a94458SPaul Walmsley 85d8a94458SPaul Walmsley /* 2430-Ratio Config 2 */ 86d8a94458SPaul Walmsley #define R2_CLKSEL_L3 (6 << 0) 87d8a94458SPaul Walmsley #define R2_CLKSEL_L4 (2 << 5) 88d8a94458SPaul Walmsley #define R2_CLKSEL_USB (2 << 25) 89d8a94458SPaul Walmsley #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \ 90d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 91d8a94458SPaul Walmsley R2_CLKSEL_L4 | R2_CLKSEL_L3) 92d8a94458SPaul Walmsley #define R2_CLKSEL_MPU (2 << 0) 93d8a94458SPaul Walmsley #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU 94d8a94458SPaul Walmsley #define R2_CLKSEL_DSP (2 << 0) 95d8a94458SPaul Walmsley #define R2_CLKSEL_DSP_IF (3 << 5) 96d8a94458SPaul Walmsley #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) 97d8a94458SPaul Walmsley #define R2_CLKSEL_GFX (2 << 0) 98d8a94458SPaul Walmsley #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX 99d8a94458SPaul Walmsley #define R2_CLKSEL_MDM (6 << 0) 100d8a94458SPaul Walmsley #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM 101d8a94458SPaul Walmsley 102d8a94458SPaul Walmsley /* 2430-Ratio Bootm (BYPASS) */ 103d8a94458SPaul Walmsley #define RB_CLKSEL_L3 (1 << 0) 104d8a94458SPaul Walmsley #define RB_CLKSEL_L4 (1 << 5) 105d8a94458SPaul Walmsley #define RB_CLKSEL_USB (1 << 25) 106d8a94458SPaul Walmsley #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \ 107d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 108d8a94458SPaul Walmsley RB_CLKSEL_L4 | RB_CLKSEL_L3) 109d8a94458SPaul Walmsley #define RB_CLKSEL_MPU (1 << 0) 110d8a94458SPaul Walmsley #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU 111d8a94458SPaul Walmsley #define RB_CLKSEL_DSP (1 << 0) 112d8a94458SPaul Walmsley #define RB_CLKSEL_DSP_IF (1 << 5) 113d8a94458SPaul Walmsley #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) 114d8a94458SPaul Walmsley #define RB_CLKSEL_GFX (1 << 0) 115d8a94458SPaul Walmsley #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX 116d8a94458SPaul Walmsley #define RB_CLKSEL_MDM (1 << 0) 117d8a94458SPaul Walmsley #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM 118d8a94458SPaul Walmsley 119d8a94458SPaul Walmsley /* 2420 Ratio Equivalents */ 120d8a94458SPaul Walmsley #define RXX_CLKSEL_VLYNQ (0x12 << 15) 121d8a94458SPaul Walmsley #define RXX_CLKSEL_SSI (0x8 << 20) 122d8a94458SPaul Walmsley 123d8a94458SPaul Walmsley /* 2420-PRCM III 532MHz core */ 124d8a94458SPaul Walmsley #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ 125d8a94458SPaul Walmsley #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ 126d8a94458SPaul Walmsley #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ 127d8a94458SPaul Walmsley #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 128d8a94458SPaul Walmsley RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 129d8a94458SPaul Walmsley RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ 130d8a94458SPaul Walmsley RIII_CLKSEL_L3) 131d8a94458SPaul Walmsley #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ 132d8a94458SPaul Walmsley #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU 133d8a94458SPaul Walmsley #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ 134d8a94458SPaul Walmsley #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ 135d8a94458SPaul Walmsley #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ 136d8a94458SPaul Walmsley #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ 137d8a94458SPaul Walmsley #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ 138d8a94458SPaul Walmsley #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ 139d8a94458SPaul Walmsley RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ 140d8a94458SPaul Walmsley RIII_CLKSEL_DSP) 141d8a94458SPaul Walmsley #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ 142d8a94458SPaul Walmsley #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX 143d8a94458SPaul Walmsley 144d8a94458SPaul Walmsley /* 2420-PRCM II 600MHz core */ 145d8a94458SPaul Walmsley #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ 146d8a94458SPaul Walmsley #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ 147d8a94458SPaul Walmsley #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ 148d8a94458SPaul Walmsley #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \ 149d8a94458SPaul Walmsley RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ 150d8a94458SPaul Walmsley RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \ 151d8a94458SPaul Walmsley RII_CLKSEL_L3) 152d8a94458SPaul Walmsley #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ 153d8a94458SPaul Walmsley #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU 154d8a94458SPaul Walmsley #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ 155d8a94458SPaul Walmsley #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ 156d8a94458SPaul Walmsley #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ 157d8a94458SPaul Walmsley #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */ 158d8a94458SPaul Walmsley #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ 159d8a94458SPaul Walmsley #define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \ 160d8a94458SPaul Walmsley RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ 161d8a94458SPaul Walmsley RII_CLKSEL_DSP) 162d8a94458SPaul Walmsley #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ 163d8a94458SPaul Walmsley #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX 164d8a94458SPaul Walmsley 165d8a94458SPaul Walmsley /* 2420-PRCM I 660MHz core */ 166d8a94458SPaul Walmsley #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */ 167d8a94458SPaul Walmsley #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */ 168d8a94458SPaul Walmsley #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */ 169d8a94458SPaul Walmsley #define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \ 170d8a94458SPaul Walmsley RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ 171d8a94458SPaul Walmsley RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ 172d8a94458SPaul Walmsley RI_CLKSEL_L4 | RI_CLKSEL_L3) 173d8a94458SPaul Walmsley #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */ 174d8a94458SPaul Walmsley #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU 175d8a94458SPaul Walmsley #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */ 176d8a94458SPaul Walmsley #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */ 177d8a94458SPaul Walmsley #define RI_SYNC_DSP (1 << 7) /* Activate sync */ 178d8a94458SPaul Walmsley #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */ 179d8a94458SPaul Walmsley #define RI_SYNC_IVA (0 << 13) /* Bypass sync */ 180d8a94458SPaul Walmsley #define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \ 181d8a94458SPaul Walmsley RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \ 182d8a94458SPaul Walmsley RI_CLKSEL_DSP) 183d8a94458SPaul Walmsley #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */ 184d8a94458SPaul Walmsley #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX 185d8a94458SPaul Walmsley 186d8a94458SPaul Walmsley /* 2420-PRCM VII (boot) */ 187d8a94458SPaul Walmsley #define RVII_CLKSEL_L3 (1 << 0) 188d8a94458SPaul Walmsley #define RVII_CLKSEL_L4 (1 << 5) 189d8a94458SPaul Walmsley #define RVII_CLKSEL_DSS1 (1 << 8) 190d8a94458SPaul Walmsley #define RVII_CLKSEL_DSS2 (0 << 13) 191d8a94458SPaul Walmsley #define RVII_CLKSEL_VLYNQ (1 << 15) 192d8a94458SPaul Walmsley #define RVII_CLKSEL_SSI (1 << 20) 193d8a94458SPaul Walmsley #define RVII_CLKSEL_USB (1 << 25) 194d8a94458SPaul Walmsley 195d8a94458SPaul Walmsley #define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ 196d8a94458SPaul Walmsley RVII_CLKSEL_VLYNQ | \ 197d8a94458SPaul Walmsley RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \ 198d8a94458SPaul Walmsley RVII_CLKSEL_L4 | RVII_CLKSEL_L3) 199d8a94458SPaul Walmsley 200d8a94458SPaul Walmsley #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ 201d8a94458SPaul Walmsley #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU 202d8a94458SPaul Walmsley 203d8a94458SPaul Walmsley #define RVII_CLKSEL_DSP (1 << 0) 204d8a94458SPaul Walmsley #define RVII_CLKSEL_DSP_IF (1 << 5) 205d8a94458SPaul Walmsley #define RVII_SYNC_DSP (0 << 7) 206d8a94458SPaul Walmsley #define RVII_CLKSEL_IVA (1 << 8) 207d8a94458SPaul Walmsley #define RVII_SYNC_IVA (0 << 13) 208d8a94458SPaul Walmsley #define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \ 209d8a94458SPaul Walmsley RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \ 210d8a94458SPaul Walmsley RVII_CLKSEL_DSP) 211d8a94458SPaul Walmsley 212d8a94458SPaul Walmsley #define RVII_CLKSEL_GFX (1 << 0) 213d8a94458SPaul Walmsley #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX 214d8a94458SPaul Walmsley 215d8a94458SPaul Walmsley /*------------------------------------------------------------------------- 216d8a94458SPaul Walmsley * 2430 Target modes: Along with each configuration the CPU has several 217d8a94458SPaul Walmsley * modes which goes along with them. Modes mainly are the addition of 218d8a94458SPaul Walmsley * describe DPLL combinations to go along with a ratio. 219d8a94458SPaul Walmsley *-------------------------------------------------------------------------*/ 220d8a94458SPaul Walmsley 221d8a94458SPaul Walmsley /* Hardware governed */ 222d8a94458SPaul Walmsley #define MX_48M_SRC (0 << 3) 223d8a94458SPaul Walmsley #define MX_54M_SRC (0 << 5) 224d8a94458SPaul Walmsley #define MX_APLLS_CLIKIN_12 (3 << 23) 225d8a94458SPaul Walmsley #define MX_APLLS_CLIKIN_13 (2 << 23) 226d8a94458SPaul Walmsley #define MX_APLLS_CLIKIN_19_2 (0 << 23) 227d8a94458SPaul Walmsley 228d8a94458SPaul Walmsley /* 229d8a94458SPaul Walmsley * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed 230d8a94458SPaul Walmsley * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz 231d8a94458SPaul Walmsley */ 232d8a94458SPaul Walmsley #define M5A_DPLL_MULT_12 (133 << 12) 233d8a94458SPaul Walmsley #define M5A_DPLL_DIV_12 (5 << 8) 234d8a94458SPaul Walmsley #define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 235d8a94458SPaul Walmsley M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ 236d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 237d8a94458SPaul Walmsley #define M5A_DPLL_MULT_13 (61 << 12) 238d8a94458SPaul Walmsley #define M5A_DPLL_DIV_13 (2 << 8) 239d8a94458SPaul Walmsley #define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 240d8a94458SPaul Walmsley M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ 241d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 242d8a94458SPaul Walmsley #define M5A_DPLL_MULT_19 (55 << 12) 243d8a94458SPaul Walmsley #define M5A_DPLL_DIV_19 (3 << 8) 244d8a94458SPaul Walmsley #define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 245d8a94458SPaul Walmsley M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ 246d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 247d8a94458SPaul Walmsley /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ 248d8a94458SPaul Walmsley #define M5B_DPLL_MULT_12 (50 << 12) 249d8a94458SPaul Walmsley #define M5B_DPLL_DIV_12 (2 << 8) 250d8a94458SPaul Walmsley #define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 251d8a94458SPaul Walmsley M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ 252d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 253d8a94458SPaul Walmsley #define M5B_DPLL_MULT_13 (200 << 12) 254d8a94458SPaul Walmsley #define M5B_DPLL_DIV_13 (12 << 8) 255d8a94458SPaul Walmsley 256d8a94458SPaul Walmsley #define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 257d8a94458SPaul Walmsley M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ 258d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 259d8a94458SPaul Walmsley #define M5B_DPLL_MULT_19 (125 << 12) 260d8a94458SPaul Walmsley #define M5B_DPLL_DIV_19 (31 << 8) 261d8a94458SPaul Walmsley #define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 262d8a94458SPaul Walmsley M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ 263d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 264d8a94458SPaul Walmsley /* 265d8a94458SPaul Walmsley * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz 266d8a94458SPaul Walmsley */ 267d8a94458SPaul Walmsley #define M4_DPLL_MULT_12 (133 << 12) 268d8a94458SPaul Walmsley #define M4_DPLL_DIV_12 (3 << 8) 269d8a94458SPaul Walmsley #define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 270d8a94458SPaul Walmsley M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \ 271d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 272d8a94458SPaul Walmsley 273d8a94458SPaul Walmsley #define M4_DPLL_MULT_13 (399 << 12) 274d8a94458SPaul Walmsley #define M4_DPLL_DIV_13 (12 << 8) 275d8a94458SPaul Walmsley #define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 276d8a94458SPaul Walmsley M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \ 277d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 278d8a94458SPaul Walmsley 279d8a94458SPaul Walmsley #define M4_DPLL_MULT_19 (145 << 12) 280d8a94458SPaul Walmsley #define M4_DPLL_DIV_19 (6 << 8) 281d8a94458SPaul Walmsley #define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 282d8a94458SPaul Walmsley M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \ 283d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 284d8a94458SPaul Walmsley 285d8a94458SPaul Walmsley /* 286d8a94458SPaul Walmsley * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz 287d8a94458SPaul Walmsley */ 288d8a94458SPaul Walmsley #define M3_DPLL_MULT_12 (55 << 12) 289d8a94458SPaul Walmsley #define M3_DPLL_DIV_12 (1 << 8) 290d8a94458SPaul Walmsley #define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 291d8a94458SPaul Walmsley M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ 292d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 293d8a94458SPaul Walmsley #define M3_DPLL_MULT_13 (76 << 12) 294d8a94458SPaul Walmsley #define M3_DPLL_DIV_13 (2 << 8) 295d8a94458SPaul Walmsley #define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 296d8a94458SPaul Walmsley M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ 297d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 298d8a94458SPaul Walmsley #define M3_DPLL_MULT_19 (17 << 12) 299d8a94458SPaul Walmsley #define M3_DPLL_DIV_19 (0 << 8) 300d8a94458SPaul Walmsley #define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 301d8a94458SPaul Walmsley M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ 302d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 303d8a94458SPaul Walmsley 304d8a94458SPaul Walmsley /* 305d8a94458SPaul Walmsley * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz 306d8a94458SPaul Walmsley */ 307d8a94458SPaul Walmsley #define M2_DPLL_MULT_12 (55 << 12) 308d8a94458SPaul Walmsley #define M2_DPLL_DIV_12 (1 << 8) 309d8a94458SPaul Walmsley #define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 310d8a94458SPaul Walmsley M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \ 311d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 312d8a94458SPaul Walmsley 313d8a94458SPaul Walmsley /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, 314d8a94458SPaul Walmsley * relock time issue */ 315d8a94458SPaul Walmsley /* Core frequency changed from 330/165 to 329/164 MHz*/ 316d8a94458SPaul Walmsley #define M2_DPLL_MULT_13 (76 << 12) 317d8a94458SPaul Walmsley #define M2_DPLL_DIV_13 (2 << 8) 318d8a94458SPaul Walmsley #define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 319d8a94458SPaul Walmsley M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \ 320d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 321d8a94458SPaul Walmsley 322d8a94458SPaul Walmsley #define M2_DPLL_MULT_19 (17 << 12) 323d8a94458SPaul Walmsley #define M2_DPLL_DIV_19 (0 << 8) 324d8a94458SPaul Walmsley #define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 325d8a94458SPaul Walmsley M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \ 326d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19_2) 327d8a94458SPaul Walmsley 328d8a94458SPaul Walmsley /* boot (boot) */ 329d8a94458SPaul Walmsley #define MB_DPLL_MULT (1 << 12) 330d8a94458SPaul Walmsley #define MB_DPLL_DIV (0 << 8) 331d8a94458SPaul Walmsley #define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 332d8a94458SPaul Walmsley MB_DPLL_DIV | MB_DPLL_MULT | \ 333d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 334d8a94458SPaul Walmsley 335d8a94458SPaul Walmsley #define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 336d8a94458SPaul Walmsley MB_DPLL_DIV | MB_DPLL_MULT | \ 337d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 338d8a94458SPaul Walmsley 339d8a94458SPaul Walmsley #define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \ 340d8a94458SPaul Walmsley MB_DPLL_DIV | MB_DPLL_MULT | \ 341d8a94458SPaul Walmsley MX_APLLS_CLIKIN_19) 342d8a94458SPaul Walmsley 343d8a94458SPaul Walmsley /* 344d8a94458SPaul Walmsley * 2430 - chassis (sedna) 345d8a94458SPaul Walmsley * 165 (ratio1) same as above #2 346d8a94458SPaul Walmsley * 150 (ratio1) 347d8a94458SPaul Walmsley * 133 (ratio2) same as above #4 348d8a94458SPaul Walmsley * 110 (ratio2) same as above #3 349d8a94458SPaul Walmsley * 104 (ratio2) 350d8a94458SPaul Walmsley * boot (boot) 351d8a94458SPaul Walmsley */ 352d8a94458SPaul Walmsley 353d8a94458SPaul Walmsley /* PRCM I target DPLL = 2*330MHz = 660MHz */ 354d8a94458SPaul Walmsley #define MI_DPLL_MULT_12 (55 << 12) 355d8a94458SPaul Walmsley #define MI_DPLL_DIV_12 (1 << 8) 356d8a94458SPaul Walmsley #define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 357d8a94458SPaul Walmsley MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \ 358d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 359d8a94458SPaul Walmsley 360d8a94458SPaul Walmsley /* 361d8a94458SPaul Walmsley * 2420 Equivalent - mode registers 362d8a94458SPaul Walmsley * PRCM II , target DPLL = 2*300MHz = 600MHz 363d8a94458SPaul Walmsley */ 364d8a94458SPaul Walmsley #define MII_DPLL_MULT_12 (50 << 12) 365d8a94458SPaul Walmsley #define MII_DPLL_DIV_12 (1 << 8) 366d8a94458SPaul Walmsley #define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 367d8a94458SPaul Walmsley MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ 368d8a94458SPaul Walmsley MX_APLLS_CLIKIN_12) 369d8a94458SPaul Walmsley #define MII_DPLL_MULT_13 (300 << 12) 370d8a94458SPaul Walmsley #define MII_DPLL_DIV_13 (12 << 8) 371d8a94458SPaul Walmsley #define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 372d8a94458SPaul Walmsley MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ 373d8a94458SPaul Walmsley MX_APLLS_CLIKIN_13) 374d8a94458SPaul Walmsley 375d8a94458SPaul Walmsley /* PRCM III target DPLL = 2*266 = 532MHz*/ 376d8a94458SPaul Walmsley #define MIII_DPLL_MULT_12 (133 << 12) 377d8a94458SPaul Walmsley #define MIII_DPLL_DIV_12 (5 << 8) 378d8a94458SPaul Walmsley #define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \ 379d8a94458SPaul Walmsley MIII_DPLL_DIV_12 | \ 380d8a94458SPaul Walmsley MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12) 381d8a94458SPaul Walmsley #define MIII_DPLL_MULT_13 (266 << 12) 382d8a94458SPaul Walmsley #define MIII_DPLL_DIV_13 (12 << 8) 383d8a94458SPaul Walmsley #define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \ 384d8a94458SPaul Walmsley MIII_DPLL_DIV_13 | \ 385d8a94458SPaul Walmsley MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13) 386d8a94458SPaul Walmsley 387d8a94458SPaul Walmsley /* PRCM VII (boot bypass) */ 388d8a94458SPaul Walmsley #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL 389d8a94458SPaul Walmsley #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL 390d8a94458SPaul Walmsley 391d8a94458SPaul Walmsley /* High and low operation value */ 392d8a94458SPaul Walmsley #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) 393d8a94458SPaul Walmsley #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) 394d8a94458SPaul Walmsley 395d8a94458SPaul Walmsley /* MPU speed defines */ 396d8a94458SPaul Walmsley #define S12M 12000000 397d8a94458SPaul Walmsley #define S13M 13000000 398d8a94458SPaul Walmsley #define S19M 19200000 399d8a94458SPaul Walmsley #define S26M 26000000 400d8a94458SPaul Walmsley #define S100M 100000000 401d8a94458SPaul Walmsley #define S133M 133000000 402d8a94458SPaul Walmsley #define S150M 150000000 403d8a94458SPaul Walmsley #define S164M 164000000 404d8a94458SPaul Walmsley #define S165M 165000000 405d8a94458SPaul Walmsley #define S199M 199000000 406d8a94458SPaul Walmsley #define S200M 200000000 407d8a94458SPaul Walmsley #define S266M 266000000 408d8a94458SPaul Walmsley #define S300M 300000000 409d8a94458SPaul Walmsley #define S329M 329000000 410d8a94458SPaul Walmsley #define S330M 330000000 411d8a94458SPaul Walmsley #define S399M 399000000 412d8a94458SPaul Walmsley #define S400M 400000000 413d8a94458SPaul Walmsley #define S532M 532000000 414d8a94458SPaul Walmsley #define S600M 600000000 415d8a94458SPaul Walmsley #define S658M 658000000 416d8a94458SPaul Walmsley #define S660M 660000000 417d8a94458SPaul Walmsley #define S798M 798000000 418d8a94458SPaul Walmsley 419d8a94458SPaul Walmsley 420d8a94458SPaul Walmsley extern const struct prcm_config omap2420_rate_table[]; 42156213ca4STony Lindgren 42259b479e0STony Lindgren #ifdef CONFIG_SOC_OMAP2430 423d8a94458SPaul Walmsley extern const struct prcm_config omap2430_rate_table[]; 42456213ca4STony Lindgren #else 42556213ca4STony Lindgren #define omap2430_rate_table NULL 42656213ca4STony Lindgren #endif 427d8a94458SPaul Walmsley extern const struct prcm_config *rate_table; 428d8a94458SPaul Walmsley extern const struct prcm_config *curr_prcm_set; 429d8a94458SPaul Walmsley 430d8a94458SPaul Walmsley #endif 431