Lines Matching +full:2 +full:mhz

22 	SERDES_REFCLK_100,	/* refclk 100Mhz */
23 	SERDES_REFCLK_122_88,	/* refclk 122.88Mhz */
24 	SERDES_REFCLK_125,	/* refclk 125Mhz */
25 	SERDES_REFCLK_156_25,	/* refclk 156.25Mhz */
30  * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
32 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
42  * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
44 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
54  * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
57 static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
63  * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
65 static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
71  * Refclk1 : 100MHz Refclk2 : 156.25MHz
73 static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
79  * Refclk1 : 125MHz Refclk2 : 156.25MHz
81 static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
87  * Refclk1 : 156.25MHz Refclk2 : 100MHz
89 static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
95  * Refclk1 : 156.25MHz Refclk2 : 125MHz
97 static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},