Lines Matching +full:2 +full:mhz
27 u32 reserved5[2];
41 u32 sdmmc_con[2];
42 u32 sdio_con[2];
43 u32 emmc_con[2];
44 u32 sdmmc_ext_con[2];
47 #define MHz 1000000 macro
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
54 #define CLK_CORE_HZ (600 * MHz)
55 #define ACLKM_CORE_HZ (300 * MHz)
56 #define PCLK_DBG_HZ (300 * MHz)
62 #define PWM_CLOCK_HZ (74 * MHz)