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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
64 - 1000base-x
91 Indicate the Ethernet core is configured to support both 1000BaseX and
121 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
/openbmc/linux/include/uapi/linux/
H A Dmii.h23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
75 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
77 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
79 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
81 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
98 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
100 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
102 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
[all …]
/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h266 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
272 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
281 #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
284 #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
341 #define DELAY_OF_ONE_MILLISEC 1000
343 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
391 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
427 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
H A Dxilinx_axienet_main.c2024 dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n"); in axienet_probe()
2140 dev_err(&pdev->dev, "pcs-handle (preferred) or phy-handle required for 1000BaseX/SGMII\n"); in axienet_probe()
/openbmc/linux/include/linux/
H A Dphylink.h29 * 1000base-X with autoneg off
144 /* 1000base-X is designed for use media-side for Fibre in phylink_pcs_neg_mode()
271 * technology to another, so, eg, don't clear 1000BaseX just
272 * because the MAC is unable to BaseX mode. This is more about
378 * 1000base-X or Cisco SGMII mode depending on the @state->interface
507 * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
597 * For 1000BASE-X, the advertisement should be programmed into the PCS.
610 * pcs_an_restart() - restart 802.3z BaseX autonegotiation
H A Dphy.h116 * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
117 * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX
118 * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX
127 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
266 return "1000base-x"; in phy_modes()
268 return "1000base-kx"; in phy_modes()
551 * @is_gigabit_capable: Set to true if PHY supports 1000Mbps
/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpmac.h49 * @DPMAC_ETH_IF_1000BASEX: 1000BASEX interface
/openbmc/linux/drivers/net/phy/
H A Dmxl-gpy.c152 {4, -25761, 1000, 1},
153 {3, 97332, 1000, 1},
154 {2, -191650, 1000, 1},
155 {1, 307620, 1000, 1},
520 /* Automatically switch SERDES interface between SGMII and 2500-BaseX in gpy_update_interface()
521 * according to speed. Disable ANEG in 2500-BaseX mode. in gpy_update_interface()
541 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed in gpy_update_interface()
542 * if ANEG is disabled (in 2500-BaseX mode). in gpy_update_interface()
H A Dsfp-bus.c195 phylink_set(modes, 1000baseX_Full); in sfp_parse_support()
199 phylink_set(modes, 1000baseT_Half); in sfp_parse_support()
200 phylink_set(modes, 1000baseT_Full); in sfp_parse_support()
205 /* 1000Base-PX or 1000Base-BX10 */ in sfp_parse_support()
208 phylink_set(modes, 1000baseX_Full); in sfp_parse_support()
236 phylink_set(modes, 1000baseX_Full); in sfp_parse_support()
304 /* For fibre channel SFP, derive possible BaseX modes */ in sfp_parse_support()
313 phylink_set(modes, 1000baseX_Full); in sfp_parse_support()
320 * 1310nm/1550nm) are not 1000BASE-BX compliant due to the differing in sfp_parse_support()
329 phylink_set(modes, 1000baseX_Full); in sfp_parse_support()
[all …]
H A Dmarvell.c188 /* RGMII to 1000BASE-X */
684 /* If not using SGMII or copper 1000BaseX modes, use normal process. in m88e1111_config_aneg()
769 * LED[0] .. 1000Mbps Link in marvell_config_led()
922 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */ in m88e1111_config_init_1000basex()
974 * 1000BaseX) to SGMII, the state of the support bits may have in m88e1111_config_init()
1289 /* Enable 1000 Mbit */ in m88e1118_config_init()
1332 /* Enable 1000 Mbit */ in m88e1149_config_init()
1618 /* The fiber link is only 1000M capable */ in marvell_read_status_page_an()
2029 msleep(1000); in m88e1510_loopback()
2077 return 1000 * amplitude / 128; in marvell_vct5_amplitude()
[all …]
H A Dmarvell10g.c108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
213 *value = ((temp & 0xff) - 75) * 1000; in mv3310_hwmon_read()
436 *edpd = 1000; in mv3310_get_edpd()
454 case 1000: in mv3310_set_edpd()
897 /* Clause 45 has no standardized support for 1000BaseT, therefore in mv3310_config_aneg()
945 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / in mv3310_update_interface()
H A Dat803x.c694 phylink_set(phy_support, 1000baseX_Full); in at803x_sfp_insert()
695 phylink_set(phy_support, 1000baseT_Full); in at803x_sfp_insert()
714 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes in at803x_sfp_insert()
717 * interface do default to and function in 1000Base-X mode, so just in at803x_sfp_insert()
722 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); in at803x_sfp_insert()
846 /* Only AR8031/8033 support 1000Base-X for SFP modules */ in at803x_parse_dt()
924 * when not operating in 1000BaseX mode. in at803x_get_features()
1770 /* Active adc&vga on 802.3az for the link 1000M and 100M */ in qca808x_config_init()
1776 /* Adjust the threshold on 802.3az for the link 1000M */ in qca808x_config_init()
1930 * 3. for PHY working in 1000BaseT. in qca808x_cable_test_start()
[all …]
H A Dmotorcomm.c122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
1228 /* only support 1000baseX Full */ in yt8521_adjust_status()
1292 /* When PHY is in fiber mode, speed transferred from 1000Mbps to in yt8521_read_status_paged()
1452 usleep_range(1000, 1100); in yt8521_modify_bmcr_paged()
1671 if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted")) in yt8531_link_change_notify()
1826 usleep_range(1000, 1100); in yt8521_fiber_config_aneg()
1926 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a in ytphy_utp_config_advert()
H A Dphylink.c903 phylink_set(pl->supported, 1000baseT_Half); in phylink_parse_mode()
904 phylink_set(pl->supported, 1000baseT_Full); in phylink_parse_mode()
908 phylink_set(pl->supported, 1000baseX_Full); in phylink_parse_mode()
931 phylink_set(pl->supported, 1000baseT_Half); in phylink_parse_mode()
932 phylink_set(pl->supported, 1000baseT_Full); in phylink_parse_mode()
933 phylink_set(pl->supported, 1000baseX_Full); in phylink_parse_mode()
934 phylink_set(pl->supported, 1000baseKX_Full); in phylink_parse_mode()
1712 * When using fixed-link mode, or in-band mode with 1000base-X or 2500base-X,
2398 * pause modes when in 1000base-X mode with a PHY, but in in phylink_ethtool_ksettings_set()
2503 /* The interface changed, e.g. 1000base-X <-> 2500base-X */ in phylink_ethtool_ksettings_set()
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_port.c18 #define SPX5_WAIT_US 1000
158 /* Get link status of 1000Base-X/in-band and SFI ports.
369 spd_prm = spd == SPEED_10 ? 1000 : spd == SPEED_100 ? 100 : 10; in sparx5_port_disable()
506 tmp1 = 1000 * mac_width / fifo_width; in sparx5_port_fifo_sz()
507 tmp2 = 3000 + ((12000 + 2 * taxi_dist[portno] * 1000) in sparx5_port_fifo_sz()
509 tmp3 = tmp1 * tmp2 / 1000; in sparx5_port_fifo_sz()
510 return (tmp3 + 2000 + 999) / 1000 + addition; in sparx5_port_fifo_sz()
749 /* Choose SGMII or 1000BaseX/2500BaseX PCS mode */ in sparx5_port_pcs_low_set()
/openbmc/linux/drivers/net/pcs/
H A Dpcs-lynx.c258 * The speed is configured at 1000 in the IF_MODE because the clock frequency
272 dev_err(&pcs->dev, "AN not supported for 2500BaseX\n"); in lynx_pcs_link_up_2500basex()
/openbmc/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_main.c27 #define PRESTERA_STATS_DELAY_MS 1000
350 /* TODO: add 1000basex AN restart support in prestera_pcs_an_restart()
351 * (Currently FW has no support for 1000baseX AN restart, but it will in the future, in prestera_pcs_an_restart()
/openbmc/linux/drivers/net/ethernet/altera/
H A Daltera_tse.h210 /* only if 100/1000 BaseX PCS, reserved otherwise */
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c643 * When a SERDES port is operating in 1000BASE-X or SGMII mode link may not
703 * We can get around this by configuring the PCS mode to 1000base-x and then
708 * PCS mode to 1000base-x and frequency to 3.125 GHz from 1.25 GHz) and then
709 * configure to sgmii or 1000base-x, the device thinks that it already has
750 "failed to %s 2500basex fix: %pe\n", in mv88e6393x_sgmii_apply_2500basex_an()
H A Dchip.c109 usleep_range(1000, 2000); in mv88e6xxx_wait_mask()
766 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is in mv88e6390x_phylink_get_caps()
767 * configured for 1000BASE-X, SGMII or 2500BASE-X. in mv88e6390x_phylink_get_caps()
768 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is in mv88e6390x_phylink_get_caps()
769 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. in mv88e6390x_phylink_get_caps()
771 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is in mv88e6390x_phylink_get_caps()
772 * configured for 1000BASE-X, SGMII or 2500BASE-X. in mv88e6390x_phylink_get_caps()
773 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is in mv88e6390x_phylink_get_caps()
774 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. in mv88e6390x_phylink_get_caps()
776 * For now, be permissive (as the old code was) and allow 1000BASE-X in mv88e6390x_phylink_get_caps()
[all …]
/openbmc/u-boot/drivers/net/
H A Dxilinx_axi_emac.c24 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
321 case 1000: in setup_phy()
378 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads in axi_ethernet_init()
/openbmc/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c628 if (!XGBE_ADV(lks, 1000baseKX_Full) && in xgbe_an73_incompat_link()
1005 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); in xgbe_an37_init()
1031 if (XGBE_ADV(&lks, 1000baseKX_Full) || in xgbe_an73_init()
1601 else if (XGBE_ADV(lks, 1000baseKX_Full)) in xgbe_phy_best_advertised_speed()
1603 else if (XGBE_ADV(lks, 1000baseT_Full)) in xgbe_phy_best_advertised_speed()
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c1155 usleep_range(1000, 2000); in sparx5_sd25g28_reset()
1555 usleep_range(1000, 2000); in sparx5_sd25g28_apply_params()
1630 usleep_range(1000, 2000); in sparx5_sd10g28_reset()
2209 /* The same Serdes mode is used for both SGMII and 1000BaseX */ in sparx5_serdes_get_serdesmode()
/openbmc/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ethtool.c500 1000baseT_Full); in i40e_phy_type_to_ethtool()
503 1000baseT_Full); in i40e_phy_type_to_ethtool()
565 1000baseT_Full); in i40e_phy_type_to_ethtool()
568 1000baseT_Full); in i40e_phy_type_to_ethtool()
613 1000baseKX_Full); in i40e_phy_type_to_ethtool()
616 1000baseKX_Full); in i40e_phy_type_to_ethtool()
694 1000baseX_Full); in i40e_phy_type_to_ethtool()
697 1000baseX_Full); in i40e_phy_type_to_ethtool()
830 1000baseX_Full); in i40e_get_settings_link_up()
832 1000baseX_Full); in i40e_get_settings_link_up()
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1771 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1840 if (state->speed == 1000) in mvpp2_port_loopback_set()
6223 * When <PortType> = 1 (1000BASE-X) this field must be set to 1. in mvpp2_gmac_pcs_validate()
6405 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can in mvpp2_gmac_config()
6407 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 in mvpp2_gmac_config()
6998 /* No COMPHY, we can switch between 1000BASE-X and SGMII in mvpp2_port_probe()

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