12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2fad09c73SVivien Didelot /*
3fad09c73SVivien Didelot * Marvell 88e6xxx Ethernet switch single-chip support
4fad09c73SVivien Didelot *
5fad09c73SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor
6fad09c73SVivien Didelot *
7fad09c73SVivien Didelot * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8fad09c73SVivien Didelot *
94333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
104333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11fad09c73SVivien Didelot */
12fad09c73SVivien Didelot
1319fb7f69SVivien Didelot #include <linux/bitfield.h>
14fad09c73SVivien Didelot #include <linux/delay.h>
155bded825SVladimir Oltean #include <linux/dsa/mv88e6xxx.h>
16fad09c73SVivien Didelot #include <linux/etherdevice.h>
17fad09c73SVivien Didelot #include <linux/ethtool.h>
18fad09c73SVivien Didelot #include <linux/if_bridge.h>
19dc30c35bSAndrew Lunn #include <linux/interrupt.h>
20dc30c35bSAndrew Lunn #include <linux/irq.h>
21dc30c35bSAndrew Lunn #include <linux/irqdomain.h>
22fad09c73SVivien Didelot #include <linux/jiffies.h>
23fad09c73SVivien Didelot #include <linux/list.h>
24fad09c73SVivien Didelot #include <linux/mdio.h>
25fad09c73SVivien Didelot #include <linux/module.h>
26f44a9010SRob Herring #include <linux/of.h>
27dc30c35bSAndrew Lunn #include <linux/of_irq.h>
28fad09c73SVivien Didelot #include <linux/of_mdio.h>
29877b7cb0SAndrew Lunn #include <linux/platform_data/mv88e6xxx.h>
30fad09c73SVivien Didelot #include <linux/netdevice.h>
31fad09c73SVivien Didelot #include <linux/gpio/consumer.h>
32c9a2356fSRussell King #include <linux/phylink.h>
33fad09c73SVivien Didelot #include <net/dsa.h>
34ec561276SVivien Didelot
354d5f2ba7SVivien Didelot #include "chip.h"
369dd43aa2SAndrew Lunn #include "devlink.h"
37a935c052SVivien Didelot #include "global1.h"
38ec561276SVivien Didelot #include "global2.h"
39c6fe0ad2SBrandon Streiff #include "hwtstamp.h"
4010fa5bfcSAndrew Lunn #include "phy.h"
4118abed21SVivien Didelot #include "port.h"
422fa8d3afSBrandon Streiff #include "ptp.h"
436d91782fSAndrew Lunn #include "serdes.h"
44e7ba0fadSVivien Didelot #include "smi.h"
45fad09c73SVivien Didelot
assert_reg_lock(struct mv88e6xxx_chip * chip)46fad09c73SVivien Didelot static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47fad09c73SVivien Didelot {
48fad09c73SVivien Didelot if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49fad09c73SVivien Didelot dev_err(chip->dev, "Switch registers lock not held!\n");
50fad09c73SVivien Didelot dump_stack();
51fad09c73SVivien Didelot }
52fad09c73SVivien Didelot }
53fad09c73SVivien Didelot
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)54ec561276SVivien Didelot int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55fad09c73SVivien Didelot {
56fad09c73SVivien Didelot int err;
57fad09c73SVivien Didelot
58fad09c73SVivien Didelot assert_reg_lock(chip);
59fad09c73SVivien Didelot
60fad09c73SVivien Didelot err = mv88e6xxx_smi_read(chip, addr, reg, val);
61fad09c73SVivien Didelot if (err)
62fad09c73SVivien Didelot return err;
63fad09c73SVivien Didelot
64fad09c73SVivien Didelot dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65fad09c73SVivien Didelot addr, reg, *val);
66fad09c73SVivien Didelot
67fad09c73SVivien Didelot return 0;
68fad09c73SVivien Didelot }
69fad09c73SVivien Didelot
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)70ec561276SVivien Didelot int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71fad09c73SVivien Didelot {
72fad09c73SVivien Didelot int err;
73fad09c73SVivien Didelot
74fad09c73SVivien Didelot assert_reg_lock(chip);
75fad09c73SVivien Didelot
76fad09c73SVivien Didelot err = mv88e6xxx_smi_write(chip, addr, reg, val);
77fad09c73SVivien Didelot if (err)
78fad09c73SVivien Didelot return err;
79fad09c73SVivien Didelot
80fad09c73SVivien Didelot dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81fad09c73SVivien Didelot addr, reg, val);
82fad09c73SVivien Didelot
83fad09c73SVivien Didelot return 0;
84fad09c73SVivien Didelot }
85fad09c73SVivien Didelot
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)86683f2244SVivien Didelot int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87683f2244SVivien Didelot u16 mask, u16 val)
88683f2244SVivien Didelot {
8935da1dfdSTobias Waldekranz const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90683f2244SVivien Didelot u16 data;
91683f2244SVivien Didelot int err;
92683f2244SVivien Didelot int i;
93683f2244SVivien Didelot
9435da1dfdSTobias Waldekranz /* There's no bus specific operation to wait for a mask. Even
9535da1dfdSTobias Waldekranz * if the initial poll takes longer than 50ms, always do at
9635da1dfdSTobias Waldekranz * least one more attempt.
9735da1dfdSTobias Waldekranz */
9835da1dfdSTobias Waldekranz for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99683f2244SVivien Didelot err = mv88e6xxx_read(chip, addr, reg, &data);
100683f2244SVivien Didelot if (err)
101683f2244SVivien Didelot return err;
102683f2244SVivien Didelot
103683f2244SVivien Didelot if ((data & mask) == val)
104683f2244SVivien Didelot return 0;
105683f2244SVivien Didelot
10635da1dfdSTobias Waldekranz if (i < 2)
10735da1dfdSTobias Waldekranz cpu_relax();
10835da1dfdSTobias Waldekranz else
109683f2244SVivien Didelot usleep_range(1000, 2000);
110683f2244SVivien Didelot }
111683f2244SVivien Didelot
11295ce158bSLinus Walleij err = mv88e6xxx_read(chip, addr, reg, &data);
11395ce158bSLinus Walleij if (err)
11495ce158bSLinus Walleij return err;
11595ce158bSLinus Walleij
11695ce158bSLinus Walleij if ((data & mask) == val)
11795ce158bSLinus Walleij return 0;
11895ce158bSLinus Walleij
119683f2244SVivien Didelot dev_err(chip->dev, "Timeout while waiting for switch\n");
120683f2244SVivien Didelot return -ETIMEDOUT;
121683f2244SVivien Didelot }
122683f2244SVivien Didelot
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)12319fb7f69SVivien Didelot int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
12419fb7f69SVivien Didelot int bit, int val)
12519fb7f69SVivien Didelot {
12619fb7f69SVivien Didelot return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
12719fb7f69SVivien Didelot val ? BIT(bit) : 0x0000);
12819fb7f69SVivien Didelot }
12919fb7f69SVivien Didelot
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)13010fa5bfcSAndrew Lunn struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131a3c53be5SAndrew Lunn {
132a3c53be5SAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus;
133a3c53be5SAndrew Lunn
134a3c53be5SAndrew Lunn mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
135a3c53be5SAndrew Lunn list);
136a3c53be5SAndrew Lunn if (!mdio_bus)
137a3c53be5SAndrew Lunn return NULL;
138a3c53be5SAndrew Lunn
139a3c53be5SAndrew Lunn return mdio_bus->bus;
140a3c53be5SAndrew Lunn }
141a3c53be5SAndrew Lunn
mv88e6xxx_g1_irq_mask(struct irq_data * d)142dc30c35bSAndrew Lunn static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143dc30c35bSAndrew Lunn {
144dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145dc30c35bSAndrew Lunn unsigned int n = d->hwirq;
146dc30c35bSAndrew Lunn
147dc30c35bSAndrew Lunn chip->g1_irq.masked |= (1 << n);
148dc30c35bSAndrew Lunn }
149dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_unmask(struct irq_data * d)150dc30c35bSAndrew Lunn static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151dc30c35bSAndrew Lunn {
152dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153dc30c35bSAndrew Lunn unsigned int n = d->hwirq;
154dc30c35bSAndrew Lunn
155dc30c35bSAndrew Lunn chip->g1_irq.masked &= ~(1 << n);
156dc30c35bSAndrew Lunn }
157dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)158294d711eSAndrew Lunn static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159dc30c35bSAndrew Lunn {
160dc30c35bSAndrew Lunn unsigned int nhandled = 0;
161dc30c35bSAndrew Lunn unsigned int sub_irq;
162dc30c35bSAndrew Lunn unsigned int n;
163dc30c35bSAndrew Lunn u16 reg;
1647c0db24cSJohn David Anglin u16 ctl1;
165dc30c35bSAndrew Lunn int err;
166dc30c35bSAndrew Lunn
167c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
16882466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
170dc30c35bSAndrew Lunn
171dc30c35bSAndrew Lunn if (err)
172dc30c35bSAndrew Lunn goto out;
173dc30c35bSAndrew Lunn
1747c0db24cSJohn David Anglin do {
175dc30c35bSAndrew Lunn for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176dc30c35bSAndrew Lunn if (reg & (1 << n)) {
1777c0db24cSJohn David Anglin sub_irq = irq_find_mapping(chip->g1_irq.domain,
1787c0db24cSJohn David Anglin n);
179dc30c35bSAndrew Lunn handle_nested_irq(sub_irq);
180dc30c35bSAndrew Lunn ++nhandled;
181dc30c35bSAndrew Lunn }
182dc30c35bSAndrew Lunn }
1837c0db24cSJohn David Anglin
184c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1857c0db24cSJohn David Anglin err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
1867c0db24cSJohn David Anglin if (err)
1877c0db24cSJohn David Anglin goto unlock;
1887c0db24cSJohn David Anglin err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
1897c0db24cSJohn David Anglin unlock:
190c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1917c0db24cSJohn David Anglin if (err)
1927c0db24cSJohn David Anglin goto out;
1937c0db24cSJohn David Anglin ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
1947c0db24cSJohn David Anglin } while (reg & ctl1);
1957c0db24cSJohn David Anglin
196dc30c35bSAndrew Lunn out:
197dc30c35bSAndrew Lunn return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198dc30c35bSAndrew Lunn }
199dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)200294d711eSAndrew Lunn static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201294d711eSAndrew Lunn {
202294d711eSAndrew Lunn struct mv88e6xxx_chip *chip = dev_id;
203294d711eSAndrew Lunn
204294d711eSAndrew Lunn return mv88e6xxx_g1_irq_thread_work(chip);
205294d711eSAndrew Lunn }
206294d711eSAndrew Lunn
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)207dc30c35bSAndrew Lunn static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208dc30c35bSAndrew Lunn {
209dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210dc30c35bSAndrew Lunn
211c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
212dc30c35bSAndrew Lunn }
213dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)214dc30c35bSAndrew Lunn static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215dc30c35bSAndrew Lunn {
216dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217dc30c35bSAndrew Lunn u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218dc30c35bSAndrew Lunn u16 reg;
219dc30c35bSAndrew Lunn int err;
220dc30c35bSAndrew Lunn
221d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222dc30c35bSAndrew Lunn if (err)
223dc30c35bSAndrew Lunn goto out;
224dc30c35bSAndrew Lunn
225dc30c35bSAndrew Lunn reg &= ~mask;
226dc30c35bSAndrew Lunn reg |= (~chip->g1_irq.masked & mask);
227dc30c35bSAndrew Lunn
228d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229dc30c35bSAndrew Lunn if (err)
230dc30c35bSAndrew Lunn goto out;
231dc30c35bSAndrew Lunn
232dc30c35bSAndrew Lunn out:
233c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
234dc30c35bSAndrew Lunn }
235dc30c35bSAndrew Lunn
2366eb15e21SBhumika Goyal static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237dc30c35bSAndrew Lunn .name = "mv88e6xxx-g1",
238dc30c35bSAndrew Lunn .irq_mask = mv88e6xxx_g1_irq_mask,
239dc30c35bSAndrew Lunn .irq_unmask = mv88e6xxx_g1_irq_unmask,
240dc30c35bSAndrew Lunn .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241dc30c35bSAndrew Lunn .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242dc30c35bSAndrew Lunn };
243dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)244dc30c35bSAndrew Lunn static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245dc30c35bSAndrew Lunn unsigned int irq,
246dc30c35bSAndrew Lunn irq_hw_number_t hwirq)
247dc30c35bSAndrew Lunn {
248dc30c35bSAndrew Lunn struct mv88e6xxx_chip *chip = d->host_data;
249dc30c35bSAndrew Lunn
250dc30c35bSAndrew Lunn irq_set_chip_data(irq, d->host_data);
251dc30c35bSAndrew Lunn irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252dc30c35bSAndrew Lunn irq_set_noprobe(irq);
253dc30c35bSAndrew Lunn
254dc30c35bSAndrew Lunn return 0;
255dc30c35bSAndrew Lunn }
256dc30c35bSAndrew Lunn
257dc30c35bSAndrew Lunn static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258dc30c35bSAndrew Lunn .map = mv88e6xxx_g1_irq_domain_map,
259dc30c35bSAndrew Lunn .xlate = irq_domain_xlate_twocell,
260dc30c35bSAndrew Lunn };
261dc30c35bSAndrew Lunn
2623d82475aSUwe Kleine-König /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)263294d711eSAndrew Lunn static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264dc30c35bSAndrew Lunn {
265dc30c35bSAndrew Lunn int irq, virq;
2663460a577SAndrew Lunn u16 mask;
2673460a577SAndrew Lunn
268d77f4321SVivien Didelot mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
2693d5fdba1SAndrew Lunn mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270d77f4321SVivien Didelot mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
2713460a577SAndrew Lunn
2725edef2f2SAndreas Färber for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273a3db3d3aSAndrew Lunn virq = irq_find_mapping(chip->g1_irq.domain, irq);
274dc30c35bSAndrew Lunn irq_dispose_mapping(virq);
275dc30c35bSAndrew Lunn }
276dc30c35bSAndrew Lunn
277a3db3d3aSAndrew Lunn irq_domain_remove(chip->g1_irq.domain);
278dc30c35bSAndrew Lunn }
279dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)280294d711eSAndrew Lunn static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281294d711eSAndrew Lunn {
2823d82475aSUwe Kleine-König /*
2833d82475aSUwe Kleine-König * free_irq must be called without reg_lock taken because the irq
2843d82475aSUwe Kleine-König * handler takes this lock, too.
2853d82475aSUwe Kleine-König */
286294d711eSAndrew Lunn free_irq(chip->irq, chip);
2873d82475aSUwe Kleine-König
288c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2893d82475aSUwe Kleine-König mv88e6xxx_g1_irq_free_common(chip);
290c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
291294d711eSAndrew Lunn }
292294d711eSAndrew Lunn
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)293294d711eSAndrew Lunn static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294dc30c35bSAndrew Lunn {
2953dd0ef05SAndrew Lunn int err, irq, virq;
2963dd0ef05SAndrew Lunn u16 reg, mask;
297dc30c35bSAndrew Lunn
298dc30c35bSAndrew Lunn chip->g1_irq.nirqs = chip->info->g1_irqs;
299dc30c35bSAndrew Lunn chip->g1_irq.domain = irq_domain_add_simple(
300dc30c35bSAndrew Lunn NULL, chip->g1_irq.nirqs, 0,
301dc30c35bSAndrew Lunn &mv88e6xxx_g1_irq_domain_ops, chip);
302dc30c35bSAndrew Lunn if (!chip->g1_irq.domain)
303dc30c35bSAndrew Lunn return -ENOMEM;
304dc30c35bSAndrew Lunn
305dc30c35bSAndrew Lunn for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306dc30c35bSAndrew Lunn irq_create_mapping(chip->g1_irq.domain, irq);
307dc30c35bSAndrew Lunn
308dc30c35bSAndrew Lunn chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309dc30c35bSAndrew Lunn chip->g1_irq.masked = ~0;
310dc30c35bSAndrew Lunn
311d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312dc30c35bSAndrew Lunn if (err)
3133dd0ef05SAndrew Lunn goto out_mapping;
314dc30c35bSAndrew Lunn
3153dd0ef05SAndrew Lunn mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316dc30c35bSAndrew Lunn
317d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318dc30c35bSAndrew Lunn if (err)
3193dd0ef05SAndrew Lunn goto out_disable;
320dc30c35bSAndrew Lunn
321dc30c35bSAndrew Lunn /* Reading the interrupt status clears (most of) them */
32282466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323dc30c35bSAndrew Lunn if (err)
3243dd0ef05SAndrew Lunn goto out_disable;
325dc30c35bSAndrew Lunn
326dc30c35bSAndrew Lunn return 0;
327dc30c35bSAndrew Lunn
3283dd0ef05SAndrew Lunn out_disable:
3293d5fdba1SAndrew Lunn mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330d77f4321SVivien Didelot mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3313dd0ef05SAndrew Lunn
3323dd0ef05SAndrew Lunn out_mapping:
3333dd0ef05SAndrew Lunn for (irq = 0; irq < 16; irq++) {
3343dd0ef05SAndrew Lunn virq = irq_find_mapping(chip->g1_irq.domain, irq);
3353dd0ef05SAndrew Lunn irq_dispose_mapping(virq);
3363dd0ef05SAndrew Lunn }
3373dd0ef05SAndrew Lunn
3383dd0ef05SAndrew Lunn irq_domain_remove(chip->g1_irq.domain);
339dc30c35bSAndrew Lunn
340dc30c35bSAndrew Lunn return err;
341dc30c35bSAndrew Lunn }
342dc30c35bSAndrew Lunn
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)343294d711eSAndrew Lunn static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344294d711eSAndrew Lunn {
345f6d9758bSAndrew Lunn static struct lock_class_key lock_key;
346f6d9758bSAndrew Lunn static struct lock_class_key request_key;
347294d711eSAndrew Lunn int err;
348294d711eSAndrew Lunn
349294d711eSAndrew Lunn err = mv88e6xxx_g1_irq_setup_common(chip);
350294d711eSAndrew Lunn if (err)
351294d711eSAndrew Lunn return err;
352294d711eSAndrew Lunn
353f6d9758bSAndrew Lunn /* These lock classes tells lockdep that global 1 irqs are in
354f6d9758bSAndrew Lunn * a different category than their parent GPIO, so it won't
355f6d9758bSAndrew Lunn * report false recursion.
356f6d9758bSAndrew Lunn */
357f6d9758bSAndrew Lunn irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358f6d9758bSAndrew Lunn
3593095383aSAndrew Lunn snprintf(chip->irq_name, sizeof(chip->irq_name),
3603095383aSAndrew Lunn "mv88e6xxx-%s", dev_name(chip->dev));
3613095383aSAndrew Lunn
362c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
363294d711eSAndrew Lunn err = request_threaded_irq(chip->irq, NULL,
364294d711eSAndrew Lunn mv88e6xxx_g1_irq_thread_fn,
3650340376eSMarek Behún IRQF_ONESHOT | IRQF_SHARED,
3663095383aSAndrew Lunn chip->irq_name, chip);
367c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
368294d711eSAndrew Lunn if (err)
369294d711eSAndrew Lunn mv88e6xxx_g1_irq_free_common(chip);
370294d711eSAndrew Lunn
371294d711eSAndrew Lunn return err;
372294d711eSAndrew Lunn }
373294d711eSAndrew Lunn
mv88e6xxx_irq_poll(struct kthread_work * work)374294d711eSAndrew Lunn static void mv88e6xxx_irq_poll(struct kthread_work *work)
375294d711eSAndrew Lunn {
376294d711eSAndrew Lunn struct mv88e6xxx_chip *chip = container_of(work,
377294d711eSAndrew Lunn struct mv88e6xxx_chip,
378294d711eSAndrew Lunn irq_poll_work.work);
379294d711eSAndrew Lunn mv88e6xxx_g1_irq_thread_work(chip);
380294d711eSAndrew Lunn
381294d711eSAndrew Lunn kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382294d711eSAndrew Lunn msecs_to_jiffies(100));
383294d711eSAndrew Lunn }
384294d711eSAndrew Lunn
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)385294d711eSAndrew Lunn static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386294d711eSAndrew Lunn {
387294d711eSAndrew Lunn int err;
388294d711eSAndrew Lunn
389294d711eSAndrew Lunn err = mv88e6xxx_g1_irq_setup_common(chip);
390294d711eSAndrew Lunn if (err)
391294d711eSAndrew Lunn return err;
392294d711eSAndrew Lunn
393294d711eSAndrew Lunn kthread_init_delayed_work(&chip->irq_poll_work,
394294d711eSAndrew Lunn mv88e6xxx_irq_poll);
395294d711eSAndrew Lunn
3963f8b8696SFlorian Fainelli chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397294d711eSAndrew Lunn if (IS_ERR(chip->kworker))
398294d711eSAndrew Lunn return PTR_ERR(chip->kworker);
399294d711eSAndrew Lunn
400294d711eSAndrew Lunn kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401294d711eSAndrew Lunn msecs_to_jiffies(100));
402294d711eSAndrew Lunn
403294d711eSAndrew Lunn return 0;
404294d711eSAndrew Lunn }
405294d711eSAndrew Lunn
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)406294d711eSAndrew Lunn static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407294d711eSAndrew Lunn {
408294d711eSAndrew Lunn kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409294d711eSAndrew Lunn kthread_destroy_worker(chip->kworker);
4103d82475aSUwe Kleine-König
411c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
4123d82475aSUwe Kleine-König mv88e6xxx_g1_irq_free_common(chip);
413c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
414294d711eSAndrew Lunn }
415294d711eSAndrew Lunn
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)41664d47d50SRussell King static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
41764d47d50SRussell King int port, phy_interface_t interface)
41864d47d50SRussell King {
41964d47d50SRussell King int err;
42064d47d50SRussell King
42164d47d50SRussell King if (chip->info->ops->port_set_rgmii_delay) {
42264d47d50SRussell King err = chip->info->ops->port_set_rgmii_delay(chip, port,
42364d47d50SRussell King interface);
42464d47d50SRussell King if (err && err != -EOPNOTSUPP)
42564d47d50SRussell King return err;
42664d47d50SRussell King }
42764d47d50SRussell King
42864d47d50SRussell King if (chip->info->ops->port_set_cmode) {
42964d47d50SRussell King err = chip->info->ops->port_set_cmode(chip, port,
43064d47d50SRussell King interface);
43164d47d50SRussell King if (err && err != -EOPNOTSUPP)
43264d47d50SRussell King return err;
43364d47d50SRussell King }
43464d47d50SRussell King
43564d47d50SRussell King return 0;
43664d47d50SRussell King }
43764d47d50SRussell King
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)438a5a6858bSRussell King static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439a5a6858bSRussell King int link, int speed, int duplex, int pause,
440d78343d2SVivien Didelot phy_interface_t mode)
441d78343d2SVivien Didelot {
442d78343d2SVivien Didelot int err;
443d78343d2SVivien Didelot
444d78343d2SVivien Didelot if (!chip->info->ops->port_set_link)
445d78343d2SVivien Didelot return 0;
446d78343d2SVivien Didelot
447d78343d2SVivien Didelot /* Port's MAC control must not be changed unless the link is down */
44843c8e0aeSHubert Feurstein err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449d78343d2SVivien Didelot if (err)
450d78343d2SVivien Didelot return err;
451d78343d2SVivien Didelot
452f365c6f7SRussell King if (chip->info->ops->port_set_speed_duplex) {
453f365c6f7SRussell King err = chip->info->ops->port_set_speed_duplex(chip, port,
454f365c6f7SRussell King speed, duplex);
455d78343d2SVivien Didelot if (err && err != -EOPNOTSUPP)
456d78343d2SVivien Didelot goto restore_link;
457d78343d2SVivien Didelot }
458d78343d2SVivien Didelot
45954186b91SAndrew Lunn if (chip->info->ops->port_set_pause) {
46054186b91SAndrew Lunn err = chip->info->ops->port_set_pause(chip, port, pause);
46154186b91SAndrew Lunn if (err)
46254186b91SAndrew Lunn goto restore_link;
46354186b91SAndrew Lunn }
46454186b91SAndrew Lunn
46564d47d50SRussell King err = mv88e6xxx_port_config_interface(chip, port, mode);
466d78343d2SVivien Didelot restore_link:
467d78343d2SVivien Didelot if (chip->info->ops->port_set_link(chip, port, link))
468774439e5SVivien Didelot dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469d78343d2SVivien Didelot
470d78343d2SVivien Didelot return err;
471d78343d2SVivien Didelot }
472d78343d2SVivien Didelot
mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip * chip,int port)473ca345931SAlexis Lothoré static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
474d700ec41SMarek Vasut {
4753ba89b28SAlexis Lothoré return port >= chip->info->internal_phys_offset &&
4763ba89b28SAlexis Lothoré port < chip->info->num_internal_phys +
4773ba89b28SAlexis Lothoré chip->info->internal_phys_offset;
478d700ec41SMarek Vasut }
479d700ec41SMarek Vasut
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)4805d5b231dSRussell King static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
4815d5b231dSRussell King {
4825d5b231dSRussell King u16 reg;
4835d5b231dSRussell King int err;
4845d5b231dSRussell King
4852b29cb9eSRussell King (Oracle) /* The 88e6250 family does not have the PHY detect bit. Instead,
4862b29cb9eSRussell King (Oracle) * report whether the port is internal.
4872b29cb9eSRussell King (Oracle) */
4882b29cb9eSRussell King (Oracle) if (chip->info->family == MV88E6XXX_FAMILY_6250)
4897a2dd00bSAlexis Lothoré return mv88e6xxx_phy_is_internal(chip, port);
4902b29cb9eSRussell King (Oracle)
4915d5b231dSRussell King err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
4925d5b231dSRussell King if (err) {
4935d5b231dSRussell King dev_err(chip->dev,
4945d5b231dSRussell King "p%d: %s: failed to read port status\n",
4955d5b231dSRussell King port, __func__);
4965d5b231dSRussell King return err;
4975d5b231dSRussell King }
4985d5b231dSRussell King
4995d5b231dSRussell King return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
5005d5b231dSRussell King }
5015d5b231dSRussell King
502d4ebf12bSRussell King (Oracle) static const u8 mv88e6185_phy_interface_modes[] = {
503d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
504d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
505d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
506d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
507d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
508d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
509d4ebf12bSRussell King (Oracle) [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
510d4ebf12bSRussell King (Oracle) };
511d4ebf12bSRussell King (Oracle)
mv88e6095_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)512d0b78ab1STobias Waldekranz static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
513d0b78ab1STobias Waldekranz struct phylink_config *config)
514d0b78ab1STobias Waldekranz {
515d0b78ab1STobias Waldekranz u8 cmode = chip->ports[port].cmode;
516d0b78ab1STobias Waldekranz
517d0b78ab1STobias Waldekranz config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
518d0b78ab1STobias Waldekranz
519ca345931SAlexis Lothoré if (mv88e6xxx_phy_is_internal(chip, port)) {
520d0b78ab1STobias Waldekranz __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
521d0b78ab1STobias Waldekranz } else {
522d0b78ab1STobias Waldekranz if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
523d0b78ab1STobias Waldekranz mv88e6185_phy_interface_modes[cmode])
524d0b78ab1STobias Waldekranz __set_bit(mv88e6185_phy_interface_modes[cmode],
525d0b78ab1STobias Waldekranz config->supported_interfaces);
526d0b78ab1STobias Waldekranz
527d0b78ab1STobias Waldekranz config->mac_capabilities |= MAC_1000FD;
528d0b78ab1STobias Waldekranz }
529d0b78ab1STobias Waldekranz }
530d0b78ab1STobias Waldekranz
mv88e6185_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)531d4ebf12bSRussell King (Oracle) static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
532d4ebf12bSRussell King (Oracle) struct phylink_config *config)
533d4ebf12bSRussell King (Oracle) {
534d4ebf12bSRussell King (Oracle) u8 cmode = chip->ports[port].cmode;
535d4ebf12bSRussell King (Oracle)
536dde41a69SDan Carpenter if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
537d4ebf12bSRussell King (Oracle) mv88e6185_phy_interface_modes[cmode])
538d4ebf12bSRussell King (Oracle) __set_bit(mv88e6185_phy_interface_modes[cmode],
539d4ebf12bSRussell King (Oracle) config->supported_interfaces);
540d4ebf12bSRussell King (Oracle)
541d4ebf12bSRussell King (Oracle) config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
542d4ebf12bSRussell King (Oracle) MAC_1000FD;
543d4ebf12bSRussell King (Oracle) }
544d4ebf12bSRussell King (Oracle)
545d4ebf12bSRussell King (Oracle) static const u8 mv88e6xxx_phy_interface_modes[] = {
54618bb56abSAndrew Lunn [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
547d4ebf12bSRussell King (Oracle) [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
548d4ebf12bSRussell King (Oracle) [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
54918bb56abSAndrew Lunn [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
550d4ebf12bSRussell King (Oracle) [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
551d4ebf12bSRussell King (Oracle) [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
552d4ebf12bSRussell King (Oracle) [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
553d4ebf12bSRussell King (Oracle) [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
554d4ebf12bSRussell King (Oracle) /* higher interface modes are not needed here, since ports supporting
555d4ebf12bSRussell King (Oracle) * them are writable, and so the supported interfaces are filled in the
556d4ebf12bSRussell King (Oracle) * corresponding .phylink_set_interfaces() implementation below
5576c422e34SRussell King */
558d4ebf12bSRussell King (Oracle) };
559d4ebf12bSRussell King (Oracle)
mv88e6xxx_translate_cmode(u8 cmode,unsigned long * supported)560d4ebf12bSRussell King (Oracle) static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
561d4ebf12bSRussell King (Oracle) {
562d4ebf12bSRussell King (Oracle) if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
563d4ebf12bSRussell King (Oracle) mv88e6xxx_phy_interface_modes[cmode])
564d4ebf12bSRussell King (Oracle) __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
565d4ebf12bSRussell King (Oracle) else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
566d4ebf12bSRussell King (Oracle) phy_interface_set_rgmii(supported);
567d4ebf12bSRussell King (Oracle) }
568d4ebf12bSRussell King (Oracle)
5690142cbb8SMatthias Schiffer static void
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)5700142cbb8SMatthias Schiffer mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
571d4ebf12bSRussell King (Oracle) struct phylink_config *config)
572d4ebf12bSRussell King (Oracle) {
573d4ebf12bSRussell King (Oracle) unsigned long *supported = config->supported_interfaces;
5740142cbb8SMatthias Schiffer int err;
5750142cbb8SMatthias Schiffer u16 reg;
576d4ebf12bSRussell King (Oracle)
5770142cbb8SMatthias Schiffer err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
5780142cbb8SMatthias Schiffer if (err) {
5790142cbb8SMatthias Schiffer dev_err(chip->dev, "p%d: failed to read port status\n", port);
5800142cbb8SMatthias Schiffer return;
5810142cbb8SMatthias Schiffer }
5820142cbb8SMatthias Schiffer
5830142cbb8SMatthias Schiffer switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
5840142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
5850142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
5860142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
5870142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
5880142cbb8SMatthias Schiffer __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
5890142cbb8SMatthias Schiffer break;
5900142cbb8SMatthias Schiffer
5910142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
5920142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
5930142cbb8SMatthias Schiffer __set_bit(PHY_INTERFACE_MODE_MII, supported);
5940142cbb8SMatthias Schiffer break;
5950142cbb8SMatthias Schiffer
5960142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
5970142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
5980142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
5990142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
6000142cbb8SMatthias Schiffer __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
6010142cbb8SMatthias Schiffer break;
6020142cbb8SMatthias Schiffer
6030142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
6040142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
6050142cbb8SMatthias Schiffer __set_bit(PHY_INTERFACE_MODE_RMII, supported);
6060142cbb8SMatthias Schiffer break;
6070142cbb8SMatthias Schiffer
6080142cbb8SMatthias Schiffer case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
6090142cbb8SMatthias Schiffer __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
6100142cbb8SMatthias Schiffer break;
6110142cbb8SMatthias Schiffer
6120142cbb8SMatthias Schiffer default:
6130142cbb8SMatthias Schiffer dev_err(chip->dev,
6140142cbb8SMatthias Schiffer "p%d: invalid port mode in status register: %04x\n",
6150142cbb8SMatthias Schiffer port, reg);
6160142cbb8SMatthias Schiffer }
6170142cbb8SMatthias Schiffer }
6180142cbb8SMatthias Schiffer
mv88e6250_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)6190142cbb8SMatthias Schiffer static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
6200142cbb8SMatthias Schiffer struct phylink_config *config)
6210142cbb8SMatthias Schiffer {
6220142cbb8SMatthias Schiffer if (!mv88e6xxx_phy_is_internal(chip, port))
6230142cbb8SMatthias Schiffer mv88e6250_setup_supported_interfaces(chip, port, config);
624d4ebf12bSRussell King (Oracle)
625d4ebf12bSRussell King (Oracle) config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
626d4ebf12bSRussell King (Oracle) }
627d4ebf12bSRussell King (Oracle)
mv88e6351_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)6285cc4ed20SGreg Ungerer static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
6295cc4ed20SGreg Ungerer struct phylink_config *config)
6305cc4ed20SGreg Ungerer {
6315cc4ed20SGreg Ungerer unsigned long *supported = config->supported_interfaces;
6325cc4ed20SGreg Ungerer
6335cc4ed20SGreg Ungerer /* Translate the default cmode */
6345cc4ed20SGreg Ungerer mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
6355cc4ed20SGreg Ungerer
6365cc4ed20SGreg Ungerer config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
6375cc4ed20SGreg Ungerer MAC_1000FD;
6385cc4ed20SGreg Ungerer }
6395cc4ed20SGreg Ungerer
mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip * chip)640d4ebf12bSRussell King (Oracle) static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
641d4ebf12bSRussell King (Oracle) {
642d4ebf12bSRussell King (Oracle) u16 reg, val;
643d4ebf12bSRussell King (Oracle) int err;
644d4ebf12bSRussell King (Oracle)
645d4ebf12bSRussell King (Oracle) err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
646d4ebf12bSRussell King (Oracle) if (err)
647d4ebf12bSRussell King (Oracle) return err;
648d4ebf12bSRussell King (Oracle)
649d4ebf12bSRussell King (Oracle) /* If PHY_DETECT is zero, then we are not in auto-media mode */
650d4ebf12bSRussell King (Oracle) if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
651d4ebf12bSRussell King (Oracle) return 0xf;
652d4ebf12bSRussell King (Oracle)
653d4ebf12bSRussell King (Oracle) val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
654d4ebf12bSRussell King (Oracle) err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
655d4ebf12bSRussell King (Oracle) if (err)
656d4ebf12bSRussell King (Oracle) return err;
657d4ebf12bSRussell King (Oracle)
658d4ebf12bSRussell King (Oracle) err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
659d4ebf12bSRussell King (Oracle) if (err)
660d4ebf12bSRussell King (Oracle) return err;
661d4ebf12bSRussell King (Oracle)
662d4ebf12bSRussell King (Oracle) /* Restore PHY_DETECT value */
663d4ebf12bSRussell King (Oracle) err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
664d4ebf12bSRussell King (Oracle) if (err)
665d4ebf12bSRussell King (Oracle) return err;
666d4ebf12bSRussell King (Oracle)
667d4ebf12bSRussell King (Oracle) return val & MV88E6XXX_PORT_STS_CMODE_MASK;
668d4ebf12bSRussell King (Oracle) }
669d4ebf12bSRussell King (Oracle)
mv88e6352_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)670d4ebf12bSRussell King (Oracle) static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
671d4ebf12bSRussell King (Oracle) struct phylink_config *config)
672d4ebf12bSRussell King (Oracle) {
673d4ebf12bSRussell King (Oracle) unsigned long *supported = config->supported_interfaces;
674d4ebf12bSRussell King (Oracle) int err, cmode;
675d4ebf12bSRussell King (Oracle)
676d4ebf12bSRussell King (Oracle) /* Translate the default cmode */
677d4ebf12bSRussell King (Oracle) mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
678d4ebf12bSRussell King (Oracle)
679d4ebf12bSRussell King (Oracle) config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
680d4ebf12bSRussell King (Oracle) MAC_1000FD;
681d4ebf12bSRussell King (Oracle)
682d4ebf12bSRussell King (Oracle) /* Port 4 supports automedia if the serdes is associated with it. */
683d4ebf12bSRussell King (Oracle) if (port == 4) {
684d4ebf12bSRussell King (Oracle) err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
685d4ebf12bSRussell King (Oracle) if (err < 0)
686d4ebf12bSRussell King (Oracle) dev_err(chip->dev, "p%d: failed to read scratch\n",
687d4ebf12bSRussell King (Oracle) port);
688d4ebf12bSRussell King (Oracle) if (err <= 0)
689a7d82367SVladimir Oltean return;
690d4ebf12bSRussell King (Oracle)
691d4ebf12bSRussell King (Oracle) cmode = mv88e6352_get_port4_serdes_cmode(chip);
692d4ebf12bSRussell King (Oracle) if (cmode < 0)
693d4ebf12bSRussell King (Oracle) dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
694d4ebf12bSRussell King (Oracle) port);
695d4ebf12bSRussell King (Oracle) else
696d4ebf12bSRussell King (Oracle) mv88e6xxx_translate_cmode(cmode, supported);
697d4ebf12bSRussell King (Oracle) }
698d4ebf12bSRussell King (Oracle) }
699d4ebf12bSRussell King (Oracle)
mv88e632x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)7007019a641SSteffen Bätz static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
7017019a641SSteffen Bätz struct phylink_config *config)
7027019a641SSteffen Bätz {
7037019a641SSteffen Bätz unsigned long *supported = config->supported_interfaces;
7047019a641SSteffen Bätz
7057019a641SSteffen Bätz /* Translate the default cmode */
7067019a641SSteffen Bätz mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
7077019a641SSteffen Bätz
7087019a641SSteffen Bätz config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
7097019a641SSteffen Bätz MAC_1000FD;
7107019a641SSteffen Bätz }
7117019a641SSteffen Bätz
mv88e6341_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)712d4ebf12bSRussell King (Oracle) static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
713d4ebf12bSRussell King (Oracle) struct phylink_config *config)
714d4ebf12bSRussell King (Oracle) {
715d4ebf12bSRussell King (Oracle) unsigned long *supported = config->supported_interfaces;
716d4ebf12bSRussell King (Oracle)
717d4ebf12bSRussell King (Oracle) /* Translate the default cmode */
718d4ebf12bSRussell King (Oracle) mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
719d4ebf12bSRussell King (Oracle)
720d4ebf12bSRussell King (Oracle) /* No ethtool bits for 200Mbps */
721d4ebf12bSRussell King (Oracle) config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
722d4ebf12bSRussell King (Oracle) MAC_1000FD;
723d4ebf12bSRussell King (Oracle)
724d4ebf12bSRussell King (Oracle) /* The C_Mode field is programmable on port 5 */
725d4ebf12bSRussell King (Oracle) if (port == 5) {
726d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
727d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
728d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
729d4ebf12bSRussell King (Oracle)
730d4ebf12bSRussell King (Oracle) config->mac_capabilities |= MAC_2500FD;
731d4ebf12bSRussell King (Oracle) }
732d4ebf12bSRussell King (Oracle) }
733d4ebf12bSRussell King (Oracle)
mv88e6390_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)734d4ebf12bSRussell King (Oracle) static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
735d4ebf12bSRussell King (Oracle) struct phylink_config *config)
736d4ebf12bSRussell King (Oracle) {
737d4ebf12bSRussell King (Oracle) unsigned long *supported = config->supported_interfaces;
738d4ebf12bSRussell King (Oracle)
739d4ebf12bSRussell King (Oracle) /* Translate the default cmode */
740d4ebf12bSRussell King (Oracle) mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
741d4ebf12bSRussell King (Oracle)
742d4ebf12bSRussell King (Oracle) /* No ethtool bits for 200Mbps */
743d4ebf12bSRussell King (Oracle) config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
744d4ebf12bSRussell King (Oracle) MAC_1000FD;
745d4ebf12bSRussell King (Oracle)
746d4ebf12bSRussell King (Oracle) /* The C_Mode field is programmable on ports 9 and 10 */
747d4ebf12bSRussell King (Oracle) if (port == 9 || port == 10) {
748d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
749d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
750d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
751d4ebf12bSRussell King (Oracle)
752d4ebf12bSRussell King (Oracle) config->mac_capabilities |= MAC_2500FD;
753d4ebf12bSRussell King (Oracle) }
754d4ebf12bSRussell King (Oracle) }
755d4ebf12bSRussell King (Oracle)
mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)756d4ebf12bSRussell King (Oracle) static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
757d4ebf12bSRussell King (Oracle) struct phylink_config *config)
758d4ebf12bSRussell King (Oracle) {
759d4ebf12bSRussell King (Oracle) unsigned long *supported = config->supported_interfaces;
760d4ebf12bSRussell King (Oracle)
761d4ebf12bSRussell King (Oracle) mv88e6390_phylink_get_caps(chip, port, config);
762d4ebf12bSRussell King (Oracle)
763d4ebf12bSRussell King (Oracle) /* For the 6x90X, ports 2-7 can be in automedia mode.
764d4ebf12bSRussell King (Oracle) * (Note that 6x90 doesn't support RXAUI nor XAUI).
765d4ebf12bSRussell King (Oracle) *
766d4ebf12bSRussell King (Oracle) * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
767d4ebf12bSRussell King (Oracle) * configured for 1000BASE-X, SGMII or 2500BASE-X.
768d4ebf12bSRussell King (Oracle) * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
769d4ebf12bSRussell King (Oracle) * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
770d4ebf12bSRussell King (Oracle) *
771d4ebf12bSRussell King (Oracle) * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
772d4ebf12bSRussell King (Oracle) * configured for 1000BASE-X, SGMII or 2500BASE-X.
773d4ebf12bSRussell King (Oracle) * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
774d4ebf12bSRussell King (Oracle) * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
775d4ebf12bSRussell King (Oracle) *
776d4ebf12bSRussell King (Oracle) * For now, be permissive (as the old code was) and allow 1000BASE-X
777d4ebf12bSRussell King (Oracle) * on ports 2..7.
778d4ebf12bSRussell King (Oracle) */
779d4ebf12bSRussell King (Oracle) if (port >= 2 && port <= 7)
780d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
781d4ebf12bSRussell King (Oracle)
782d4ebf12bSRussell King (Oracle) /* The C_Mode field can also be programmed for 10G speeds */
783d4ebf12bSRussell King (Oracle) if (port == 9 || port == 10) {
784d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
785d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
786d4ebf12bSRussell King (Oracle)
787d4ebf12bSRussell King (Oracle) config->mac_capabilities |= MAC_10000FD;
788d4ebf12bSRussell King (Oracle) }
789d4ebf12bSRussell King (Oracle) }
790d4ebf12bSRussell King (Oracle)
mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)791d4ebf12bSRussell King (Oracle) static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
792d4ebf12bSRussell King (Oracle) struct phylink_config *config)
793d4ebf12bSRussell King (Oracle) {
794d4ebf12bSRussell King (Oracle) unsigned long *supported = config->supported_interfaces;
795d4ebf12bSRussell King (Oracle) bool is_6191x =
796d4ebf12bSRussell King (Oracle) chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
79712899f29SAlexis Lothoré bool is_6361 =
79812899f29SAlexis Lothoré chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
799d4ebf12bSRussell King (Oracle)
800d4ebf12bSRussell King (Oracle) mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
801d4ebf12bSRussell King (Oracle)
802d4ebf12bSRussell King (Oracle) config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
803d4ebf12bSRussell King (Oracle) MAC_1000FD;
804d4ebf12bSRussell King (Oracle)
805d4ebf12bSRussell King (Oracle) /* The C_Mode field can be programmed for ports 0, 9 and 10 */
806d4ebf12bSRussell King (Oracle) if (port == 0 || port == 9 || port == 10) {
807d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
808d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
809d4ebf12bSRussell King (Oracle)
810d4ebf12bSRussell King (Oracle) /* 6191X supports >1G modes only on port 10 */
811d4ebf12bSRussell King (Oracle) if (!is_6191x || port == 10) {
812d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
81312899f29SAlexis Lothoré config->mac_capabilities |= MAC_2500FD;
81412899f29SAlexis Lothoré
81512899f29SAlexis Lothoré /* 6361 only supports up to 2500BaseX */
81612899f29SAlexis Lothoré if (!is_6361) {
817d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
818d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
8194a562127SMichal Smulski __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
82012899f29SAlexis Lothoré config->mac_capabilities |= MAC_5000FD |
82112899f29SAlexis Lothoré MAC_10000FD;
82212899f29SAlexis Lothoré }
823d4ebf12bSRussell King (Oracle) }
824d4ebf12bSRussell King (Oracle) }
8251d2577abSMarcus Carlberg
8261d2577abSMarcus Carlberg if (port == 0) {
8271d2577abSMarcus Carlberg __set_bit(PHY_INTERFACE_MODE_RMII, supported);
8281d2577abSMarcus Carlberg __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
8291d2577abSMarcus Carlberg __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
8301d2577abSMarcus Carlberg __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
8311d2577abSMarcus Carlberg __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
8321d2577abSMarcus Carlberg }
833d4ebf12bSRussell King (Oracle) }
834d4ebf12bSRussell King (Oracle)
mv88e6xxx_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)835d4ebf12bSRussell King (Oracle) static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
836d4ebf12bSRussell King (Oracle) struct phylink_config *config)
837d4ebf12bSRussell King (Oracle) {
838d4ebf12bSRussell King (Oracle) struct mv88e6xxx_chip *chip = ds->priv;
839d4ebf12bSRussell King (Oracle)
840a7d82367SVladimir Oltean mv88e6xxx_reg_lock(chip);
841d4ebf12bSRussell King (Oracle) chip->info->ops->phylink_get_caps(chip, port, config);
842a7d82367SVladimir Oltean mv88e6xxx_reg_unlock(chip);
843d4ebf12bSRussell King (Oracle)
844ca345931SAlexis Lothoré if (mv88e6xxx_phy_is_internal(chip, port)) {
84587a39882SVladimir Oltean __set_bit(PHY_INTERFACE_MODE_INTERNAL,
84687a39882SVladimir Oltean config->supported_interfaces);
84787a39882SVladimir Oltean /* Internal ports with no phy-mode need GMII for PHYLIB */
848d4ebf12bSRussell King (Oracle) __set_bit(PHY_INTERFACE_MODE_GMII,
849d4ebf12bSRussell King (Oracle) config->supported_interfaces);
850c9a2356fSRussell King }
851b92143d4SRussell King (Oracle) }
852b92143d4SRussell King (Oracle)
mv88e6xxx_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)853b92143d4SRussell King (Oracle) static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
854b92143d4SRussell King (Oracle) int port,
855b92143d4SRussell King (Oracle) phy_interface_t interface)
856b92143d4SRussell King (Oracle) {
857b92143d4SRussell King (Oracle) struct mv88e6xxx_chip *chip = ds->priv;
858b92143d4SRussell King (Oracle) struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
859b92143d4SRussell King (Oracle)
860b92143d4SRussell King (Oracle) if (chip->info->ops->pcs_ops)
861b92143d4SRussell King (Oracle) pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
862b92143d4SRussell King (Oracle) interface);
863b92143d4SRussell King (Oracle)
864b92143d4SRussell King (Oracle) return pcs;
86587a39882SVladimir Oltean }
866c9a2356fSRussell King
mv88e6xxx_mac_prepare(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)867267d7692SRussell King (Oracle) static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
868267d7692SRussell King (Oracle) unsigned int mode, phy_interface_t interface)
869267d7692SRussell King (Oracle) {
870267d7692SRussell King (Oracle) struct mv88e6xxx_chip *chip = ds->priv;
871267d7692SRussell King (Oracle) int err = 0;
872267d7692SRussell King (Oracle)
873267d7692SRussell King (Oracle) /* In inband mode, the link may come up at any time while the link
874267d7692SRussell King (Oracle) * is not forced down. Force the link down while we reconfigure the
875267d7692SRussell King (Oracle) * interface mode.
876267d7692SRussell King (Oracle) */
877267d7692SRussell King (Oracle) if (mode == MLO_AN_INBAND &&
878267d7692SRussell King (Oracle) chip->ports[port].interface != interface &&
879267d7692SRussell King (Oracle) chip->info->ops->port_set_link) {
880267d7692SRussell King (Oracle) mv88e6xxx_reg_lock(chip);
881267d7692SRussell King (Oracle) err = chip->info->ops->port_set_link(chip, port,
882267d7692SRussell King (Oracle) LINK_FORCED_DOWN);
883267d7692SRussell King (Oracle) mv88e6xxx_reg_unlock(chip);
884267d7692SRussell King (Oracle) }
885267d7692SRussell King (Oracle)
886267d7692SRussell King (Oracle) return err;
887267d7692SRussell King (Oracle) }
888267d7692SRussell King (Oracle)
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)889c9a2356fSRussell King static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
890c9a2356fSRussell King unsigned int mode,
891c9a2356fSRussell King const struct phylink_link_state *state)
892c9a2356fSRussell King {
893c9a2356fSRussell King struct mv88e6xxx_chip *chip = ds->priv;
89404ec4e62SRussell King (Oracle) int err = 0;
895c9a2356fSRussell King
896c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
897fad58190SRussell King
898ca345931SAlexis Lothoré if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
89904ec4e62SRussell King (Oracle) err = mv88e6xxx_port_config_interface(chip, port,
90004ec4e62SRussell King (Oracle) state->interface);
901a5a6858bSRussell King if (err && err != -EOPNOTSUPP)
902a5a6858bSRussell King goto err_unlock;
90304ec4e62SRussell King (Oracle) }
904a5a6858bSRussell King
905267d7692SRussell King (Oracle) err_unlock:
906267d7692SRussell King (Oracle) mv88e6xxx_reg_unlock(chip);
907267d7692SRussell King (Oracle)
908267d7692SRussell King (Oracle) if (err && err != -EOPNOTSUPP)
909267d7692SRussell King (Oracle) dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
910267d7692SRussell King (Oracle) }
911267d7692SRussell King (Oracle)
mv88e6xxx_mac_finish(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)912267d7692SRussell King (Oracle) static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
913267d7692SRussell King (Oracle) unsigned int mode, phy_interface_t interface)
914267d7692SRussell King (Oracle) {
915267d7692SRussell King (Oracle) struct mv88e6xxx_chip *chip = ds->priv;
916267d7692SRussell King (Oracle) int err = 0;
917267d7692SRussell King (Oracle)
918fad58190SRussell King /* Undo the forced down state above after completing configuration
91904ec4e62SRussell King (Oracle) * irrespective of its state on entry, which allows the link to come
92004ec4e62SRussell King (Oracle) * up in the in-band case where there is no separate SERDES. Also
92104ec4e62SRussell King (Oracle) * ensure that the link can come up if the PPU is in use and we are
92204ec4e62SRussell King (Oracle) * in PHY mode (we treat the PPU as an effective in-band mechanism.)
923fad58190SRussell King */
924267d7692SRussell King (Oracle) mv88e6xxx_reg_lock(chip);
925267d7692SRussell King (Oracle)
92604ec4e62SRussell King (Oracle) if (chip->info->ops->port_set_link &&
927267d7692SRussell King (Oracle) ((mode == MLO_AN_INBAND &&
928267d7692SRussell King (Oracle) chip->ports[port].interface != interface) ||
92904ec4e62SRussell King (Oracle) (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
930267d7692SRussell King (Oracle) err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
931fad58190SRussell King
932c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
933c9a2356fSRussell King
934267d7692SRussell King (Oracle) chip->ports[port].interface = interface;
935267d7692SRussell King (Oracle)
936267d7692SRussell King (Oracle) return err;
937c9a2356fSRussell King }
938c9a2356fSRussell King
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)939c9a2356fSRussell King static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
940c9a2356fSRussell King unsigned int mode,
941c9a2356fSRussell King phy_interface_t interface)
942c9a2356fSRussell King {
94330c4a5b0SRussell King struct mv88e6xxx_chip *chip = ds->priv;
94430c4a5b0SRussell King const struct mv88e6xxx_ops *ops;
94530c4a5b0SRussell King int err = 0;
94630c4a5b0SRussell King
94730c4a5b0SRussell King ops = chip->info->ops;
94830c4a5b0SRussell King
94930c4a5b0SRussell King mv88e6xxx_reg_lock(chip);
9502b29cb9eSRussell King (Oracle) /* Force the link down if we know the port may not be automatically
9512b29cb9eSRussell King (Oracle) * updated by the switch or if we are using fixed-link mode.
9524a3e0aedSMaarten Zanders */
9532b29cb9eSRussell King (Oracle) if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
9544efe7662SChris Packham mode == MLO_AN_FIXED) && ops->port_sync_link)
9554efe7662SChris Packham err = ops->port_sync_link(chip, port, mode, false);
9569d591fc0SMarek Behún
9579d591fc0SMarek Behún if (!err && ops->port_set_speed_duplex)
9589d591fc0SMarek Behún err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
9599d591fc0SMarek Behún DUPLEX_UNFORCED);
96030c4a5b0SRussell King mv88e6xxx_reg_unlock(chip);
96130c4a5b0SRussell King
96230c4a5b0SRussell King if (err)
96330c4a5b0SRussell King dev_err(chip->dev,
96430c4a5b0SRussell King "p%d: failed to force MAC link down\n", port);
96530c4a5b0SRussell King }
966c9a2356fSRussell King
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)967c9a2356fSRussell King static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
968c9a2356fSRussell King unsigned int mode, phy_interface_t interface,
9695b502a7bSRussell King struct phy_device *phydev,
9705b502a7bSRussell King int speed, int duplex,
9715b502a7bSRussell King bool tx_pause, bool rx_pause)
972c9a2356fSRussell King {
97330c4a5b0SRussell King struct mv88e6xxx_chip *chip = ds->priv;
97430c4a5b0SRussell King const struct mv88e6xxx_ops *ops;
97530c4a5b0SRussell King int err = 0;
97630c4a5b0SRussell King
97730c4a5b0SRussell King ops = chip->info->ops;
97830c4a5b0SRussell King
97930c4a5b0SRussell King mv88e6xxx_reg_lock(chip);
9802b29cb9eSRussell King (Oracle) /* Configure and force the link up if we know that the port may not
9812b29cb9eSRussell King (Oracle) * automatically updated by the switch or if we are using fixed-link
9822b29cb9eSRussell King (Oracle) * mode.
9834a3e0aedSMaarten Zanders */
9842b29cb9eSRussell King (Oracle) if (!mv88e6xxx_port_ppu_updates(chip, port) ||
9854a3e0aedSMaarten Zanders mode == MLO_AN_FIXED) {
986f365c6f7SRussell King if (ops->port_set_speed_duplex) {
987f365c6f7SRussell King err = ops->port_set_speed_duplex(chip, port,
988f365c6f7SRussell King speed, duplex);
98930c4a5b0SRussell King if (err && err != -EOPNOTSUPP)
99030c4a5b0SRussell King goto error;
99130c4a5b0SRussell King }
99230c4a5b0SRussell King
9934efe7662SChris Packham if (ops->port_sync_link)
9944efe7662SChris Packham err = ops->port_sync_link(chip, port, mode, true);
9955d5b231dSRussell King }
99630c4a5b0SRussell King error:
99730c4a5b0SRussell King mv88e6xxx_reg_unlock(chip);
99830c4a5b0SRussell King
99930c4a5b0SRussell King if (err && err != -EOPNOTSUPP)
100030c4a5b0SRussell King dev_err(ds->dev,
100130c4a5b0SRussell King "p%d: failed to configure MAC link up\n", port);
100230c4a5b0SRussell King }
1003c9a2356fSRussell King
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)1004a605a0feSAndrew Lunn static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1005fad09c73SVivien Didelot {
1006a605a0feSAndrew Lunn if (!chip->info->ops->stats_snapshot)
1007a605a0feSAndrew Lunn return -EOPNOTSUPP;
1008fad09c73SVivien Didelot
1009a605a0feSAndrew Lunn return chip->info->ops->stats_snapshot(chip, port);
1010fad09c73SVivien Didelot }
1011fad09c73SVivien Didelot
1012fad09c73SVivien Didelot static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1013dfafe449SAndrew Lunn { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
1014dfafe449SAndrew Lunn { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
1015dfafe449SAndrew Lunn { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
1016dfafe449SAndrew Lunn { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
1017dfafe449SAndrew Lunn { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
1018dfafe449SAndrew Lunn { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
1019dfafe449SAndrew Lunn { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
1020dfafe449SAndrew Lunn { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
1021dfafe449SAndrew Lunn { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
1022dfafe449SAndrew Lunn { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
1023dfafe449SAndrew Lunn { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
1024dfafe449SAndrew Lunn { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
1025dfafe449SAndrew Lunn { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
1026dfafe449SAndrew Lunn { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
1027dfafe449SAndrew Lunn { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
1028dfafe449SAndrew Lunn { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
1029dfafe449SAndrew Lunn { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
1030dfafe449SAndrew Lunn { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
1031dfafe449SAndrew Lunn { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
1032dfafe449SAndrew Lunn { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
1033dfafe449SAndrew Lunn { "single", 4, 0x14, STATS_TYPE_BANK0, },
1034dfafe449SAndrew Lunn { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
1035dfafe449SAndrew Lunn { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
1036dfafe449SAndrew Lunn { "late", 4, 0x1f, STATS_TYPE_BANK0, },
1037dfafe449SAndrew Lunn { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
1038dfafe449SAndrew Lunn { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
1039dfafe449SAndrew Lunn { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
1040dfafe449SAndrew Lunn { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
1041dfafe449SAndrew Lunn { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
1042dfafe449SAndrew Lunn { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
1043dfafe449SAndrew Lunn { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
1044dfafe449SAndrew Lunn { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
1045dfafe449SAndrew Lunn { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
1046dfafe449SAndrew Lunn { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
1047dfafe449SAndrew Lunn { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
1048dfafe449SAndrew Lunn { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
1049dfafe449SAndrew Lunn { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
1050dfafe449SAndrew Lunn { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
1051dfafe449SAndrew Lunn { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
1052dfafe449SAndrew Lunn { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
1053dfafe449SAndrew Lunn { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
1054dfafe449SAndrew Lunn { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
1055dfafe449SAndrew Lunn { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
1056dfafe449SAndrew Lunn { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
1057dfafe449SAndrew Lunn { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
1058dfafe449SAndrew Lunn { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
1059dfafe449SAndrew Lunn { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
1060dfafe449SAndrew Lunn { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
1061dfafe449SAndrew Lunn { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
1062dfafe449SAndrew Lunn { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
1063dfafe449SAndrew Lunn { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
1064dfafe449SAndrew Lunn { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
1065dfafe449SAndrew Lunn { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
1066dfafe449SAndrew Lunn { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
1067dfafe449SAndrew Lunn { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
1068dfafe449SAndrew Lunn { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
1069dfafe449SAndrew Lunn { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
1070dfafe449SAndrew Lunn { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
1071dfafe449SAndrew Lunn { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
1072fad09c73SVivien Didelot };
1073fad09c73SVivien Didelot
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)1074fad09c73SVivien Didelot static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1075fad09c73SVivien Didelot struct mv88e6xxx_hw_stat *s,
1076e0d8b615SAndrew Lunn int port, u16 bank1_select,
1077e0d8b615SAndrew Lunn u16 histogram)
1078fad09c73SVivien Didelot {
1079fad09c73SVivien Didelot u32 low;
1080fad09c73SVivien Didelot u32 high = 0;
1081dfafe449SAndrew Lunn u16 reg = 0;
10820e7b9925SAndrew Lunn int err;
1083fad09c73SVivien Didelot u64 value;
1084fad09c73SVivien Didelot
1085fad09c73SVivien Didelot switch (s->type) {
1086dfafe449SAndrew Lunn case STATS_TYPE_PORT:
10870e7b9925SAndrew Lunn err = mv88e6xxx_port_read(chip, port, s->reg, ®);
10880e7b9925SAndrew Lunn if (err)
10896c3442f5SJisheng Zhang return U64_MAX;
1090fad09c73SVivien Didelot
10910e7b9925SAndrew Lunn low = reg;
1092cda9f4aaSAndrew Lunn if (s->size == 4) {
10930e7b9925SAndrew Lunn err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
10940e7b9925SAndrew Lunn if (err)
10956c3442f5SJisheng Zhang return U64_MAX;
109684b3fd1fSRasmus Villemoes low |= ((u32)reg) << 16;
1097fad09c73SVivien Didelot }
1098fad09c73SVivien Didelot break;
1099dfafe449SAndrew Lunn case STATS_TYPE_BANK1:
1100e0d8b615SAndrew Lunn reg = bank1_select;
1101df561f66SGustavo A. R. Silva fallthrough;
1102dfafe449SAndrew Lunn case STATS_TYPE_BANK0:
1103e0d8b615SAndrew Lunn reg |= s->reg | histogram;
11047f9ef3afSAndrew Lunn mv88e6xxx_g1_stats_read(chip, reg, &low);
1105cda9f4aaSAndrew Lunn if (s->size == 8)
11067f9ef3afSAndrew Lunn mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
11079fc3e4dcSGustavo A. R. Silva break;
11089fc3e4dcSGustavo A. R. Silva default:
11096c3442f5SJisheng Zhang return U64_MAX;
1110fad09c73SVivien Didelot }
11116e46e2d8SAndrew Lunn value = (((u64)high) << 32) | low;
1112fad09c73SVivien Didelot return value;
1113fad09c73SVivien Didelot }
1114fad09c73SVivien Didelot
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)1115436fe17dSAndrew Lunn static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1116dfafe449SAndrew Lunn uint8_t *data, int types)
1117fad09c73SVivien Didelot {
1118fad09c73SVivien Didelot struct mv88e6xxx_hw_stat *stat;
1119fad09c73SVivien Didelot int i, j;
1120fad09c73SVivien Didelot
1121fad09c73SVivien Didelot for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1122fad09c73SVivien Didelot stat = &mv88e6xxx_hw_stats[i];
1123dfafe449SAndrew Lunn if (stat->type & types) {
1124fad09c73SVivien Didelot memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1125fad09c73SVivien Didelot ETH_GSTRING_LEN);
1126fad09c73SVivien Didelot j++;
1127fad09c73SVivien Didelot }
1128fad09c73SVivien Didelot }
1129436fe17dSAndrew Lunn
1130436fe17dSAndrew Lunn return j;
1131fad09c73SVivien Didelot }
1132fad09c73SVivien Didelot
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1133436fe17dSAndrew Lunn static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1134dfafe449SAndrew Lunn uint8_t *data)
1135dfafe449SAndrew Lunn {
1136436fe17dSAndrew Lunn return mv88e6xxx_stats_get_strings(chip, data,
1137dfafe449SAndrew Lunn STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1138dfafe449SAndrew Lunn }
1139dfafe449SAndrew Lunn
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)11401f71836fSRasmus Villemoes static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
11411f71836fSRasmus Villemoes uint8_t *data)
11421f71836fSRasmus Villemoes {
11431f71836fSRasmus Villemoes return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
11441f71836fSRasmus Villemoes }
11451f71836fSRasmus Villemoes
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1146436fe17dSAndrew Lunn static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1147dfafe449SAndrew Lunn uint8_t *data)
1148dfafe449SAndrew Lunn {
1149436fe17dSAndrew Lunn return mv88e6xxx_stats_get_strings(chip, data,
1150dfafe449SAndrew Lunn STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1151dfafe449SAndrew Lunn }
1152dfafe449SAndrew Lunn
115365f60e45SAndrew Lunn static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
115465f60e45SAndrew Lunn "atu_member_violation",
115565f60e45SAndrew Lunn "atu_miss_violation",
115665f60e45SAndrew Lunn "atu_full_violation",
115765f60e45SAndrew Lunn "vtu_member_violation",
115865f60e45SAndrew Lunn "vtu_miss_violation",
115965f60e45SAndrew Lunn };
116065f60e45SAndrew Lunn
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)116165f60e45SAndrew Lunn static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
116265f60e45SAndrew Lunn {
116365f60e45SAndrew Lunn unsigned int i;
116465f60e45SAndrew Lunn
116565f60e45SAndrew Lunn for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1166fb3ceec1SWolfram Sang strscpy(data + i * ETH_GSTRING_LEN,
116765f60e45SAndrew Lunn mv88e6xxx_atu_vtu_stats_strings[i],
116865f60e45SAndrew Lunn ETH_GSTRING_LEN);
116965f60e45SAndrew Lunn }
117065f60e45SAndrew Lunn
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1171dfafe449SAndrew Lunn static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
117289f09048SFlorian Fainelli u32 stringset, uint8_t *data)
1173fad09c73SVivien Didelot {
117404bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
1175436fe17dSAndrew Lunn int count = 0;
1176dfafe449SAndrew Lunn
117789f09048SFlorian Fainelli if (stringset != ETH_SS_STATS)
117889f09048SFlorian Fainelli return;
117989f09048SFlorian Fainelli
1180c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1181c6c8cd5eSAndrew Lunn
1182dfafe449SAndrew Lunn if (chip->info->ops->stats_get_strings)
1183436fe17dSAndrew Lunn count = chip->info->ops->stats_get_strings(chip, data);
1184436fe17dSAndrew Lunn
1185436fe17dSAndrew Lunn if (chip->info->ops->serdes_get_strings) {
1186436fe17dSAndrew Lunn data += count * ETH_GSTRING_LEN;
118765f60e45SAndrew Lunn count = chip->info->ops->serdes_get_strings(chip, port, data);
1188436fe17dSAndrew Lunn }
1189c6c8cd5eSAndrew Lunn
119065f60e45SAndrew Lunn data += count * ETH_GSTRING_LEN;
119165f60e45SAndrew Lunn mv88e6xxx_atu_vtu_get_strings(data);
119265f60e45SAndrew Lunn
1193c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1194dfafe449SAndrew Lunn }
1195dfafe449SAndrew Lunn
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1196dfafe449SAndrew Lunn static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1197dfafe449SAndrew Lunn int types)
1198dfafe449SAndrew Lunn {
1199fad09c73SVivien Didelot struct mv88e6xxx_hw_stat *stat;
1200fad09c73SVivien Didelot int i, j;
1201fad09c73SVivien Didelot
1202fad09c73SVivien Didelot for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1203fad09c73SVivien Didelot stat = &mv88e6xxx_hw_stats[i];
1204dfafe449SAndrew Lunn if (stat->type & types)
1205fad09c73SVivien Didelot j++;
1206fad09c73SVivien Didelot }
1207fad09c73SVivien Didelot return j;
1208fad09c73SVivien Didelot }
1209fad09c73SVivien Didelot
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1210dfafe449SAndrew Lunn static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1211dfafe449SAndrew Lunn {
1212dfafe449SAndrew Lunn return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1213dfafe449SAndrew Lunn STATS_TYPE_PORT);
1214dfafe449SAndrew Lunn }
1215dfafe449SAndrew Lunn
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)12161f71836fSRasmus Villemoes static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
12171f71836fSRasmus Villemoes {
12181f71836fSRasmus Villemoes return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
12191f71836fSRasmus Villemoes }
12201f71836fSRasmus Villemoes
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1221dfafe449SAndrew Lunn static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1222dfafe449SAndrew Lunn {
1223dfafe449SAndrew Lunn return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1224dfafe449SAndrew Lunn STATS_TYPE_BANK1);
1225dfafe449SAndrew Lunn }
1226dfafe449SAndrew Lunn
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)122789f09048SFlorian Fainelli static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1228dfafe449SAndrew Lunn {
1229dfafe449SAndrew Lunn struct mv88e6xxx_chip *chip = ds->priv;
1230436fe17dSAndrew Lunn int serdes_count = 0;
1231436fe17dSAndrew Lunn int count = 0;
1232dfafe449SAndrew Lunn
123389f09048SFlorian Fainelli if (sset != ETH_SS_STATS)
123489f09048SFlorian Fainelli return 0;
123589f09048SFlorian Fainelli
1236c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1237dfafe449SAndrew Lunn if (chip->info->ops->stats_get_sset_count)
1238436fe17dSAndrew Lunn count = chip->info->ops->stats_get_sset_count(chip);
1239436fe17dSAndrew Lunn if (count < 0)
1240436fe17dSAndrew Lunn goto out;
1241436fe17dSAndrew Lunn
1242436fe17dSAndrew Lunn if (chip->info->ops->serdes_get_sset_count)
1243436fe17dSAndrew Lunn serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1244436fe17dSAndrew Lunn port);
124565f60e45SAndrew Lunn if (serdes_count < 0) {
1246436fe17dSAndrew Lunn count = serdes_count;
124765f60e45SAndrew Lunn goto out;
124865f60e45SAndrew Lunn }
1249436fe17dSAndrew Lunn count += serdes_count;
125065f60e45SAndrew Lunn count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
125165f60e45SAndrew Lunn
1252436fe17dSAndrew Lunn out:
1253c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1254dfafe449SAndrew Lunn
1255436fe17dSAndrew Lunn return count;
1256dfafe449SAndrew Lunn }
1257dfafe449SAndrew Lunn
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1258436fe17dSAndrew Lunn static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1259e0d8b615SAndrew Lunn uint64_t *data, int types,
1260e0d8b615SAndrew Lunn u16 bank1_select, u16 histogram)
1261052f947fSAndrew Lunn {
1262052f947fSAndrew Lunn struct mv88e6xxx_hw_stat *stat;
1263052f947fSAndrew Lunn int i, j;
1264052f947fSAndrew Lunn
1265052f947fSAndrew Lunn for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1266052f947fSAndrew Lunn stat = &mv88e6xxx_hw_stats[i];
1267052f947fSAndrew Lunn if (stat->type & types) {
1268c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1269e0d8b615SAndrew Lunn data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1270e0d8b615SAndrew Lunn bank1_select,
1271e0d8b615SAndrew Lunn histogram);
1272c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1273377cda13SAndrew Lunn
1274052f947fSAndrew Lunn j++;
1275052f947fSAndrew Lunn }
1276052f947fSAndrew Lunn }
1277436fe17dSAndrew Lunn return j;
1278052f947fSAndrew Lunn }
1279052f947fSAndrew Lunn
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1280436fe17dSAndrew Lunn static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1281052f947fSAndrew Lunn uint64_t *data)
1282052f947fSAndrew Lunn {
1283052f947fSAndrew Lunn return mv88e6xxx_stats_get_stats(chip, port, data,
1284e0d8b615SAndrew Lunn STATS_TYPE_BANK0 | STATS_TYPE_PORT,
128557d1ef38SVivien Didelot 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1286052f947fSAndrew Lunn }
1287052f947fSAndrew Lunn
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)12881f71836fSRasmus Villemoes static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
12891f71836fSRasmus Villemoes uint64_t *data)
12901f71836fSRasmus Villemoes {
12911f71836fSRasmus Villemoes return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
12921f71836fSRasmus Villemoes 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
12931f71836fSRasmus Villemoes }
12941f71836fSRasmus Villemoes
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1295436fe17dSAndrew Lunn static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1296052f947fSAndrew Lunn uint64_t *data)
1297052f947fSAndrew Lunn {
1298052f947fSAndrew Lunn return mv88e6xxx_stats_get_stats(chip, port, data,
1299e0d8b615SAndrew Lunn STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
130057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
130157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1302e0d8b615SAndrew Lunn }
1303e0d8b615SAndrew Lunn
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1304436fe17dSAndrew Lunn static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1305e0d8b615SAndrew Lunn uint64_t *data)
1306e0d8b615SAndrew Lunn {
1307e0d8b615SAndrew Lunn return mv88e6xxx_stats_get_stats(chip, port, data,
1308e0d8b615SAndrew Lunn STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
130957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
131057d1ef38SVivien Didelot 0);
1311052f947fSAndrew Lunn }
1312052f947fSAndrew Lunn
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)131365f60e45SAndrew Lunn static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
131465f60e45SAndrew Lunn uint64_t *data)
131565f60e45SAndrew Lunn {
131665f60e45SAndrew Lunn *data++ = chip->ports[port].atu_member_violation;
131765f60e45SAndrew Lunn *data++ = chip->ports[port].atu_miss_violation;
131865f60e45SAndrew Lunn *data++ = chip->ports[port].atu_full_violation;
131965f60e45SAndrew Lunn *data++ = chip->ports[port].vtu_member_violation;
132065f60e45SAndrew Lunn *data++ = chip->ports[port].vtu_miss_violation;
132165f60e45SAndrew Lunn }
132265f60e45SAndrew Lunn
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1323052f947fSAndrew Lunn static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1324052f947fSAndrew Lunn uint64_t *data)
1325052f947fSAndrew Lunn {
1326436fe17dSAndrew Lunn int count = 0;
1327436fe17dSAndrew Lunn
1328052f947fSAndrew Lunn if (chip->info->ops->stats_get_stats)
1329436fe17dSAndrew Lunn count = chip->info->ops->stats_get_stats(chip, port, data);
1330436fe17dSAndrew Lunn
1331c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1332436fe17dSAndrew Lunn if (chip->info->ops->serdes_get_stats) {
1333436fe17dSAndrew Lunn data += count;
133465f60e45SAndrew Lunn count = chip->info->ops->serdes_get_stats(chip, port, data);
1335436fe17dSAndrew Lunn }
133665f60e45SAndrew Lunn data += count;
133765f60e45SAndrew Lunn mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1338c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1339052f947fSAndrew Lunn }
1340052f947fSAndrew Lunn
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1341fad09c73SVivien Didelot static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1342fad09c73SVivien Didelot uint64_t *data)
1343fad09c73SVivien Didelot {
134404bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
1345fad09c73SVivien Didelot int ret;
1346fad09c73SVivien Didelot
1347c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1348fad09c73SVivien Didelot
1349a605a0feSAndrew Lunn ret = mv88e6xxx_stats_snapshot(chip, port);
1350c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1351377cda13SAndrew Lunn
1352377cda13SAndrew Lunn if (ret < 0)
1353fad09c73SVivien Didelot return;
1354052f947fSAndrew Lunn
1355052f947fSAndrew Lunn mv88e6xxx_get_stats(chip, port, data);
1356fad09c73SVivien Didelot
1357fad09c73SVivien Didelot }
1358fad09c73SVivien Didelot
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1359fad09c73SVivien Didelot static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1360fad09c73SVivien Didelot {
13610d30bbd0SAndrew Lunn struct mv88e6xxx_chip *chip = ds->priv;
13620d30bbd0SAndrew Lunn int len;
13630d30bbd0SAndrew Lunn
13640d30bbd0SAndrew Lunn len = 32 * sizeof(u16);
13650d30bbd0SAndrew Lunn if (chip->info->ops->serdes_get_regs_len)
13660d30bbd0SAndrew Lunn len += chip->info->ops->serdes_get_regs_len(chip, port);
13670d30bbd0SAndrew Lunn
13680d30bbd0SAndrew Lunn return len;
1369fad09c73SVivien Didelot }
1370fad09c73SVivien Didelot
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1371fad09c73SVivien Didelot static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1372fad09c73SVivien Didelot struct ethtool_regs *regs, void *_p)
1373fad09c73SVivien Didelot {
137404bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
13750e7b9925SAndrew Lunn int err;
13760e7b9925SAndrew Lunn u16 reg;
1377fad09c73SVivien Didelot u16 *p = _p;
1378fad09c73SVivien Didelot int i;
1379fad09c73SVivien Didelot
1380a5f39326SVivien Didelot regs->version = chip->info->prod_num;
1381fad09c73SVivien Didelot
1382fad09c73SVivien Didelot memset(p, 0xff, 32 * sizeof(u16));
1383fad09c73SVivien Didelot
1384c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1385fad09c73SVivien Didelot
1386fad09c73SVivien Didelot for (i = 0; i < 32; i++) {
1387fad09c73SVivien Didelot
13880e7b9925SAndrew Lunn err = mv88e6xxx_port_read(chip, port, i, ®);
13890e7b9925SAndrew Lunn if (!err)
13900e7b9925SAndrew Lunn p[i] = reg;
1391fad09c73SVivien Didelot }
1392fad09c73SVivien Didelot
13930d30bbd0SAndrew Lunn if (chip->info->ops->serdes_get_regs)
13940d30bbd0SAndrew Lunn chip->info->ops->serdes_get_regs(chip, port, &p[i]);
13950d30bbd0SAndrew Lunn
1396c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1397fad09c73SVivien Didelot }
1398fad09c73SVivien Didelot
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)139908f50061SVivien Didelot static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1400fad09c73SVivien Didelot struct ethtool_eee *e)
1401fad09c73SVivien Didelot {
14025480db69SVivien Didelot /* Nothing to do on the port's MAC */
14035480db69SVivien Didelot return 0;
1404fad09c73SVivien Didelot }
1405fad09c73SVivien Didelot
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)140608f50061SVivien Didelot static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
140746587e4aSVivien Didelot struct ethtool_eee *e)
1408fad09c73SVivien Didelot {
14095480db69SVivien Didelot /* Nothing to do on the port's MAC */
14105480db69SVivien Didelot return 0;
1411fad09c73SVivien Didelot }
1412fad09c73SVivien Didelot
14139dc8b13eSVivien Didelot /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1414e5887a2aSVivien Didelot static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1415fad09c73SVivien Didelot {
14169dc8b13eSVivien Didelot struct dsa_switch *ds = chip->ds;
14179dc8b13eSVivien Didelot struct dsa_switch_tree *dst = ds->dst;
141865144067SVladimir Oltean struct dsa_port *dp, *other_dp;
14199dc8b13eSVivien Didelot bool found = false;
1420e5887a2aSVivien Didelot u16 pvlan;
1421fad09c73SVivien Didelot
1422ce5df689SVladimir Oltean /* dev is a physical switch */
1423ce5df689SVladimir Oltean if (dev <= dst->last_switch) {
14249dc8b13eSVivien Didelot list_for_each_entry(dp, &dst->ports, list) {
14259dc8b13eSVivien Didelot if (dp->ds->index == dev && dp->index == port) {
1426ce5df689SVladimir Oltean /* dp might be a DSA link or a user port, so it
142765144067SVladimir Oltean * might or might not have a bridge.
142865144067SVladimir Oltean * Use the "found" variable for both cases.
1429ce5df689SVladimir Oltean */
1430ce5df689SVladimir Oltean found = true;
1431ce5df689SVladimir Oltean break;
1432ce5df689SVladimir Oltean }
1433ce5df689SVladimir Oltean }
1434ce5df689SVladimir Oltean /* dev is a virtual bridge */
1435ce5df689SVladimir Oltean } else {
1436ce5df689SVladimir Oltean list_for_each_entry(dp, &dst->ports, list) {
143741fb0cf1SVladimir Oltean unsigned int bridge_num = dsa_port_bridge_num_get(dp);
143841fb0cf1SVladimir Oltean
143941fb0cf1SVladimir Oltean if (!bridge_num)
1440ce5df689SVladimir Oltean continue;
1441ce5df689SVladimir Oltean
144241fb0cf1SVladimir Oltean if (bridge_num + dst->last_switch != dev)
1443ce5df689SVladimir Oltean continue;
1444ce5df689SVladimir Oltean
14459dc8b13eSVivien Didelot found = true;
14469dc8b13eSVivien Didelot break;
14479dc8b13eSVivien Didelot }
14489dc8b13eSVivien Didelot }
1449fad09c73SVivien Didelot
1450ce5df689SVladimir Oltean /* Prevent frames from unknown switch or virtual bridge */
14519dc8b13eSVivien Didelot if (!found)
1452e5887a2aSVivien Didelot return 0;
1453e5887a2aSVivien Didelot
1454e5887a2aSVivien Didelot /* Frames from DSA links and CPU ports can egress any local port */
14559dc8b13eSVivien Didelot if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1456e5887a2aSVivien Didelot return mv88e6xxx_port_mask(chip);
1457e5887a2aSVivien Didelot
1458e5887a2aSVivien Didelot pvlan = 0;
1459e5887a2aSVivien Didelot
14607af4a361STobias Waldekranz /* Frames from standalone user ports can only egress on the
14617af4a361STobias Waldekranz * upstream port.
14627af4a361STobias Waldekranz */
14637af4a361STobias Waldekranz if (!dsa_port_bridge_dev_get(dp))
14647af4a361STobias Waldekranz return BIT(dsa_switch_upstream_port(ds));
14657af4a361STobias Waldekranz
14667af4a361STobias Waldekranz /* Frames from bridged user ports can egress any local DSA
14677af4a361STobias Waldekranz * links and CPU ports, as well as any local member of their
14687af4a361STobias Waldekranz * bridge group.
1469e5887a2aSVivien Didelot */
147065144067SVladimir Oltean dsa_switch_for_each_port(other_dp, ds)
147165144067SVladimir Oltean if (other_dp->type == DSA_PORT_TYPE_CPU ||
147265144067SVladimir Oltean other_dp->type == DSA_PORT_TYPE_DSA ||
147341fb0cf1SVladimir Oltean dsa_port_bridge_same(dp, other_dp))
147465144067SVladimir Oltean pvlan |= BIT(other_dp->index);
1475e5887a2aSVivien Didelot
1476e5887a2aSVivien Didelot return pvlan;
1477fad09c73SVivien Didelot }
1478e5887a2aSVivien Didelot
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1479240ea3efSVivien Didelot static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1480e5887a2aSVivien Didelot {
1481e5887a2aSVivien Didelot u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1482fad09c73SVivien Didelot
1483fad09c73SVivien Didelot /* prevent frames from going back out of the port they came in on */
1484fad09c73SVivien Didelot output_ports &= ~BIT(port);
1485fad09c73SVivien Didelot
14865a7921f4SVivien Didelot return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1487fad09c73SVivien Didelot }
1488fad09c73SVivien Didelot
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1489fad09c73SVivien Didelot static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1490fad09c73SVivien Didelot u8 state)
1491fad09c73SVivien Didelot {
149204bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
1493fad09c73SVivien Didelot int err;
1494fad09c73SVivien Didelot
1495c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1496f894c29cSVivien Didelot err = mv88e6xxx_port_set_state(chip, port, state);
1497c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1498fad09c73SVivien Didelot
1499fad09c73SVivien Didelot if (err)
1500774439e5SVivien Didelot dev_err(ds->dev, "p%d: failed to update state\n", port);
1501fad09c73SVivien Didelot }
1502fad09c73SVivien Didelot
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)150393e18d61SVivien Didelot static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
150493e18d61SVivien Didelot {
150593e18d61SVivien Didelot int err;
150693e18d61SVivien Didelot
150793e18d61SVivien Didelot if (chip->info->ops->ieee_pri_map) {
150893e18d61SVivien Didelot err = chip->info->ops->ieee_pri_map(chip);
150993e18d61SVivien Didelot if (err)
151093e18d61SVivien Didelot return err;
151193e18d61SVivien Didelot }
151293e18d61SVivien Didelot
151393e18d61SVivien Didelot if (chip->info->ops->ip_pri_map) {
151493e18d61SVivien Didelot err = chip->info->ops->ip_pri_map(chip);
151593e18d61SVivien Didelot if (err)
151693e18d61SVivien Didelot return err;
151793e18d61SVivien Didelot }
151893e18d61SVivien Didelot
151993e18d61SVivien Didelot return 0;
152093e18d61SVivien Didelot }
152193e18d61SVivien Didelot
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1522c7f047b6SVivien Didelot static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1523c7f047b6SVivien Didelot {
1524c5f51765SVivien Didelot struct dsa_switch *ds = chip->ds;
1525c7f047b6SVivien Didelot int target, port;
1526c7f047b6SVivien Didelot int err;
1527c7f047b6SVivien Didelot
1528c7f047b6SVivien Didelot if (!chip->info->global2_addr)
1529c7f047b6SVivien Didelot return 0;
1530c7f047b6SVivien Didelot
1531c7f047b6SVivien Didelot /* Initialize the routing port to the 32 possible target devices */
1532c7f047b6SVivien Didelot for (target = 0; target < 32; target++) {
1533c5f51765SVivien Didelot port = dsa_routing_port(ds, target);
1534c5f51765SVivien Didelot if (port == ds->num_ports)
1535c7f047b6SVivien Didelot port = 0x1f;
1536c7f047b6SVivien Didelot
1537c7f047b6SVivien Didelot err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1538c7f047b6SVivien Didelot if (err)
1539c7f047b6SVivien Didelot return err;
1540c7f047b6SVivien Didelot }
1541c7f047b6SVivien Didelot
154202317e68SVivien Didelot if (chip->info->ops->set_cascade_port) {
154302317e68SVivien Didelot port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
154402317e68SVivien Didelot err = chip->info->ops->set_cascade_port(chip, port);
154502317e68SVivien Didelot if (err)
154602317e68SVivien Didelot return err;
154702317e68SVivien Didelot }
154802317e68SVivien Didelot
154923c98919SVivien Didelot err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
155023c98919SVivien Didelot if (err)
155123c98919SVivien Didelot return err;
155223c98919SVivien Didelot
1553c7f047b6SVivien Didelot return 0;
1554c7f047b6SVivien Didelot }
1555c7f047b6SVivien Didelot
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1556b28f872dSVivien Didelot static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1557b28f872dSVivien Didelot {
1558b28f872dSVivien Didelot /* Clear all trunk masks and mapping */
1559b28f872dSVivien Didelot if (chip->info->global2_addr)
1560b28f872dSVivien Didelot return mv88e6xxx_g2_trunk_clear(chip);
1561b28f872dSVivien Didelot
1562b28f872dSVivien Didelot return 0;
1563b28f872dSVivien Didelot }
1564b28f872dSVivien Didelot
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)15659e5baf9bSVivien Didelot static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
15669e5baf9bSVivien Didelot {
15679e5baf9bSVivien Didelot if (chip->info->ops->rmu_disable)
15689e5baf9bSVivien Didelot return chip->info->ops->rmu_disable(chip);
15699e5baf9bSVivien Didelot
15709e5baf9bSVivien Didelot return 0;
15719e5baf9bSVivien Didelot }
15729e5baf9bSVivien Didelot
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)15739e907d73SVivien Didelot static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
15749e907d73SVivien Didelot {
15759e907d73SVivien Didelot if (chip->info->ops->pot_clear)
15769e907d73SVivien Didelot return chip->info->ops->pot_clear(chip);
15779e907d73SVivien Didelot
15789e907d73SVivien Didelot return 0;
15799e907d73SVivien Didelot }
15809e907d73SVivien Didelot
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)158151c901a7SVivien Didelot static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
158251c901a7SVivien Didelot {
158351c901a7SVivien Didelot if (chip->info->ops->mgmt_rsvd2cpu)
158451c901a7SVivien Didelot return chip->info->ops->mgmt_rsvd2cpu(chip);
158551c901a7SVivien Didelot
158651c901a7SVivien Didelot return 0;
158751c901a7SVivien Didelot }
158851c901a7SVivien Didelot
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1589a2ac29d2SVivien Didelot static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1590a2ac29d2SVivien Didelot {
1591c3a7d4adSVivien Didelot int err;
1592c3a7d4adSVivien Didelot
1593daefc943SVivien Didelot err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1594daefc943SVivien Didelot if (err)
1595daefc943SVivien Didelot return err;
1596daefc943SVivien Didelot
159749506a9bSRasmus Villemoes /* The chips that have a "learn2all" bit in Global1, ATU
159849506a9bSRasmus Villemoes * Control are precisely those whose port registers have a
159949506a9bSRasmus Villemoes * Message Port bit in Port Control 1 and hence implement
160049506a9bSRasmus Villemoes * ->port_setup_message_port.
160149506a9bSRasmus Villemoes */
160249506a9bSRasmus Villemoes if (chip->info->ops->port_setup_message_port) {
1603c3a7d4adSVivien Didelot err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1604c3a7d4adSVivien Didelot if (err)
1605c3a7d4adSVivien Didelot return err;
160649506a9bSRasmus Villemoes }
1607c3a7d4adSVivien Didelot
1608a2ac29d2SVivien Didelot return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1609a2ac29d2SVivien Didelot }
1610a2ac29d2SVivien Didelot
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1611cd8da8bbSVivien Didelot static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1612cd8da8bbSVivien Didelot {
1613cd8da8bbSVivien Didelot int port;
1614cd8da8bbSVivien Didelot int err;
1615cd8da8bbSVivien Didelot
1616cd8da8bbSVivien Didelot if (!chip->info->ops->irl_init_all)
1617cd8da8bbSVivien Didelot return 0;
1618cd8da8bbSVivien Didelot
1619cd8da8bbSVivien Didelot for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1620cd8da8bbSVivien Didelot /* Disable ingress rate limiting by resetting all per port
1621cd8da8bbSVivien Didelot * ingress rate limit resources to their initial state.
1622cd8da8bbSVivien Didelot */
1623cd8da8bbSVivien Didelot err = chip->info->ops->irl_init_all(chip, port);
1624cd8da8bbSVivien Didelot if (err)
1625cd8da8bbSVivien Didelot return err;
1626cd8da8bbSVivien Didelot }
1627cd8da8bbSVivien Didelot
1628cd8da8bbSVivien Didelot return 0;
1629cd8da8bbSVivien Didelot }
1630cd8da8bbSVivien Didelot
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)163104a69a17SVivien Didelot static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
163204a69a17SVivien Didelot {
163304a69a17SVivien Didelot if (chip->info->ops->set_switch_mac) {
163404a69a17SVivien Didelot u8 addr[ETH_ALEN];
163504a69a17SVivien Didelot
163604a69a17SVivien Didelot eth_random_addr(addr);
163704a69a17SVivien Didelot
163804a69a17SVivien Didelot return chip->info->ops->set_switch_mac(chip, addr);
163904a69a17SVivien Didelot }
164004a69a17SVivien Didelot
164104a69a17SVivien Didelot return 0;
164204a69a17SVivien Didelot }
164304a69a17SVivien Didelot
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)164417a1594eSVivien Didelot static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
164517a1594eSVivien Didelot {
164657e661aaSTobias Waldekranz struct dsa_switch_tree *dst = chip->ds->dst;
164757e661aaSTobias Waldekranz struct dsa_switch *ds;
164857e661aaSTobias Waldekranz struct dsa_port *dp;
164917a1594eSVivien Didelot u16 pvlan = 0;
165017a1594eSVivien Didelot
165117a1594eSVivien Didelot if (!mv88e6xxx_has_pvt(chip))
1652d14939beSVivien Didelot return 0;
165317a1594eSVivien Didelot
165417a1594eSVivien Didelot /* Skip the local source device, which uses in-chip port VLAN */
165557e661aaSTobias Waldekranz if (dev != chip->ds->index) {
1656aec5ac88SVivien Didelot pvlan = mv88e6xxx_port_vlan(chip, dev, port);
165717a1594eSVivien Didelot
165857e661aaSTobias Waldekranz ds = dsa_switch_find(dst->index, dev);
165957e661aaSTobias Waldekranz dp = ds ? dsa_to_port(ds, port) : NULL;
1660dedd6a00SVladimir Oltean if (dp && dp->lag) {
166157e661aaSTobias Waldekranz /* As the PVT is used to limit flooding of
166257e661aaSTobias Waldekranz * FORWARD frames, which use the LAG ID as the
166357e661aaSTobias Waldekranz * source port, we must translate dev/port to
166457e661aaSTobias Waldekranz * the special "LAG device" in the PVT, using
16653d4a0a2aSVladimir Oltean * the LAG ID (one-based) as the port number
16663d4a0a2aSVladimir Oltean * (zero-based).
166757e661aaSTobias Waldekranz */
166878e70dbcSTobias Waldekranz dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1669dedd6a00SVladimir Oltean port = dsa_port_lag_id_get(dp) - 1;
167057e661aaSTobias Waldekranz }
167157e661aaSTobias Waldekranz }
167257e661aaSTobias Waldekranz
167317a1594eSVivien Didelot return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
167417a1594eSVivien Didelot }
167517a1594eSVivien Didelot
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)167681228996SVivien Didelot static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
167781228996SVivien Didelot {
167817a1594eSVivien Didelot int dev, port;
167917a1594eSVivien Didelot int err;
168017a1594eSVivien Didelot
168181228996SVivien Didelot if (!mv88e6xxx_has_pvt(chip))
168281228996SVivien Didelot return 0;
168381228996SVivien Didelot
168481228996SVivien Didelot /* Clear 5 Bit Port for usage with Marvell Link Street devices:
168581228996SVivien Didelot * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
168681228996SVivien Didelot */
168717a1594eSVivien Didelot err = mv88e6xxx_g2_misc_4_bit_port(chip);
168817a1594eSVivien Didelot if (err)
168917a1594eSVivien Didelot return err;
169017a1594eSVivien Didelot
169117a1594eSVivien Didelot for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
169217a1594eSVivien Didelot for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
169317a1594eSVivien Didelot err = mv88e6xxx_pvt_map(chip, dev, port);
169417a1594eSVivien Didelot if (err)
169517a1594eSVivien Didelot return err;
169617a1594eSVivien Didelot }
169717a1594eSVivien Didelot }
169817a1594eSVivien Didelot
169917a1594eSVivien Didelot return 0;
170081228996SVivien Didelot }
170181228996SVivien Didelot
mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1702acaf4d2eSTobias Waldekranz static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1703acaf4d2eSTobias Waldekranz u16 fid)
1704acaf4d2eSTobias Waldekranz {
1705acaf4d2eSTobias Waldekranz if (dsa_to_port(chip->ds, port)->lag)
1706acaf4d2eSTobias Waldekranz /* Hardware is incapable of fast-aging a LAG through a
1707acaf4d2eSTobias Waldekranz * regular ATU move operation. Until we have something
1708acaf4d2eSTobias Waldekranz * more fancy in place this is a no-op.
1709acaf4d2eSTobias Waldekranz */
1710acaf4d2eSTobias Waldekranz return -EOPNOTSUPP;
1711acaf4d2eSTobias Waldekranz
1712acaf4d2eSTobias Waldekranz return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1713acaf4d2eSTobias Waldekranz }
1714acaf4d2eSTobias Waldekranz
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1715749efcb8SVivien Didelot static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1716749efcb8SVivien Didelot {
1717749efcb8SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
1718749efcb8SVivien Didelot int err;
1719749efcb8SVivien Didelot
1720c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
1721acaf4d2eSTobias Waldekranz err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1722c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
1723749efcb8SVivien Didelot
1724749efcb8SVivien Didelot if (err)
1725acaf4d2eSTobias Waldekranz dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1726acaf4d2eSTobias Waldekranz port, err);
1727749efcb8SVivien Didelot }
1728749efcb8SVivien Didelot
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1729b486d7c9SVivien Didelot static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1730b486d7c9SVivien Didelot {
1731e545f865STobias Waldekranz if (!mv88e6xxx_max_vid(chip))
1732b486d7c9SVivien Didelot return 0;
1733b486d7c9SVivien Didelot
1734b486d7c9SVivien Didelot return mv88e6xxx_g1_vtu_flush(chip);
1735b486d7c9SVivien Didelot }
1736b486d7c9SVivien Didelot
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)173734065c58STobias Waldekranz static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1738f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry)
1739f1394b78SVivien Didelot {
174034065c58STobias Waldekranz int err;
174134065c58STobias Waldekranz
1742f1394b78SVivien Didelot if (!chip->info->ops->vtu_getnext)
1743f1394b78SVivien Didelot return -EOPNOTSUPP;
1744f1394b78SVivien Didelot
174534065c58STobias Waldekranz entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
174634065c58STobias Waldekranz entry->valid = false;
174734065c58STobias Waldekranz
174834065c58STobias Waldekranz err = chip->info->ops->vtu_getnext(chip, entry);
174934065c58STobias Waldekranz
175034065c58STobias Waldekranz if (entry->vid != vid)
175134065c58STobias Waldekranz entry->valid = false;
175234065c58STobias Waldekranz
175334065c58STobias Waldekranz return err;
1754f1394b78SVivien Didelot }
1755f1394b78SVivien Didelot
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1756830763b9SHans J. Schultz int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1757d89ef4b8STobias Waldekranz int (*cb)(struct mv88e6xxx_chip *chip,
1758d89ef4b8STobias Waldekranz const struct mv88e6xxx_vtu_entry *entry,
1759d89ef4b8STobias Waldekranz void *priv),
1760d89ef4b8STobias Waldekranz void *priv)
1761d89ef4b8STobias Waldekranz {
1762d89ef4b8STobias Waldekranz struct mv88e6xxx_vtu_entry entry = {
1763d89ef4b8STobias Waldekranz .vid = mv88e6xxx_max_vid(chip),
1764d89ef4b8STobias Waldekranz .valid = false,
1765d89ef4b8STobias Waldekranz };
1766d89ef4b8STobias Waldekranz int err;
1767d89ef4b8STobias Waldekranz
1768d89ef4b8STobias Waldekranz if (!chip->info->ops->vtu_getnext)
1769d89ef4b8STobias Waldekranz return -EOPNOTSUPP;
1770d89ef4b8STobias Waldekranz
1771d89ef4b8STobias Waldekranz do {
1772d89ef4b8STobias Waldekranz err = chip->info->ops->vtu_getnext(chip, &entry);
1773d89ef4b8STobias Waldekranz if (err)
1774d89ef4b8STobias Waldekranz return err;
1775d89ef4b8STobias Waldekranz
1776d89ef4b8STobias Waldekranz if (!entry.valid)
1777d89ef4b8STobias Waldekranz break;
1778d89ef4b8STobias Waldekranz
1779d89ef4b8STobias Waldekranz err = cb(chip, &entry, priv);
1780d89ef4b8STobias Waldekranz if (err)
1781d89ef4b8STobias Waldekranz return err;
1782d89ef4b8STobias Waldekranz } while (entry.vid < mv88e6xxx_max_vid(chip));
1783d89ef4b8STobias Waldekranz
1784d89ef4b8STobias Waldekranz return 0;
1785d89ef4b8STobias Waldekranz }
1786d89ef4b8STobias Waldekranz
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)17870ad5daf6SVivien Didelot static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
17880ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry)
17890ad5daf6SVivien Didelot {
17900ad5daf6SVivien Didelot if (!chip->info->ops->vtu_loadpurge)
17910ad5daf6SVivien Didelot return -EOPNOTSUPP;
17920ad5daf6SVivien Didelot
17930ad5daf6SVivien Didelot return chip->info->ops->vtu_loadpurge(chip, entry);
17940ad5daf6SVivien Didelot }
17950ad5daf6SVivien Didelot
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1796d89ef4b8STobias Waldekranz static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1797d89ef4b8STobias Waldekranz const struct mv88e6xxx_vtu_entry *entry,
1798d89ef4b8STobias Waldekranz void *_fid_bitmap)
1799d89ef4b8STobias Waldekranz {
1800d89ef4b8STobias Waldekranz unsigned long *fid_bitmap = _fid_bitmap;
1801d89ef4b8STobias Waldekranz
1802d89ef4b8STobias Waldekranz set_bit(entry->fid, fid_bitmap);
1803d89ef4b8STobias Waldekranz return 0;
1804d89ef4b8STobias Waldekranz }
1805d89ef4b8STobias Waldekranz
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)180690b6dbdfSAndrew Lunn int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1807fad09c73SVivien Didelot {
1808fad09c73SVivien Didelot bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1809fad09c73SVivien Didelot
1810d352b20fSTobias Waldekranz /* Every FID has an associated VID, so walking the VTU
1811d352b20fSTobias Waldekranz * will discover the full set of FIDs in use.
1812d352b20fSTobias Waldekranz */
1813d89ef4b8STobias Waldekranz return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
181490b6dbdfSAndrew Lunn }
181590b6dbdfSAndrew Lunn
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)181690b6dbdfSAndrew Lunn static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
181790b6dbdfSAndrew Lunn {
181890b6dbdfSAndrew Lunn DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
181990b6dbdfSAndrew Lunn int err;
182090b6dbdfSAndrew Lunn
182190b6dbdfSAndrew Lunn err = mv88e6xxx_fid_map(chip, fid_bitmap);
182290b6dbdfSAndrew Lunn if (err)
182390b6dbdfSAndrew Lunn return err;
182490b6dbdfSAndrew Lunn
1825d352b20fSTobias Waldekranz *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1826fad09c73SVivien Didelot if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1827fad09c73SVivien Didelot return -ENOSPC;
1828fad09c73SVivien Didelot
1829fad09c73SVivien Didelot /* Clear the database */
1830daefc943SVivien Didelot return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1831fad09c73SVivien Didelot }
1832fad09c73SVivien Didelot
mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_stu_entry * entry)183349c98c1dSTobias Waldekranz static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
183449c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry *entry)
183549c98c1dSTobias Waldekranz {
183649c98c1dSTobias Waldekranz if (!chip->info->ops->stu_loadpurge)
183749c98c1dSTobias Waldekranz return -EOPNOTSUPP;
183849c98c1dSTobias Waldekranz
183949c98c1dSTobias Waldekranz return chip->info->ops->stu_loadpurge(chip, entry);
184049c98c1dSTobias Waldekranz }
184149c98c1dSTobias Waldekranz
mv88e6xxx_stu_setup(struct mv88e6xxx_chip * chip)184249c98c1dSTobias Waldekranz static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
184349c98c1dSTobias Waldekranz {
184449c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry stu = {
184549c98c1dSTobias Waldekranz .valid = true,
184649c98c1dSTobias Waldekranz .sid = 0
184749c98c1dSTobias Waldekranz };
184849c98c1dSTobias Waldekranz
184949c98c1dSTobias Waldekranz if (!mv88e6xxx_has_stu(chip))
185049c98c1dSTobias Waldekranz return 0;
185149c98c1dSTobias Waldekranz
185249c98c1dSTobias Waldekranz /* Make sure that SID 0 is always valid. This is used by VTU
185349c98c1dSTobias Waldekranz * entries that do not make use of the STU, e.g. when creating
185449c98c1dSTobias Waldekranz * a VLAN upper on a port that is also part of a VLAN
185549c98c1dSTobias Waldekranz * filtering bridge.
185649c98c1dSTobias Waldekranz */
185749c98c1dSTobias Waldekranz return mv88e6xxx_stu_loadpurge(chip, &stu);
185849c98c1dSTobias Waldekranz }
185949c98c1dSTobias Waldekranz
mv88e6xxx_sid_get(struct mv88e6xxx_chip * chip,u8 * sid)1860acaf4d2eSTobias Waldekranz static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1861acaf4d2eSTobias Waldekranz {
1862acaf4d2eSTobias Waldekranz DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1863acaf4d2eSTobias Waldekranz struct mv88e6xxx_mst *mst;
1864acaf4d2eSTobias Waldekranz
1865acaf4d2eSTobias Waldekranz __set_bit(0, busy);
1866acaf4d2eSTobias Waldekranz
1867acaf4d2eSTobias Waldekranz list_for_each_entry(mst, &chip->msts, node)
1868acaf4d2eSTobias Waldekranz __set_bit(mst->stu.sid, busy);
1869acaf4d2eSTobias Waldekranz
1870acaf4d2eSTobias Waldekranz *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1871acaf4d2eSTobias Waldekranz
1872acaf4d2eSTobias Waldekranz return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1873acaf4d2eSTobias Waldekranz }
1874acaf4d2eSTobias Waldekranz
mv88e6xxx_mst_put(struct mv88e6xxx_chip * chip,u8 sid)1875acaf4d2eSTobias Waldekranz static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1876acaf4d2eSTobias Waldekranz {
1877acaf4d2eSTobias Waldekranz struct mv88e6xxx_mst *mst, *tmp;
1878acaf4d2eSTobias Waldekranz int err;
1879acaf4d2eSTobias Waldekranz
1880acaf4d2eSTobias Waldekranz if (!sid)
1881acaf4d2eSTobias Waldekranz return 0;
1882acaf4d2eSTobias Waldekranz
1883acaf4d2eSTobias Waldekranz list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1884acaf4d2eSTobias Waldekranz if (mst->stu.sid != sid)
1885acaf4d2eSTobias Waldekranz continue;
1886acaf4d2eSTobias Waldekranz
1887acaf4d2eSTobias Waldekranz if (!refcount_dec_and_test(&mst->refcnt))
1888acaf4d2eSTobias Waldekranz return 0;
1889acaf4d2eSTobias Waldekranz
1890acaf4d2eSTobias Waldekranz mst->stu.valid = false;
1891acaf4d2eSTobias Waldekranz err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1892acaf4d2eSTobias Waldekranz if (err) {
1893acaf4d2eSTobias Waldekranz refcount_set(&mst->refcnt, 1);
1894acaf4d2eSTobias Waldekranz return err;
1895acaf4d2eSTobias Waldekranz }
1896acaf4d2eSTobias Waldekranz
1897acaf4d2eSTobias Waldekranz list_del(&mst->node);
1898acaf4d2eSTobias Waldekranz kfree(mst);
1899acaf4d2eSTobias Waldekranz return 0;
1900acaf4d2eSTobias Waldekranz }
1901acaf4d2eSTobias Waldekranz
1902acaf4d2eSTobias Waldekranz return -ENOENT;
1903acaf4d2eSTobias Waldekranz }
1904acaf4d2eSTobias Waldekranz
mv88e6xxx_mst_get(struct mv88e6xxx_chip * chip,struct net_device * br,u16 msti,u8 * sid)1905acaf4d2eSTobias Waldekranz static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1906acaf4d2eSTobias Waldekranz u16 msti, u8 *sid)
1907acaf4d2eSTobias Waldekranz {
1908acaf4d2eSTobias Waldekranz struct mv88e6xxx_mst *mst;
1909acaf4d2eSTobias Waldekranz int err, i;
1910acaf4d2eSTobias Waldekranz
1911acaf4d2eSTobias Waldekranz if (!mv88e6xxx_has_stu(chip)) {
1912acaf4d2eSTobias Waldekranz err = -EOPNOTSUPP;
1913acaf4d2eSTobias Waldekranz goto err;
1914acaf4d2eSTobias Waldekranz }
1915acaf4d2eSTobias Waldekranz
1916acaf4d2eSTobias Waldekranz if (!msti) {
1917acaf4d2eSTobias Waldekranz *sid = 0;
1918acaf4d2eSTobias Waldekranz return 0;
1919acaf4d2eSTobias Waldekranz }
1920acaf4d2eSTobias Waldekranz
1921acaf4d2eSTobias Waldekranz list_for_each_entry(mst, &chip->msts, node) {
1922acaf4d2eSTobias Waldekranz if (mst->br == br && mst->msti == msti) {
1923acaf4d2eSTobias Waldekranz refcount_inc(&mst->refcnt);
1924acaf4d2eSTobias Waldekranz *sid = mst->stu.sid;
1925acaf4d2eSTobias Waldekranz return 0;
1926acaf4d2eSTobias Waldekranz }
1927acaf4d2eSTobias Waldekranz }
1928acaf4d2eSTobias Waldekranz
1929acaf4d2eSTobias Waldekranz err = mv88e6xxx_sid_get(chip, sid);
1930acaf4d2eSTobias Waldekranz if (err)
1931acaf4d2eSTobias Waldekranz goto err;
1932acaf4d2eSTobias Waldekranz
1933acaf4d2eSTobias Waldekranz mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1934acaf4d2eSTobias Waldekranz if (!mst) {
1935acaf4d2eSTobias Waldekranz err = -ENOMEM;
1936acaf4d2eSTobias Waldekranz goto err;
1937acaf4d2eSTobias Waldekranz }
1938acaf4d2eSTobias Waldekranz
1939acaf4d2eSTobias Waldekranz INIT_LIST_HEAD(&mst->node);
1940acaf4d2eSTobias Waldekranz refcount_set(&mst->refcnt, 1);
1941acaf4d2eSTobias Waldekranz mst->br = br;
1942acaf4d2eSTobias Waldekranz mst->msti = msti;
1943acaf4d2eSTobias Waldekranz mst->stu.valid = true;
1944acaf4d2eSTobias Waldekranz mst->stu.sid = *sid;
1945acaf4d2eSTobias Waldekranz
1946acaf4d2eSTobias Waldekranz /* The bridge starts out all ports in the disabled state. But
1947acaf4d2eSTobias Waldekranz * a STU state of disabled means to go by the port-global
1948acaf4d2eSTobias Waldekranz * state. So we set all user port's initial state to blocking,
1949acaf4d2eSTobias Waldekranz * to match the bridge's behavior.
1950acaf4d2eSTobias Waldekranz */
1951acaf4d2eSTobias Waldekranz for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1952acaf4d2eSTobias Waldekranz mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1953acaf4d2eSTobias Waldekranz MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1954acaf4d2eSTobias Waldekranz MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1955acaf4d2eSTobias Waldekranz
1956acaf4d2eSTobias Waldekranz err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1957acaf4d2eSTobias Waldekranz if (err)
1958acaf4d2eSTobias Waldekranz goto err_free;
1959acaf4d2eSTobias Waldekranz
1960acaf4d2eSTobias Waldekranz list_add_tail(&mst->node, &chip->msts);
1961acaf4d2eSTobias Waldekranz return 0;
1962acaf4d2eSTobias Waldekranz
1963acaf4d2eSTobias Waldekranz err_free:
1964acaf4d2eSTobias Waldekranz kfree(mst);
1965acaf4d2eSTobias Waldekranz err:
1966acaf4d2eSTobias Waldekranz return err;
1967acaf4d2eSTobias Waldekranz }
1968acaf4d2eSTobias Waldekranz
mv88e6xxx_port_mst_state_set(struct dsa_switch * ds,int port,const struct switchdev_mst_state * st)1969acaf4d2eSTobias Waldekranz static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1970acaf4d2eSTobias Waldekranz const struct switchdev_mst_state *st)
1971acaf4d2eSTobias Waldekranz {
1972acaf4d2eSTobias Waldekranz struct dsa_port *dp = dsa_to_port(ds, port);
1973acaf4d2eSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
1974acaf4d2eSTobias Waldekranz struct mv88e6xxx_mst *mst;
1975acaf4d2eSTobias Waldekranz u8 state;
1976acaf4d2eSTobias Waldekranz int err;
1977acaf4d2eSTobias Waldekranz
1978acaf4d2eSTobias Waldekranz if (!mv88e6xxx_has_stu(chip))
1979acaf4d2eSTobias Waldekranz return -EOPNOTSUPP;
1980acaf4d2eSTobias Waldekranz
1981acaf4d2eSTobias Waldekranz switch (st->state) {
1982acaf4d2eSTobias Waldekranz case BR_STATE_DISABLED:
1983acaf4d2eSTobias Waldekranz case BR_STATE_BLOCKING:
1984acaf4d2eSTobias Waldekranz case BR_STATE_LISTENING:
1985acaf4d2eSTobias Waldekranz state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1986acaf4d2eSTobias Waldekranz break;
1987acaf4d2eSTobias Waldekranz case BR_STATE_LEARNING:
1988acaf4d2eSTobias Waldekranz state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1989acaf4d2eSTobias Waldekranz break;
1990acaf4d2eSTobias Waldekranz case BR_STATE_FORWARDING:
1991acaf4d2eSTobias Waldekranz state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1992acaf4d2eSTobias Waldekranz break;
1993acaf4d2eSTobias Waldekranz default:
1994acaf4d2eSTobias Waldekranz return -EINVAL;
1995acaf4d2eSTobias Waldekranz }
1996acaf4d2eSTobias Waldekranz
1997acaf4d2eSTobias Waldekranz list_for_each_entry(mst, &chip->msts, node) {
1998acaf4d2eSTobias Waldekranz if (mst->br == dsa_port_bridge_dev_get(dp) &&
1999acaf4d2eSTobias Waldekranz mst->msti == st->msti) {
2000acaf4d2eSTobias Waldekranz if (mst->stu.state[port] == state)
2001acaf4d2eSTobias Waldekranz return 0;
2002acaf4d2eSTobias Waldekranz
2003acaf4d2eSTobias Waldekranz mst->stu.state[port] = state;
2004acaf4d2eSTobias Waldekranz mv88e6xxx_reg_lock(chip);
2005acaf4d2eSTobias Waldekranz err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2006acaf4d2eSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
2007acaf4d2eSTobias Waldekranz return err;
2008acaf4d2eSTobias Waldekranz }
2009acaf4d2eSTobias Waldekranz }
2010acaf4d2eSTobias Waldekranz
2011acaf4d2eSTobias Waldekranz return -ENOENT;
2012acaf4d2eSTobias Waldekranz }
2013acaf4d2eSTobias Waldekranz
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)2014fad09c73SVivien Didelot static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2015b7a9e0daSVladimir Oltean u16 vid)
2016fad09c73SVivien Didelot {
20170493fa79SVladimir Oltean struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
201804bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2019425d2d37SVivien Didelot struct mv88e6xxx_vtu_entry vlan;
20200493fa79SVladimir Oltean int err;
2021fad09c73SVivien Didelot
2022db06ae41SAndrew Lunn /* DSA and CPU ports have to be members of multiple vlans */
20230493fa79SVladimir Oltean if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2024db06ae41SAndrew Lunn return 0;
2025db06ae41SAndrew Lunn
202634065c58STobias Waldekranz err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2027fad09c73SVivien Didelot if (err)
20287095a4c4SVivien Didelot return err;
2029fad09c73SVivien Didelot
2030fad09c73SVivien Didelot if (!vlan.valid)
2031b7a9e0daSVladimir Oltean return 0;
2032fad09c73SVivien Didelot
20330493fa79SVladimir Oltean dsa_switch_for_each_user_port(other_dp, ds) {
203441fb0cf1SVladimir Oltean struct net_device *other_br;
203541fb0cf1SVladimir Oltean
20360493fa79SVladimir Oltean if (vlan.member[other_dp->index] ==
20377ec60d6eSVivien Didelot MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2038fad09c73SVivien Didelot continue;
2039fad09c73SVivien Didelot
204041fb0cf1SVladimir Oltean if (dsa_port_bridge_same(dp, other_dp))
2041fad09c73SVivien Didelot break; /* same bridge, check next VLAN */
2042fad09c73SVivien Didelot
204341fb0cf1SVladimir Oltean other_br = dsa_port_bridge_dev_get(other_dp);
204441fb0cf1SVladimir Oltean if (!other_br)
204566e2809dSAndrew Lunn continue;
204666e2809dSAndrew Lunn
2047743fcc28SAndrew Lunn dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
204841fb0cf1SVladimir Oltean port, vlan.vid, other_dp->index, netdev_name(other_br));
20497095a4c4SVivien Didelot return -EOPNOTSUPP;
2050fad09c73SVivien Didelot }
2051fad09c73SVivien Didelot
20527095a4c4SVivien Didelot return 0;
2053fad09c73SVivien Didelot }
2054fad09c73SVivien Didelot
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)20558b6836d8SVladimir Oltean static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
20568b6836d8SVladimir Oltean {
20578b6836d8SVladimir Oltean struct dsa_port *dp = dsa_to_port(chip->ds, port);
205841fb0cf1SVladimir Oltean struct net_device *br = dsa_port_bridge_dev_get(dp);
20598b6836d8SVladimir Oltean struct mv88e6xxx_port *p = &chip->ports[port];
20605bded825SVladimir Oltean u16 pvid = MV88E6XXX_VID_STANDALONE;
20618b6836d8SVladimir Oltean bool drop_untagged = false;
20628b6836d8SVladimir Oltean int err;
20638b6836d8SVladimir Oltean
206441fb0cf1SVladimir Oltean if (br) {
206541fb0cf1SVladimir Oltean if (br_vlan_enabled(br)) {
20668b6836d8SVladimir Oltean pvid = p->bridge_pvid.vid;
20678b6836d8SVladimir Oltean drop_untagged = !p->bridge_pvid.valid;
20685bded825SVladimir Oltean } else {
20695bded825SVladimir Oltean pvid = MV88E6XXX_VID_BRIDGED;
20705bded825SVladimir Oltean }
20718b6836d8SVladimir Oltean }
20728b6836d8SVladimir Oltean
20738b6836d8SVladimir Oltean err = mv88e6xxx_port_set_pvid(chip, port, pvid);
20748b6836d8SVladimir Oltean if (err)
20758b6836d8SVladimir Oltean return err;
20768b6836d8SVladimir Oltean
20778b6836d8SVladimir Oltean return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
20788b6836d8SVladimir Oltean }
20798b6836d8SVladimir Oltean
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)2080fad09c73SVivien Didelot static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
208189153ed6SVladimir Oltean bool vlan_filtering,
208289153ed6SVladimir Oltean struct netlink_ext_ack *extack)
2083fad09c73SVivien Didelot {
208404bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
208581c6edb2SVivien Didelot u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
208681c6edb2SVivien Didelot MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
20870e7b9925SAndrew Lunn int err;
2088fad09c73SVivien Didelot
2089bae33f2bSVladimir Oltean if (!mv88e6xxx_max_vid(chip))
2090bae33f2bSVladimir Oltean return -EOPNOTSUPP;
2091fad09c73SVivien Didelot
2092c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
20938b6836d8SVladimir Oltean
2094385a0995SVivien Didelot err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
20958b6836d8SVladimir Oltean if (err)
20968b6836d8SVladimir Oltean goto unlock;
20978b6836d8SVladimir Oltean
20988b6836d8SVladimir Oltean err = mv88e6xxx_port_commit_pvid(chip, port);
20998b6836d8SVladimir Oltean if (err)
21008b6836d8SVladimir Oltean goto unlock;
21018b6836d8SVladimir Oltean
21028b6836d8SVladimir Oltean unlock:
2103c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2104fad09c73SVivien Didelot
21050e7b9925SAndrew Lunn return err;
2106fad09c73SVivien Didelot }
2107fad09c73SVivien Didelot
2108fad09c73SVivien Didelot static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2109fad09c73SVivien Didelot mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
211080e02360SVivien Didelot const struct switchdev_obj_port_vlan *vlan)
2111fad09c73SVivien Didelot {
211204bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2113fad09c73SVivien Didelot int err;
2114fad09c73SVivien Didelot
2115e545f865STobias Waldekranz if (!mv88e6xxx_max_vid(chip))
2116fad09c73SVivien Didelot return -EOPNOTSUPP;
2117fad09c73SVivien Didelot
2118fad09c73SVivien Didelot /* If the requested port doesn't belong to the same bridge as the VLAN
2119fad09c73SVivien Didelot * members, do not support it (yet) and fallback to software VLAN.
2120fad09c73SVivien Didelot */
21217095a4c4SVivien Didelot mv88e6xxx_reg_lock(chip);
2122b7a9e0daSVladimir Oltean err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
21237095a4c4SVivien Didelot mv88e6xxx_reg_unlock(chip);
2124fad09c73SVivien Didelot
21257095a4c4SVivien Didelot return err;
2126fad09c73SVivien Didelot }
2127fad09c73SVivien Didelot
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)2128a4c93ae1SAndrew Lunn static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2129a4c93ae1SAndrew Lunn const unsigned char *addr, u16 vid,
2130a4c93ae1SAndrew Lunn u8 state)
2131a4c93ae1SAndrew Lunn {
2132a4c93ae1SAndrew Lunn struct mv88e6xxx_atu_entry entry;
21335ef8d249SVivien Didelot struct mv88e6xxx_vtu_entry vlan;
21345ef8d249SVivien Didelot u16 fid;
2135a4c93ae1SAndrew Lunn int err;
2136a4c93ae1SAndrew Lunn
21375bded825SVladimir Oltean /* Ports have two private address databases: one for when the port is
21385bded825SVladimir Oltean * standalone and one for when the port is under a bridge and the
21395bded825SVladimir Oltean * 802.1Q mode is disabled. When the port is standalone, DSA wants its
21405bded825SVladimir Oltean * address database to remain 100% empty, so we never load an ATU entry
21415bded825SVladimir Oltean * into a standalone port's database. Therefore, translate the null
21425bded825SVladimir Oltean * VLAN ID into the port's database used for VLAN-unaware bridging.
21435bded825SVladimir Oltean */
21445ef8d249SVivien Didelot if (vid == 0) {
21455bded825SVladimir Oltean fid = MV88E6XXX_FID_BRIDGED;
21465ef8d249SVivien Didelot } else {
214734065c58STobias Waldekranz err = mv88e6xxx_vtu_get(chip, vid, &vlan);
21485ef8d249SVivien Didelot if (err)
21495ef8d249SVivien Didelot return err;
21505ef8d249SVivien Didelot
21515ef8d249SVivien Didelot /* switchdev expects -EOPNOTSUPP to honor software VLANs */
215234065c58STobias Waldekranz if (!vlan.valid)
21535ef8d249SVivien Didelot return -EOPNOTSUPP;
21545ef8d249SVivien Didelot
21555ef8d249SVivien Didelot fid = vlan.fid;
21565ef8d249SVivien Didelot }
2157a4c93ae1SAndrew Lunn
2158d8291a95SVivien Didelot entry.state = 0;
2159a4c93ae1SAndrew Lunn ether_addr_copy(entry.mac, addr);
2160a4c93ae1SAndrew Lunn eth_addr_dec(entry.mac);
2161a4c93ae1SAndrew Lunn
21625ef8d249SVivien Didelot err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2163a4c93ae1SAndrew Lunn if (err)
2164a4c93ae1SAndrew Lunn return err;
2165a4c93ae1SAndrew Lunn
2166a4c93ae1SAndrew Lunn /* Initialize a fresh ATU entry if it isn't found */
2167d8291a95SVivien Didelot if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2168a4c93ae1SAndrew Lunn memset(&entry, 0, sizeof(entry));
2169a4c93ae1SAndrew Lunn ether_addr_copy(entry.mac, addr);
2170a4c93ae1SAndrew Lunn }
2171a4c93ae1SAndrew Lunn
2172a4c93ae1SAndrew Lunn /* Purge the ATU entry only if no port is using it anymore */
2173d8291a95SVivien Didelot if (!state) {
2174a4c93ae1SAndrew Lunn entry.portvec &= ~BIT(port);
2175a4c93ae1SAndrew Lunn if (!entry.portvec)
2176d8291a95SVivien Didelot entry.state = 0;
2177a4c93ae1SAndrew Lunn } else {
2178f72f2fb8SDENG Qingfang if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2179f72f2fb8SDENG Qingfang entry.portvec = BIT(port);
2180f72f2fb8SDENG Qingfang else
2181a4c93ae1SAndrew Lunn entry.portvec |= BIT(port);
2182f72f2fb8SDENG Qingfang
2183a4c93ae1SAndrew Lunn entry.state = state;
2184a4c93ae1SAndrew Lunn }
2185a4c93ae1SAndrew Lunn
21865ef8d249SVivien Didelot return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2187a4c93ae1SAndrew Lunn }
2188a4c93ae1SAndrew Lunn
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)2189da7dc875SVivien Didelot static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2190da7dc875SVivien Didelot const struct mv88e6xxx_policy *policy)
2191da7dc875SVivien Didelot {
2192da7dc875SVivien Didelot enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2193da7dc875SVivien Didelot enum mv88e6xxx_policy_action action = policy->action;
2194da7dc875SVivien Didelot const u8 *addr = policy->addr;
2195da7dc875SVivien Didelot u16 vid = policy->vid;
2196da7dc875SVivien Didelot u8 state;
2197da7dc875SVivien Didelot int err;
2198da7dc875SVivien Didelot int id;
2199da7dc875SVivien Didelot
2200da7dc875SVivien Didelot if (!chip->info->ops->port_set_policy)
2201da7dc875SVivien Didelot return -EOPNOTSUPP;
2202da7dc875SVivien Didelot
2203da7dc875SVivien Didelot switch (mapping) {
2204da7dc875SVivien Didelot case MV88E6XXX_POLICY_MAPPING_DA:
2205da7dc875SVivien Didelot case MV88E6XXX_POLICY_MAPPING_SA:
2206da7dc875SVivien Didelot if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2207da7dc875SVivien Didelot state = 0; /* Dissociate the port and address */
2208da7dc875SVivien Didelot else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2209da7dc875SVivien Didelot is_multicast_ether_addr(addr))
2210da7dc875SVivien Didelot state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2211da7dc875SVivien Didelot else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2212da7dc875SVivien Didelot is_unicast_ether_addr(addr))
2213da7dc875SVivien Didelot state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2214da7dc875SVivien Didelot else
2215da7dc875SVivien Didelot return -EOPNOTSUPP;
2216da7dc875SVivien Didelot
2217da7dc875SVivien Didelot err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2218da7dc875SVivien Didelot state);
2219da7dc875SVivien Didelot if (err)
2220da7dc875SVivien Didelot return err;
2221da7dc875SVivien Didelot break;
2222da7dc875SVivien Didelot default:
2223da7dc875SVivien Didelot return -EOPNOTSUPP;
2224da7dc875SVivien Didelot }
2225da7dc875SVivien Didelot
2226da7dc875SVivien Didelot /* Skip the port's policy clearing if the mapping is still in use */
2227da7dc875SVivien Didelot if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2228da7dc875SVivien Didelot idr_for_each_entry(&chip->policies, policy, id)
2229da7dc875SVivien Didelot if (policy->port == port &&
2230da7dc875SVivien Didelot policy->mapping == mapping &&
2231da7dc875SVivien Didelot policy->action != action)
2232da7dc875SVivien Didelot return 0;
2233da7dc875SVivien Didelot
2234da7dc875SVivien Didelot return chip->info->ops->port_set_policy(chip, port, mapping, action);
2235da7dc875SVivien Didelot }
2236da7dc875SVivien Didelot
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)2237da7dc875SVivien Didelot static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2238da7dc875SVivien Didelot struct ethtool_rx_flow_spec *fs)
2239da7dc875SVivien Didelot {
2240da7dc875SVivien Didelot struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2241da7dc875SVivien Didelot struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2242da7dc875SVivien Didelot enum mv88e6xxx_policy_mapping mapping;
2243da7dc875SVivien Didelot enum mv88e6xxx_policy_action action;
2244da7dc875SVivien Didelot struct mv88e6xxx_policy *policy;
2245da7dc875SVivien Didelot u16 vid = 0;
2246da7dc875SVivien Didelot u8 *addr;
2247da7dc875SVivien Didelot int err;
2248da7dc875SVivien Didelot int id;
2249da7dc875SVivien Didelot
2250da7dc875SVivien Didelot if (fs->location != RX_CLS_LOC_ANY)
2251da7dc875SVivien Didelot return -EINVAL;
2252da7dc875SVivien Didelot
2253da7dc875SVivien Didelot if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2254da7dc875SVivien Didelot action = MV88E6XXX_POLICY_ACTION_DISCARD;
2255da7dc875SVivien Didelot else
2256da7dc875SVivien Didelot return -EOPNOTSUPP;
2257da7dc875SVivien Didelot
2258da7dc875SVivien Didelot switch (fs->flow_type & ~FLOW_EXT) {
2259da7dc875SVivien Didelot case ETHER_FLOW:
2260da7dc875SVivien Didelot if (!is_zero_ether_addr(mac_mask->h_dest) &&
2261da7dc875SVivien Didelot is_zero_ether_addr(mac_mask->h_source)) {
2262da7dc875SVivien Didelot mapping = MV88E6XXX_POLICY_MAPPING_DA;
2263da7dc875SVivien Didelot addr = mac_entry->h_dest;
2264da7dc875SVivien Didelot } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2265da7dc875SVivien Didelot !is_zero_ether_addr(mac_mask->h_source)) {
2266da7dc875SVivien Didelot mapping = MV88E6XXX_POLICY_MAPPING_SA;
2267da7dc875SVivien Didelot addr = mac_entry->h_source;
2268da7dc875SVivien Didelot } else {
2269da7dc875SVivien Didelot /* Cannot support DA and SA mapping in the same rule */
2270da7dc875SVivien Didelot return -EOPNOTSUPP;
2271da7dc875SVivien Didelot }
2272da7dc875SVivien Didelot break;
2273da7dc875SVivien Didelot default:
2274da7dc875SVivien Didelot return -EOPNOTSUPP;
2275da7dc875SVivien Didelot }
2276da7dc875SVivien Didelot
2277da7dc875SVivien Didelot if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
227804844280SAndrew Lunn if (fs->m_ext.vlan_tci != htons(0xffff))
2279da7dc875SVivien Didelot return -EOPNOTSUPP;
2280da7dc875SVivien Didelot vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2281da7dc875SVivien Didelot }
2282da7dc875SVivien Didelot
2283da7dc875SVivien Didelot idr_for_each_entry(&chip->policies, policy, id) {
2284da7dc875SVivien Didelot if (policy->port == port && policy->mapping == mapping &&
2285da7dc875SVivien Didelot policy->action == action && policy->vid == vid &&
2286da7dc875SVivien Didelot ether_addr_equal(policy->addr, addr))
2287da7dc875SVivien Didelot return -EEXIST;
2288da7dc875SVivien Didelot }
2289da7dc875SVivien Didelot
2290da7dc875SVivien Didelot policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2291da7dc875SVivien Didelot if (!policy)
2292da7dc875SVivien Didelot return -ENOMEM;
2293da7dc875SVivien Didelot
2294da7dc875SVivien Didelot fs->location = 0;
2295da7dc875SVivien Didelot err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2296da7dc875SVivien Didelot GFP_KERNEL);
2297da7dc875SVivien Didelot if (err) {
2298da7dc875SVivien Didelot devm_kfree(chip->dev, policy);
2299da7dc875SVivien Didelot return err;
2300da7dc875SVivien Didelot }
2301da7dc875SVivien Didelot
2302da7dc875SVivien Didelot memcpy(&policy->fs, fs, sizeof(*fs));
2303da7dc875SVivien Didelot ether_addr_copy(policy->addr, addr);
2304da7dc875SVivien Didelot policy->mapping = mapping;
2305da7dc875SVivien Didelot policy->action = action;
2306da7dc875SVivien Didelot policy->port = port;
2307da7dc875SVivien Didelot policy->vid = vid;
2308da7dc875SVivien Didelot
2309da7dc875SVivien Didelot err = mv88e6xxx_policy_apply(chip, port, policy);
2310da7dc875SVivien Didelot if (err) {
2311da7dc875SVivien Didelot idr_remove(&chip->policies, fs->location);
2312da7dc875SVivien Didelot devm_kfree(chip->dev, policy);
2313da7dc875SVivien Didelot return err;
2314da7dc875SVivien Didelot }
2315da7dc875SVivien Didelot
2316da7dc875SVivien Didelot return 0;
2317da7dc875SVivien Didelot }
2318da7dc875SVivien Didelot
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)2319da7dc875SVivien Didelot static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2320da7dc875SVivien Didelot struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2321da7dc875SVivien Didelot {
2322da7dc875SVivien Didelot struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2323da7dc875SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2324da7dc875SVivien Didelot struct mv88e6xxx_policy *policy;
2325da7dc875SVivien Didelot int err;
2326da7dc875SVivien Didelot int id;
2327da7dc875SVivien Didelot
2328da7dc875SVivien Didelot mv88e6xxx_reg_lock(chip);
2329da7dc875SVivien Didelot
2330da7dc875SVivien Didelot switch (rxnfc->cmd) {
2331da7dc875SVivien Didelot case ETHTOOL_GRXCLSRLCNT:
2332da7dc875SVivien Didelot rxnfc->data = 0;
2333da7dc875SVivien Didelot rxnfc->data |= RX_CLS_LOC_SPECIAL;
2334da7dc875SVivien Didelot rxnfc->rule_cnt = 0;
2335da7dc875SVivien Didelot idr_for_each_entry(&chip->policies, policy, id)
2336da7dc875SVivien Didelot if (policy->port == port)
2337da7dc875SVivien Didelot rxnfc->rule_cnt++;
2338da7dc875SVivien Didelot err = 0;
2339da7dc875SVivien Didelot break;
2340da7dc875SVivien Didelot case ETHTOOL_GRXCLSRULE:
2341da7dc875SVivien Didelot err = -ENOENT;
2342da7dc875SVivien Didelot policy = idr_find(&chip->policies, fs->location);
2343da7dc875SVivien Didelot if (policy) {
2344da7dc875SVivien Didelot memcpy(fs, &policy->fs, sizeof(*fs));
2345da7dc875SVivien Didelot err = 0;
2346da7dc875SVivien Didelot }
2347da7dc875SVivien Didelot break;
2348da7dc875SVivien Didelot case ETHTOOL_GRXCLSRLALL:
2349da7dc875SVivien Didelot rxnfc->data = 0;
2350da7dc875SVivien Didelot rxnfc->rule_cnt = 0;
2351da7dc875SVivien Didelot idr_for_each_entry(&chip->policies, policy, id)
2352da7dc875SVivien Didelot if (policy->port == port)
2353da7dc875SVivien Didelot rule_locs[rxnfc->rule_cnt++] = id;
2354da7dc875SVivien Didelot err = 0;
2355da7dc875SVivien Didelot break;
2356da7dc875SVivien Didelot default:
2357da7dc875SVivien Didelot err = -EOPNOTSUPP;
2358da7dc875SVivien Didelot break;
2359da7dc875SVivien Didelot }
2360da7dc875SVivien Didelot
2361da7dc875SVivien Didelot mv88e6xxx_reg_unlock(chip);
2362da7dc875SVivien Didelot
2363da7dc875SVivien Didelot return err;
2364da7dc875SVivien Didelot }
2365da7dc875SVivien Didelot
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2366da7dc875SVivien Didelot static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2367da7dc875SVivien Didelot struct ethtool_rxnfc *rxnfc)
2368da7dc875SVivien Didelot {
2369da7dc875SVivien Didelot struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2370da7dc875SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2371da7dc875SVivien Didelot struct mv88e6xxx_policy *policy;
2372da7dc875SVivien Didelot int err;
2373da7dc875SVivien Didelot
2374da7dc875SVivien Didelot mv88e6xxx_reg_lock(chip);
2375da7dc875SVivien Didelot
2376da7dc875SVivien Didelot switch (rxnfc->cmd) {
2377da7dc875SVivien Didelot case ETHTOOL_SRXCLSRLINS:
2378da7dc875SVivien Didelot err = mv88e6xxx_policy_insert(chip, port, fs);
2379da7dc875SVivien Didelot break;
2380da7dc875SVivien Didelot case ETHTOOL_SRXCLSRLDEL:
2381da7dc875SVivien Didelot err = -ENOENT;
2382da7dc875SVivien Didelot policy = idr_remove(&chip->policies, fs->location);
2383da7dc875SVivien Didelot if (policy) {
2384da7dc875SVivien Didelot policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2385da7dc875SVivien Didelot err = mv88e6xxx_policy_apply(chip, port, policy);
2386da7dc875SVivien Didelot devm_kfree(chip->dev, policy);
2387da7dc875SVivien Didelot }
2388da7dc875SVivien Didelot break;
2389da7dc875SVivien Didelot default:
2390da7dc875SVivien Didelot err = -EOPNOTSUPP;
2391da7dc875SVivien Didelot break;
2392da7dc875SVivien Didelot }
2393da7dc875SVivien Didelot
2394da7dc875SVivien Didelot mv88e6xxx_reg_unlock(chip);
2395da7dc875SVivien Didelot
2396da7dc875SVivien Didelot return err;
2397da7dc875SVivien Didelot }
2398da7dc875SVivien Didelot
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)239987fa886eSAndrew Lunn static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
240087fa886eSAndrew Lunn u16 vid)
240187fa886eSAndrew Lunn {
240287fa886eSAndrew Lunn u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
24030806dd46STobias Waldekranz u8 broadcast[ETH_ALEN];
24040806dd46STobias Waldekranz
24050806dd46STobias Waldekranz eth_broadcast_addr(broadcast);
240687fa886eSAndrew Lunn
240787fa886eSAndrew Lunn return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
240887fa886eSAndrew Lunn }
240987fa886eSAndrew Lunn
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)241087fa886eSAndrew Lunn static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
241187fa886eSAndrew Lunn {
241287fa886eSAndrew Lunn int port;
241387fa886eSAndrew Lunn int err;
241487fa886eSAndrew Lunn
241587fa886eSAndrew Lunn for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
24168d1d8298STobias Waldekranz struct dsa_port *dp = dsa_to_port(chip->ds, port);
24178d1d8298STobias Waldekranz struct net_device *brport;
24188d1d8298STobias Waldekranz
24198d1d8298STobias Waldekranz if (dsa_is_unused_port(chip->ds, port))
24208d1d8298STobias Waldekranz continue;
24218d1d8298STobias Waldekranz
24228d1d8298STobias Waldekranz brport = dsa_port_to_bridge_port(dp);
24238d1d8298STobias Waldekranz if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
24248d1d8298STobias Waldekranz /* Skip bridged user ports where broadcast
24258d1d8298STobias Waldekranz * flooding is disabled.
24268d1d8298STobias Waldekranz */
24278d1d8298STobias Waldekranz continue;
24288d1d8298STobias Waldekranz
242987fa886eSAndrew Lunn err = mv88e6xxx_port_add_broadcast(chip, port, vid);
243087fa886eSAndrew Lunn if (err)
243187fa886eSAndrew Lunn return err;
243287fa886eSAndrew Lunn }
243387fa886eSAndrew Lunn
243487fa886eSAndrew Lunn return 0;
243587fa886eSAndrew Lunn }
243687fa886eSAndrew Lunn
24378d1d8298STobias Waldekranz struct mv88e6xxx_port_broadcast_sync_ctx {
24388d1d8298STobias Waldekranz int port;
24398d1d8298STobias Waldekranz bool flood;
24408d1d8298STobias Waldekranz };
24418d1d8298STobias Waldekranz
24428d1d8298STobias Waldekranz static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)24438d1d8298STobias Waldekranz mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
24448d1d8298STobias Waldekranz const struct mv88e6xxx_vtu_entry *vlan,
24458d1d8298STobias Waldekranz void *_ctx)
24468d1d8298STobias Waldekranz {
24478d1d8298STobias Waldekranz struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
24488d1d8298STobias Waldekranz u8 broadcast[ETH_ALEN];
24498d1d8298STobias Waldekranz u8 state;
24508d1d8298STobias Waldekranz
24518d1d8298STobias Waldekranz if (ctx->flood)
24528d1d8298STobias Waldekranz state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
24538d1d8298STobias Waldekranz else
24548d1d8298STobias Waldekranz state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
24558d1d8298STobias Waldekranz
24568d1d8298STobias Waldekranz eth_broadcast_addr(broadcast);
24578d1d8298STobias Waldekranz
24588d1d8298STobias Waldekranz return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
24598d1d8298STobias Waldekranz vlan->vid, state);
24608d1d8298STobias Waldekranz }
24618d1d8298STobias Waldekranz
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)24628d1d8298STobias Waldekranz static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
24638d1d8298STobias Waldekranz bool flood)
24648d1d8298STobias Waldekranz {
24658d1d8298STobias Waldekranz struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
24668d1d8298STobias Waldekranz .port = port,
24678d1d8298STobias Waldekranz .flood = flood,
24688d1d8298STobias Waldekranz };
24698d1d8298STobias Waldekranz struct mv88e6xxx_vtu_entry vid0 = {
24708d1d8298STobias Waldekranz .vid = 0,
24718d1d8298STobias Waldekranz };
24728d1d8298STobias Waldekranz int err;
24738d1d8298STobias Waldekranz
24748d1d8298STobias Waldekranz /* Update the port's private database... */
24758d1d8298STobias Waldekranz err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
24768d1d8298STobias Waldekranz if (err)
24778d1d8298STobias Waldekranz return err;
24788d1d8298STobias Waldekranz
24798d1d8298STobias Waldekranz /* ...and the database for all VLANs. */
24808d1d8298STobias Waldekranz return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
24818d1d8298STobias Waldekranz &ctx);
24828d1d8298STobias Waldekranz }
24838d1d8298STobias Waldekranz
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2484b1ac6fb4SVivien Didelot static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2485933b4425SRussell King u16 vid, u8 member, bool warn)
2486fad09c73SVivien Didelot {
2487b1ac6fb4SVivien Didelot const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2488b4e47c0fSVivien Didelot struct mv88e6xxx_vtu_entry vlan;
2489b1ac6fb4SVivien Didelot int i, err;
2490fad09c73SVivien Didelot
249134065c58STobias Waldekranz err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2492fad09c73SVivien Didelot if (err)
2493fad09c73SVivien Didelot return err;
2494fad09c73SVivien Didelot
249534065c58STobias Waldekranz if (!vlan.valid) {
2496b1ac6fb4SVivien Didelot memset(&vlan, 0, sizeof(vlan));
2497b1ac6fb4SVivien Didelot
2498d352b20fSTobias Waldekranz if (vid == MV88E6XXX_VID_STANDALONE)
2499d352b20fSTobias Waldekranz vlan.policy = true;
2500d352b20fSTobias Waldekranz
2501b1ac6fb4SVivien Didelot err = mv88e6xxx_atu_new(chip, &vlan.fid);
2502b1ac6fb4SVivien Didelot if (err)
2503b1ac6fb4SVivien Didelot return err;
2504b1ac6fb4SVivien Didelot
2505b1ac6fb4SVivien Didelot for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2506b1ac6fb4SVivien Didelot if (i == port)
2507b1ac6fb4SVivien Didelot vlan.member[i] = member;
2508b1ac6fb4SVivien Didelot else
2509b1ac6fb4SVivien Didelot vlan.member[i] = non_member;
2510b1ac6fb4SVivien Didelot
2511b1ac6fb4SVivien Didelot vlan.vid = vid;
25121cb9dfcaSRasmus Villemoes vlan.valid = true;
2513fad09c73SVivien Didelot
251487fa886eSAndrew Lunn err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
251587fa886eSAndrew Lunn if (err)
251687fa886eSAndrew Lunn return err;
251787fa886eSAndrew Lunn
2518b1ac6fb4SVivien Didelot err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2519b1ac6fb4SVivien Didelot if (err)
2520b1ac6fb4SVivien Didelot return err;
2521b1ac6fb4SVivien Didelot } else if (vlan.member[port] != member) {
2522b1ac6fb4SVivien Didelot vlan.member[port] = member;
2523b1ac6fb4SVivien Didelot
2524b1ac6fb4SVivien Didelot err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2525b1ac6fb4SVivien Didelot if (err)
2526b1ac6fb4SVivien Didelot return err;
2527933b4425SRussell King } else if (warn) {
2528b1ac6fb4SVivien Didelot dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2529b1ac6fb4SVivien Didelot port, vid);
2530b1ac6fb4SVivien Didelot }
2531b1ac6fb4SVivien Didelot
2532b1ac6fb4SVivien Didelot return 0;
2533fad09c73SVivien Didelot }
2534fad09c73SVivien Didelot
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)25351958d581SVladimir Oltean static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
253631046a5fSVladimir Oltean const struct switchdev_obj_port_vlan *vlan,
253731046a5fSVladimir Oltean struct netlink_ext_ack *extack)
2538fad09c73SVivien Didelot {
253904bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2540fad09c73SVivien Didelot bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2541fad09c73SVivien Didelot bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
25428b6836d8SVladimir Oltean struct mv88e6xxx_port *p = &chip->ports[port];
2543933b4425SRussell King bool warn;
2544c91498e1SVivien Didelot u8 member;
25451958d581SVladimir Oltean int err;
2546fad09c73SVivien Didelot
2547b8b79c41SEldar Gasanov if (!vlan->vid)
2548b8b79c41SEldar Gasanov return 0;
2549b8b79c41SEldar Gasanov
25501958d581SVladimir Oltean err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
25511958d581SVladimir Oltean if (err)
25521958d581SVladimir Oltean return err;
2553fad09c73SVivien Didelot
2554c91498e1SVivien Didelot if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
25557ec60d6eSVivien Didelot member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2556c91498e1SVivien Didelot else if (untagged)
25577ec60d6eSVivien Didelot member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2558c91498e1SVivien Didelot else
25597ec60d6eSVivien Didelot member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2560c91498e1SVivien Didelot
2561933b4425SRussell King /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2562933b4425SRussell King * and then the CPU port. Do not warn for duplicates for the CPU port.
2563933b4425SRussell King */
2564933b4425SRussell King warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2565933b4425SRussell King
2566c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2567fad09c73SVivien Didelot
25681958d581SVladimir Oltean err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
25691958d581SVladimir Oltean if (err) {
2570774439e5SVivien Didelot dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2571b7a9e0daSVladimir Oltean vlan->vid, untagged ? 'u' : 't');
25721958d581SVladimir Oltean goto out;
25731958d581SVladimir Oltean }
2574fad09c73SVivien Didelot
25751958d581SVladimir Oltean if (pvid) {
25768b6836d8SVladimir Oltean p->bridge_pvid.vid = vlan->vid;
25778b6836d8SVladimir Oltean p->bridge_pvid.valid = true;
25788b6836d8SVladimir Oltean
25798b6836d8SVladimir Oltean err = mv88e6xxx_port_commit_pvid(chip, port);
25808b6836d8SVladimir Oltean if (err)
25818b6836d8SVladimir Oltean goto out;
25828b6836d8SVladimir Oltean } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
25838b6836d8SVladimir Oltean /* The old pvid was reinstalled as a non-pvid VLAN */
25848b6836d8SVladimir Oltean p->bridge_pvid.valid = false;
25858b6836d8SVladimir Oltean
25868b6836d8SVladimir Oltean err = mv88e6xxx_port_commit_pvid(chip, port);
25878b6836d8SVladimir Oltean if (err)
25881958d581SVladimir Oltean goto out;
25891958d581SVladimir Oltean }
25908b6836d8SVladimir Oltean
25911958d581SVladimir Oltean out:
2592c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
25931958d581SVladimir Oltean
25941958d581SVladimir Oltean return err;
2595fad09c73SVivien Didelot }
2596fad09c73SVivien Didelot
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)259752109892SVivien Didelot static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2598fad09c73SVivien Didelot int port, u16 vid)
2599fad09c73SVivien Didelot {
2600b4e47c0fSVivien Didelot struct mv88e6xxx_vtu_entry vlan;
2601fad09c73SVivien Didelot int i, err;
2602fad09c73SVivien Didelot
260352109892SVivien Didelot if (!vid)
2604c92c7413SVladimir Oltean return 0;
260552109892SVivien Didelot
260634065c58STobias Waldekranz err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2607fad09c73SVivien Didelot if (err)
2608fad09c73SVivien Didelot return err;
2609fad09c73SVivien Didelot
261052109892SVivien Didelot /* If the VLAN doesn't exist in hardware or the port isn't a member,
261152109892SVivien Didelot * tell switchdev that this VLAN is likely handled in software.
261252109892SVivien Didelot */
261334065c58STobias Waldekranz if (!vlan.valid ||
261452109892SVivien Didelot vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2615fad09c73SVivien Didelot return -EOPNOTSUPP;
2616fad09c73SVivien Didelot
26177ec60d6eSVivien Didelot vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2618fad09c73SVivien Didelot
2619fad09c73SVivien Didelot /* keep the VLAN unless all ports are excluded */
2620fad09c73SVivien Didelot vlan.valid = false;
2621370b4ffbSVivien Didelot for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
26227ec60d6eSVivien Didelot if (vlan.member[i] !=
26237ec60d6eSVivien Didelot MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2624fad09c73SVivien Didelot vlan.valid = true;
2625fad09c73SVivien Didelot break;
2626fad09c73SVivien Didelot }
2627fad09c73SVivien Didelot }
2628fad09c73SVivien Didelot
26290ad5daf6SVivien Didelot err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2630fad09c73SVivien Didelot if (err)
2631fad09c73SVivien Didelot return err;
2632fad09c73SVivien Didelot
2633acaf4d2eSTobias Waldekranz if (!vlan.valid) {
2634acaf4d2eSTobias Waldekranz err = mv88e6xxx_mst_put(chip, vlan.sid);
2635acaf4d2eSTobias Waldekranz if (err)
2636acaf4d2eSTobias Waldekranz return err;
2637acaf4d2eSTobias Waldekranz }
2638acaf4d2eSTobias Waldekranz
2639e606ca36SVivien Didelot return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2640fad09c73SVivien Didelot }
2641fad09c73SVivien Didelot
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2642fad09c73SVivien Didelot static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2643fad09c73SVivien Didelot const struct switchdev_obj_port_vlan *vlan)
2644fad09c73SVivien Didelot {
264504bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
26468b6836d8SVladimir Oltean struct mv88e6xxx_port *p = &chip->ports[port];
2647fad09c73SVivien Didelot int err = 0;
2648b7a9e0daSVladimir Oltean u16 pvid;
2649fad09c73SVivien Didelot
2650e545f865STobias Waldekranz if (!mv88e6xxx_max_vid(chip))
2651fad09c73SVivien Didelot return -EOPNOTSUPP;
2652fad09c73SVivien Didelot
2653a2614140SVladimir Oltean /* The ATU removal procedure needs the FID to be mapped in the VTU,
2654a2614140SVladimir Oltean * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2655a2614140SVladimir Oltean * switchdev workqueue to ensure that all FDB entries are deleted
2656a2614140SVladimir Oltean * before we remove the VLAN.
2657a2614140SVladimir Oltean */
2658a2614140SVladimir Oltean dsa_flush_workqueue();
2659a2614140SVladimir Oltean
2660c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2661fad09c73SVivien Didelot
266277064f37SVivien Didelot err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2663fad09c73SVivien Didelot if (err)
2664fad09c73SVivien Didelot goto unlock;
2665fad09c73SVivien Didelot
2666b7a9e0daSVladimir Oltean err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2667fad09c73SVivien Didelot if (err)
2668fad09c73SVivien Didelot goto unlock;
2669fad09c73SVivien Didelot
2670b7a9e0daSVladimir Oltean if (vlan->vid == pvid) {
26718b6836d8SVladimir Oltean p->bridge_pvid.valid = false;
26728b6836d8SVladimir Oltean
26738b6836d8SVladimir Oltean err = mv88e6xxx_port_commit_pvid(chip, port);
2674fad09c73SVivien Didelot if (err)
2675fad09c73SVivien Didelot goto unlock;
2676fad09c73SVivien Didelot }
2677fad09c73SVivien Didelot
2678fad09c73SVivien Didelot unlock:
2679c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2680fad09c73SVivien Didelot
2681fad09c73SVivien Didelot return err;
2682fad09c73SVivien Didelot }
2683fad09c73SVivien Didelot
mv88e6xxx_port_vlan_fast_age(struct dsa_switch * ds,int port,u16 vid)2684acaf4d2eSTobias Waldekranz static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2685acaf4d2eSTobias Waldekranz {
2686acaf4d2eSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
2687acaf4d2eSTobias Waldekranz struct mv88e6xxx_vtu_entry vlan;
2688acaf4d2eSTobias Waldekranz int err;
2689acaf4d2eSTobias Waldekranz
2690acaf4d2eSTobias Waldekranz mv88e6xxx_reg_lock(chip);
2691acaf4d2eSTobias Waldekranz
2692acaf4d2eSTobias Waldekranz err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2693acaf4d2eSTobias Waldekranz if (err)
2694acaf4d2eSTobias Waldekranz goto unlock;
2695acaf4d2eSTobias Waldekranz
2696acaf4d2eSTobias Waldekranz err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2697acaf4d2eSTobias Waldekranz
2698acaf4d2eSTobias Waldekranz unlock:
2699acaf4d2eSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
2700acaf4d2eSTobias Waldekranz
2701acaf4d2eSTobias Waldekranz return err;
2702acaf4d2eSTobias Waldekranz }
2703acaf4d2eSTobias Waldekranz
mv88e6xxx_vlan_msti_set(struct dsa_switch * ds,struct dsa_bridge bridge,const struct switchdev_vlan_msti * msti)2704acaf4d2eSTobias Waldekranz static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2705acaf4d2eSTobias Waldekranz struct dsa_bridge bridge,
2706acaf4d2eSTobias Waldekranz const struct switchdev_vlan_msti *msti)
2707acaf4d2eSTobias Waldekranz {
2708acaf4d2eSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
2709acaf4d2eSTobias Waldekranz struct mv88e6xxx_vtu_entry vlan;
2710acaf4d2eSTobias Waldekranz u8 old_sid, new_sid;
2711acaf4d2eSTobias Waldekranz int err;
2712acaf4d2eSTobias Waldekranz
2713bd48b911STobias Waldekranz if (!mv88e6xxx_has_stu(chip))
2714bd48b911STobias Waldekranz return -EOPNOTSUPP;
2715bd48b911STobias Waldekranz
2716acaf4d2eSTobias Waldekranz mv88e6xxx_reg_lock(chip);
2717acaf4d2eSTobias Waldekranz
2718acaf4d2eSTobias Waldekranz err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2719acaf4d2eSTobias Waldekranz if (err)
2720acaf4d2eSTobias Waldekranz goto unlock;
2721acaf4d2eSTobias Waldekranz
2722acaf4d2eSTobias Waldekranz if (!vlan.valid) {
2723acaf4d2eSTobias Waldekranz err = -EINVAL;
2724acaf4d2eSTobias Waldekranz goto unlock;
2725acaf4d2eSTobias Waldekranz }
2726acaf4d2eSTobias Waldekranz
2727acaf4d2eSTobias Waldekranz old_sid = vlan.sid;
2728acaf4d2eSTobias Waldekranz
2729acaf4d2eSTobias Waldekranz err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2730acaf4d2eSTobias Waldekranz if (err)
2731acaf4d2eSTobias Waldekranz goto unlock;
2732acaf4d2eSTobias Waldekranz
2733acaf4d2eSTobias Waldekranz if (new_sid != old_sid) {
2734acaf4d2eSTobias Waldekranz vlan.sid = new_sid;
2735acaf4d2eSTobias Waldekranz
2736acaf4d2eSTobias Waldekranz err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2737acaf4d2eSTobias Waldekranz if (err) {
2738acaf4d2eSTobias Waldekranz mv88e6xxx_mst_put(chip, new_sid);
2739acaf4d2eSTobias Waldekranz goto unlock;
2740acaf4d2eSTobias Waldekranz }
2741acaf4d2eSTobias Waldekranz }
2742acaf4d2eSTobias Waldekranz
2743acaf4d2eSTobias Waldekranz err = mv88e6xxx_mst_put(chip, old_sid);
2744acaf4d2eSTobias Waldekranz
2745acaf4d2eSTobias Waldekranz unlock:
2746acaf4d2eSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
2747acaf4d2eSTobias Waldekranz return err;
2748acaf4d2eSTobias Waldekranz }
2749acaf4d2eSTobias Waldekranz
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)27501b6dd556SArkadi Sharshevsky static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2751c2693363SVladimir Oltean const unsigned char *addr, u16 vid,
2752c2693363SVladimir Oltean struct dsa_db db)
2753fad09c73SVivien Didelot {
275404bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
27551b6dd556SArkadi Sharshevsky int err;
2756fad09c73SVivien Didelot
2757c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
27581b6dd556SArkadi Sharshevsky err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
27591b6dd556SArkadi Sharshevsky MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2760c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
27611b6dd556SArkadi Sharshevsky
27621b6dd556SArkadi Sharshevsky return err;
2763fad09c73SVivien Didelot }
2764fad09c73SVivien Didelot
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2765fad09c73SVivien Didelot static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2766c2693363SVladimir Oltean const unsigned char *addr, u16 vid,
2767c2693363SVladimir Oltean struct dsa_db db)
2768fad09c73SVivien Didelot {
276904bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
277083dabd1fSVivien Didelot int err;
2771fad09c73SVivien Didelot
2772c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2773d8291a95SVivien Didelot err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2774c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2775fad09c73SVivien Didelot
277683dabd1fSVivien Didelot return err;
2777fad09c73SVivien Didelot }
2778fad09c73SVivien Didelot
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)277983dabd1fSVivien Didelot static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2780fad09c73SVivien Didelot u16 fid, u16 vid, int port,
27812bedde1aSArkadi Sharshevsky dsa_fdb_dump_cb_t *cb, void *data)
2782fad09c73SVivien Didelot {
2783dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry addr;
27842bedde1aSArkadi Sharshevsky bool is_static;
2785fad09c73SVivien Didelot int err;
2786fad09c73SVivien Didelot
2787d8291a95SVivien Didelot addr.state = 0;
2788dabc1a96SVivien Didelot eth_broadcast_addr(addr.mac);
2789fad09c73SVivien Didelot
2790fad09c73SVivien Didelot do {
2791dabc1a96SVivien Didelot err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2792fad09c73SVivien Didelot if (err)
279383dabd1fSVivien Didelot return err;
2794fad09c73SVivien Didelot
2795d8291a95SVivien Didelot if (!addr.state)
2796fad09c73SVivien Didelot break;
2797fad09c73SVivien Didelot
279801bd96c8SVivien Didelot if (addr.trunk || (addr.portvec & BIT(port)) == 0)
279983dabd1fSVivien Didelot continue;
2800fad09c73SVivien Didelot
280183dabd1fSVivien Didelot if (!is_unicast_ether_addr(addr.mac))
280283dabd1fSVivien Didelot continue;
280383dabd1fSVivien Didelot
28042bedde1aSArkadi Sharshevsky is_static = (addr.state ==
28052bedde1aSArkadi Sharshevsky MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
28062bedde1aSArkadi Sharshevsky err = cb(addr.mac, vid, is_static, data);
280783dabd1fSVivien Didelot if (err)
280883dabd1fSVivien Didelot return err;
2809fad09c73SVivien Didelot } while (!is_broadcast_ether_addr(addr.mac));
2810fad09c73SVivien Didelot
2811fad09c73SVivien Didelot return err;
2812fad09c73SVivien Didelot }
2813fad09c73SVivien Didelot
2814d89ef4b8STobias Waldekranz struct mv88e6xxx_port_db_dump_vlan_ctx {
2815d89ef4b8STobias Waldekranz int port;
2816d89ef4b8STobias Waldekranz dsa_fdb_dump_cb_t *cb;
2817d89ef4b8STobias Waldekranz void *data;
2818d89ef4b8STobias Waldekranz };
2819d89ef4b8STobias Waldekranz
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2820d89ef4b8STobias Waldekranz static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2821d89ef4b8STobias Waldekranz const struct mv88e6xxx_vtu_entry *entry,
2822d89ef4b8STobias Waldekranz void *_data)
2823d89ef4b8STobias Waldekranz {
2824d89ef4b8STobias Waldekranz struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2825d89ef4b8STobias Waldekranz
2826d89ef4b8STobias Waldekranz return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2827d89ef4b8STobias Waldekranz ctx->port, ctx->cb, ctx->data);
2828d89ef4b8STobias Waldekranz }
2829d89ef4b8STobias Waldekranz
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)283083dabd1fSVivien Didelot static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
28312bedde1aSArkadi Sharshevsky dsa_fdb_dump_cb_t *cb, void *data)
283283dabd1fSVivien Didelot {
2833d89ef4b8STobias Waldekranz struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2834d89ef4b8STobias Waldekranz .port = port,
2835d89ef4b8STobias Waldekranz .cb = cb,
2836d89ef4b8STobias Waldekranz .data = data,
2837d89ef4b8STobias Waldekranz };
283883dabd1fSVivien Didelot u16 fid;
283983dabd1fSVivien Didelot int err;
284083dabd1fSVivien Didelot
284183dabd1fSVivien Didelot /* Dump port's default Filtering Information Database (VLAN ID 0) */
2842b4e48c50SVivien Didelot err = mv88e6xxx_port_get_fid(chip, port, &fid);
284383dabd1fSVivien Didelot if (err)
284483dabd1fSVivien Didelot return err;
284583dabd1fSVivien Didelot
28462bedde1aSArkadi Sharshevsky err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
284783dabd1fSVivien Didelot if (err)
284883dabd1fSVivien Didelot return err;
284983dabd1fSVivien Didelot
2850d89ef4b8STobias Waldekranz return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
285183dabd1fSVivien Didelot }
285283dabd1fSVivien Didelot
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2853fad09c73SVivien Didelot static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
28542bedde1aSArkadi Sharshevsky dsa_fdb_dump_cb_t *cb, void *data)
2855fad09c73SVivien Didelot {
285604bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2857fcf15367SVivien Didelot int err;
2858fad09c73SVivien Didelot
2859c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2860fcf15367SVivien Didelot err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2861c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2862fcf15367SVivien Didelot
2863fcf15367SVivien Didelot return err;
2864fad09c73SVivien Didelot }
2865fad09c73SVivien Didelot
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct dsa_bridge bridge)2866240ea3efSVivien Didelot static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2867d3eed0e5SVladimir Oltean struct dsa_bridge bridge)
2868240ea3efSVivien Didelot {
2869ef2025ecSVivien Didelot struct dsa_switch *ds = chip->ds;
2870ef2025ecSVivien Didelot struct dsa_switch_tree *dst = ds->dst;
2871ef2025ecSVivien Didelot struct dsa_port *dp;
2872240ea3efSVivien Didelot int err;
2873240ea3efSVivien Didelot
2874ef2025ecSVivien Didelot list_for_each_entry(dp, &dst->ports, list) {
2875d3eed0e5SVladimir Oltean if (dsa_port_offloads_bridge(dp, &bridge)) {
2876ef2025ecSVivien Didelot if (dp->ds == ds) {
2877ef2025ecSVivien Didelot /* This is a local bridge group member,
2878ef2025ecSVivien Didelot * remap its Port VLAN Map.
2879ef2025ecSVivien Didelot */
2880ef2025ecSVivien Didelot err = mv88e6xxx_port_vlan_map(chip, dp->index);
2881240ea3efSVivien Didelot if (err)
2882240ea3efSVivien Didelot return err;
2883ef2025ecSVivien Didelot } else {
2884ef2025ecSVivien Didelot /* This is an external bridge group member,
2885ef2025ecSVivien Didelot * remap its cross-chip Port VLAN Table entry.
2886ef2025ecSVivien Didelot */
2887ef2025ecSVivien Didelot err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2888ef2025ecSVivien Didelot dp->index);
2889e96a6e02SVivien Didelot if (err)
2890e96a6e02SVivien Didelot return err;
2891e96a6e02SVivien Didelot }
2892e96a6e02SVivien Didelot }
2893e96a6e02SVivien Didelot }
2894e96a6e02SVivien Didelot
2895240ea3efSVivien Didelot return 0;
2896240ea3efSVivien Didelot }
2897240ea3efSVivien Didelot
2898857fdd74SVladimir Oltean /* Treat the software bridge as a virtual single-port switch behind the
2899857fdd74SVladimir Oltean * CPU and map in the PVT. First dst->last_switch elements are taken by
2900857fdd74SVladimir Oltean * physical switches, so start from beyond that range.
2901857fdd74SVladimir Oltean */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,unsigned int bridge_num)2902857fdd74SVladimir Oltean static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2903857fdd74SVladimir Oltean unsigned int bridge_num)
2904857fdd74SVladimir Oltean {
2905857fdd74SVladimir Oltean u8 dev = bridge_num + ds->dst->last_switch;
2906857fdd74SVladimir Oltean struct mv88e6xxx_chip *chip = ds->priv;
2907857fdd74SVladimir Oltean
2908857fdd74SVladimir Oltean return mv88e6xxx_pvt_map(chip, dev, 0);
2909857fdd74SVladimir Oltean }
2910857fdd74SVladimir Oltean
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2911fad09c73SVivien Didelot static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2912b079922bSVladimir Oltean struct dsa_bridge bridge,
291306b9cce4SVladimir Oltean bool *tx_fwd_offload,
291406b9cce4SVladimir Oltean struct netlink_ext_ack *extack)
2915fad09c73SVivien Didelot {
291604bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2917240ea3efSVivien Didelot int err;
2918fad09c73SVivien Didelot
2919c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
29205bded825SVladimir Oltean
2921d3eed0e5SVladimir Oltean err = mv88e6xxx_bridge_map(chip, bridge);
29225bded825SVladimir Oltean if (err)
29235bded825SVladimir Oltean goto unlock;
29245bded825SVladimir Oltean
29257af4a361STobias Waldekranz err = mv88e6xxx_port_set_map_da(chip, port, true);
29267af4a361STobias Waldekranz if (err)
2927ff624338SDan Carpenter goto unlock;
29287af4a361STobias Waldekranz
29295bded825SVladimir Oltean err = mv88e6xxx_port_commit_pvid(chip, port);
29305bded825SVladimir Oltean if (err)
29315bded825SVladimir Oltean goto unlock;
29325bded825SVladimir Oltean
2933857fdd74SVladimir Oltean if (mv88e6xxx_has_pvt(chip)) {
2934857fdd74SVladimir Oltean err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2935857fdd74SVladimir Oltean if (err)
2936857fdd74SVladimir Oltean goto unlock;
2937857fdd74SVladimir Oltean
2938857fdd74SVladimir Oltean *tx_fwd_offload = true;
2939857fdd74SVladimir Oltean }
2940857fdd74SVladimir Oltean
29415bded825SVladimir Oltean unlock:
2942c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2943fad09c73SVivien Didelot
2944fad09c73SVivien Didelot return err;
2945fad09c73SVivien Didelot }
2946fad09c73SVivien Didelot
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2947f123f2fbSVivien Didelot static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2948d3eed0e5SVladimir Oltean struct dsa_bridge bridge)
2949fad09c73SVivien Didelot {
295004bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
29515bded825SVladimir Oltean int err;
2952fad09c73SVivien Didelot
2953c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
29545bded825SVladimir Oltean
2955857fdd74SVladimir Oltean if (bridge.tx_fwd_offload &&
2956857fdd74SVladimir Oltean mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2957857fdd74SVladimir Oltean dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2958857fdd74SVladimir Oltean
2959d3eed0e5SVladimir Oltean if (mv88e6xxx_bridge_map(chip, bridge) ||
2960240ea3efSVivien Didelot mv88e6xxx_port_vlan_map(chip, port))
2961240ea3efSVivien Didelot dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
29625bded825SVladimir Oltean
29637af4a361STobias Waldekranz err = mv88e6xxx_port_set_map_da(chip, port, false);
29647af4a361STobias Waldekranz if (err)
29657af4a361STobias Waldekranz dev_err(ds->dev,
29667af4a361STobias Waldekranz "port %d failed to restore map-DA: %pe\n",
29677af4a361STobias Waldekranz port, ERR_PTR(err));
29687af4a361STobias Waldekranz
29695bded825SVladimir Oltean err = mv88e6xxx_port_commit_pvid(chip, port);
29705bded825SVladimir Oltean if (err)
29715bded825SVladimir Oltean dev_err(ds->dev,
29725bded825SVladimir Oltean "port %d failed to restore standalone pvid: %pe\n",
29735bded825SVladimir Oltean port, ERR_PTR(err));
29745bded825SVladimir Oltean
2975c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2976fad09c73SVivien Didelot }
2977fad09c73SVivien Didelot
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge,struct netlink_ext_ack * extack)2978f66a6a69SVladimir Oltean static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2979f66a6a69SVladimir Oltean int tree_index, int sw_index,
298006b9cce4SVladimir Oltean int port, struct dsa_bridge bridge,
298106b9cce4SVladimir Oltean struct netlink_ext_ack *extack)
2982aec5ac88SVivien Didelot {
2983aec5ac88SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
2984aec5ac88SVivien Didelot int err;
2985aec5ac88SVivien Didelot
2986f66a6a69SVladimir Oltean if (tree_index != ds->dst->index)
2987f66a6a69SVladimir Oltean return 0;
2988f66a6a69SVladimir Oltean
2989c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
2990f66a6a69SVladimir Oltean err = mv88e6xxx_pvt_map(chip, sw_index, port);
2991e0068620STobias Waldekranz err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2992c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
2993aec5ac88SVivien Didelot
2994aec5ac88SVivien Didelot return err;
2995aec5ac88SVivien Didelot }
2996aec5ac88SVivien Didelot
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge)2997f66a6a69SVladimir Oltean static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2998f66a6a69SVladimir Oltean int tree_index, int sw_index,
2999d3eed0e5SVladimir Oltean int port, struct dsa_bridge bridge)
3000aec5ac88SVivien Didelot {
3001aec5ac88SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
3002aec5ac88SVivien Didelot
3003f66a6a69SVladimir Oltean if (tree_index != ds->dst->index)
3004f66a6a69SVladimir Oltean return;
3005f66a6a69SVladimir Oltean
3006c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
3007e0068620STobias Waldekranz if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3008e0068620STobias Waldekranz mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3009aec5ac88SVivien Didelot dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3010c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
3011aec5ac88SVivien Didelot }
3012aec5ac88SVivien Didelot
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)301317e708baSVivien Didelot static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
301417e708baSVivien Didelot {
301517e708baSVivien Didelot if (chip->info->ops->reset)
301617e708baSVivien Didelot return chip->info->ops->reset(chip);
301717e708baSVivien Didelot
301817e708baSVivien Didelot return 0;
301917e708baSVivien Didelot }
302017e708baSVivien Didelot
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)3021309eca6dSVivien Didelot static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3022309eca6dSVivien Didelot {
3023309eca6dSVivien Didelot struct gpio_desc *gpiod = chip->reset;
3024d1e3dc19SMatthias Schiffer int err;
3025309eca6dSVivien Didelot
3026309eca6dSVivien Didelot /* If there is a GPIO connected to the reset pin, toggle it */
3027309eca6dSVivien Didelot if (gpiod) {
302823d775f1SAlfred Lee /* If the switch has just been reset and not yet completed
302923d775f1SAlfred Lee * loading EEPROM, the reset may interrupt the I2C transaction
303023d775f1SAlfred Lee * mid-byte, causing the first EEPROM read after the reset
303123d775f1SAlfred Lee * from the wrong location resulting in the switch booting
303223d775f1SAlfred Lee * to wrong mode and inoperable.
3033d1e3dc19SMatthias Schiffer * For this reason, switch families with EEPROM support
3034d1e3dc19SMatthias Schiffer * generally wait for EEPROM loads to complete as their pre-
3035d1e3dc19SMatthias Schiffer * and post-reset handlers.
303623d775f1SAlfred Lee */
3037d1e3dc19SMatthias Schiffer if (chip->info->ops->hardware_reset_pre) {
3038d1e3dc19SMatthias Schiffer err = chip->info->ops->hardware_reset_pre(chip);
3039d1e3dc19SMatthias Schiffer if (err)
3040d1e3dc19SMatthias Schiffer dev_err(chip->dev, "pre-reset error: %d\n", err);
3041d1e3dc19SMatthias Schiffer }
304223d775f1SAlfred Lee
3043309eca6dSVivien Didelot gpiod_set_value_cansleep(gpiod, 1);
3044309eca6dSVivien Didelot usleep_range(10000, 20000);
3045309eca6dSVivien Didelot gpiod_set_value_cansleep(gpiod, 0);
3046309eca6dSVivien Didelot usleep_range(10000, 20000);
3047a3dcb3e7SAndrew Lunn
3048d1e3dc19SMatthias Schiffer if (chip->info->ops->hardware_reset_post) {
3049d1e3dc19SMatthias Schiffer err = chip->info->ops->hardware_reset_post(chip);
3050d1e3dc19SMatthias Schiffer if (err)
3051d1e3dc19SMatthias Schiffer dev_err(chip->dev, "post-reset error: %d\n", err);
3052d1e3dc19SMatthias Schiffer }
3053309eca6dSVivien Didelot }
3054309eca6dSVivien Didelot }
3055309eca6dSVivien Didelot
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)30564ac4b5a6SVivien Didelot static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
30574ac4b5a6SVivien Didelot {
30584ac4b5a6SVivien Didelot int i, err;
30594ac4b5a6SVivien Didelot
30604ac4b5a6SVivien Didelot /* Set all ports to the Disabled state */
30614ac4b5a6SVivien Didelot for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3062f894c29cSVivien Didelot err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
30634ac4b5a6SVivien Didelot if (err)
30644ac4b5a6SVivien Didelot return err;
30654ac4b5a6SVivien Didelot }
30664ac4b5a6SVivien Didelot
30674ac4b5a6SVivien Didelot /* Wait for transmit queues to drain,
30684ac4b5a6SVivien Didelot * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
30694ac4b5a6SVivien Didelot */
30704ac4b5a6SVivien Didelot usleep_range(2000, 4000);
30714ac4b5a6SVivien Didelot
30724ac4b5a6SVivien Didelot return 0;
30734ac4b5a6SVivien Didelot }
30744ac4b5a6SVivien Didelot
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)3075fad09c73SVivien Didelot static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3076fad09c73SVivien Didelot {
3077a935c052SVivien Didelot int err;
3078fad09c73SVivien Didelot
30794ac4b5a6SVivien Didelot err = mv88e6xxx_disable_ports(chip);
30800e7b9925SAndrew Lunn if (err)
30810e7b9925SAndrew Lunn return err;
3082fad09c73SVivien Didelot
3083309eca6dSVivien Didelot mv88e6xxx_hardware_reset(chip);
3084fad09c73SVivien Didelot
308517e708baSVivien Didelot return mv88e6xxx_software_reset(chip);
3086fad09c73SVivien Didelot }
3087fad09c73SVivien Didelot
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)30884314557cSVivien Didelot static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
308931bef4e9SVivien Didelot enum mv88e6xxx_frame_mode frame,
309031bef4e9SVivien Didelot enum mv88e6xxx_egress_mode egress, u16 etype)
309156995cbcSAndrew Lunn {
309256995cbcSAndrew Lunn int err;
309356995cbcSAndrew Lunn
30944314557cSVivien Didelot if (!chip->info->ops->port_set_frame_mode)
30954314557cSVivien Didelot return -EOPNOTSUPP;
30964314557cSVivien Didelot
30974314557cSVivien Didelot err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
309856995cbcSAndrew Lunn if (err)
309956995cbcSAndrew Lunn return err;
310056995cbcSAndrew Lunn
31014314557cSVivien Didelot err = chip->info->ops->port_set_frame_mode(chip, port, frame);
31024314557cSVivien Didelot if (err)
31034314557cSVivien Didelot return err;
31044314557cSVivien Didelot
31054314557cSVivien Didelot if (chip->info->ops->port_set_ether_type)
31064314557cSVivien Didelot return chip->info->ops->port_set_ether_type(chip, port, etype);
31074314557cSVivien Didelot
31084314557cSVivien Didelot return 0;
31094314557cSVivien Didelot }
31104314557cSVivien Didelot
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)31114314557cSVivien Didelot static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
31124314557cSVivien Didelot {
31134314557cSVivien Didelot return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
311431bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3115b8109594SVivien Didelot MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
31164314557cSVivien Didelot }
31174314557cSVivien Didelot
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)31184314557cSVivien Didelot static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
31194314557cSVivien Didelot {
31204314557cSVivien Didelot return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
312131bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3122b8109594SVivien Didelot MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
31234314557cSVivien Didelot }
31244314557cSVivien Didelot
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)31254314557cSVivien Didelot static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
31264314557cSVivien Didelot {
31274314557cSVivien Didelot return mv88e6xxx_set_port_mode(chip, port,
31284314557cSVivien Didelot MV88E6XXX_FRAME_MODE_ETHERTYPE,
312931bef4e9SVivien Didelot MV88E6XXX_EGRESS_MODE_ETHERTYPE,
313031bef4e9SVivien Didelot ETH_P_EDSA);
31314314557cSVivien Didelot }
31324314557cSVivien Didelot
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)31334314557cSVivien Didelot static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
31344314557cSVivien Didelot {
31354314557cSVivien Didelot if (dsa_is_dsa_port(chip->ds, port))
31364314557cSVivien Didelot return mv88e6xxx_set_port_mode_dsa(chip, port);
31374314557cSVivien Didelot
31382b3e9891SVivien Didelot if (dsa_is_user_port(chip->ds, port))
31394314557cSVivien Didelot return mv88e6xxx_set_port_mode_normal(chip, port);
31404314557cSVivien Didelot
31414314557cSVivien Didelot /* Setup CPU port mode depending on its supported tag format */
3142670bb80fSTobias Waldekranz if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
31434314557cSVivien Didelot return mv88e6xxx_set_port_mode_dsa(chip, port);
31444314557cSVivien Didelot
3145670bb80fSTobias Waldekranz if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
31464314557cSVivien Didelot return mv88e6xxx_set_port_mode_edsa(chip, port);
31474314557cSVivien Didelot
31484314557cSVivien Didelot return -EINVAL;
31494314557cSVivien Didelot }
31504314557cSVivien Didelot
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)3151ea698f4fSVivien Didelot static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3152ea698f4fSVivien Didelot {
3153ea698f4fSVivien Didelot bool message = dsa_is_dsa_port(chip->ds, port);
3154ea698f4fSVivien Didelot
3155ea698f4fSVivien Didelot return mv88e6xxx_port_set_message_port(chip, port, message);
3156ea698f4fSVivien Didelot }
3157ea698f4fSVivien Didelot
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)3158601aeed3SVivien Didelot static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3159601aeed3SVivien Didelot {
3160a8b659e7SVladimir Oltean int err;
3161601aeed3SVivien Didelot
3162a8b659e7SVladimir Oltean if (chip->info->ops->port_set_ucast_flood) {
31637b9f16feSTobias Waldekranz err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3164a8b659e7SVladimir Oltean if (err)
3165a8b659e7SVladimir Oltean return err;
3166a8b659e7SVladimir Oltean }
3167a8b659e7SVladimir Oltean if (chip->info->ops->port_set_mcast_flood) {
31687b9f16feSTobias Waldekranz err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3169a8b659e7SVladimir Oltean if (err)
3170a8b659e7SVladimir Oltean return err;
3171a8b659e7SVladimir Oltean }
3172407308f6SDavid S. Miller
3173601aeed3SVivien Didelot return 0;
3174601aeed3SVivien Didelot }
3175601aeed3SVivien Didelot
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)31762fda45f0SMarek Behún static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
31772fda45f0SMarek Behún enum mv88e6xxx_egress_direction direction,
31782fda45f0SMarek Behún int port)
31792fda45f0SMarek Behún {
31802fda45f0SMarek Behún int err;
31812fda45f0SMarek Behún
31822fda45f0SMarek Behún if (!chip->info->ops->set_egress_port)
31832fda45f0SMarek Behún return -EOPNOTSUPP;
31842fda45f0SMarek Behún
31852fda45f0SMarek Behún err = chip->info->ops->set_egress_port(chip, direction, port);
31862fda45f0SMarek Behún if (err)
31872fda45f0SMarek Behún return err;
31882fda45f0SMarek Behún
31892fda45f0SMarek Behún if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
31902fda45f0SMarek Behún chip->ingress_dest_port = port;
31912fda45f0SMarek Behún else
31922fda45f0SMarek Behún chip->egress_dest_port = port;
31932fda45f0SMarek Behún
31942fda45f0SMarek Behún return 0;
31952fda45f0SMarek Behún }
31962fda45f0SMarek Behún
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)3197fa371c80SVivien Didelot static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3198fa371c80SVivien Didelot {
3199fa371c80SVivien Didelot struct dsa_switch *ds = chip->ds;
3200fa371c80SVivien Didelot int upstream_port;
3201fa371c80SVivien Didelot int err;
3202fa371c80SVivien Didelot
320307073c79SVivien Didelot upstream_port = dsa_upstream_port(ds, port);
3204fa371c80SVivien Didelot if (chip->info->ops->port_set_upstream_port) {
3205fa371c80SVivien Didelot err = chip->info->ops->port_set_upstream_port(chip, port,
3206fa371c80SVivien Didelot upstream_port);
3207fa371c80SVivien Didelot if (err)
3208fa371c80SVivien Didelot return err;
3209fa371c80SVivien Didelot }
3210fa371c80SVivien Didelot
32110ea54ddaSVivien Didelot if (port == upstream_port) {
32120ea54ddaSVivien Didelot if (chip->info->ops->set_cpu_port) {
32130ea54ddaSVivien Didelot err = chip->info->ops->set_cpu_port(chip,
32140ea54ddaSVivien Didelot upstream_port);
32150ea54ddaSVivien Didelot if (err)
32160ea54ddaSVivien Didelot return err;
32170ea54ddaSVivien Didelot }
32180ea54ddaSVivien Didelot
32192fda45f0SMarek Behún err = mv88e6xxx_set_egress_port(chip,
32205c74c54cSIwan R Timmer MV88E6XXX_EGRESS_DIR_INGRESS,
32215c74c54cSIwan R Timmer upstream_port);
32222fda45f0SMarek Behún if (err && err != -EOPNOTSUPP)
32235c74c54cSIwan R Timmer return err;
32245c74c54cSIwan R Timmer
32252fda45f0SMarek Behún err = mv88e6xxx_set_egress_port(chip,
32265c74c54cSIwan R Timmer MV88E6XXX_EGRESS_DIR_EGRESS,
32270ea54ddaSVivien Didelot upstream_port);
32282fda45f0SMarek Behún if (err && err != -EOPNOTSUPP)
32290ea54ddaSVivien Didelot return err;
32300ea54ddaSVivien Didelot }
32310ea54ddaSVivien Didelot
3232fa371c80SVivien Didelot return 0;
3233fa371c80SVivien Didelot }
3234fa371c80SVivien Didelot
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)3235fad09c73SVivien Didelot static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3236fad09c73SVivien Didelot {
3237926eae60SHolger Brunck struct device_node *phy_handle = NULL;
3238fad09c73SVivien Didelot struct dsa_switch *ds = chip->ds;
3239926eae60SHolger Brunck struct dsa_port *dp;
324040da0c32SRussell King (Oracle) int tx_amp;
32410e7b9925SAndrew Lunn int err;
3242fad09c73SVivien Didelot u16 reg;
3243fad09c73SVivien Didelot
32447b898469SAndrew Lunn chip->ports[port].chip = chip;
32457b898469SAndrew Lunn chip->ports[port].port = port;
32467b898469SAndrew Lunn
3247d78343d2SVivien Didelot err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3248d78343d2SVivien Didelot SPEED_UNFORCED, DUPLEX_UNFORCED,
324940da0c32SRussell King (Oracle) PAUSE_ON, PHY_INTERFACE_MODE_NA);
32500e7b9925SAndrew Lunn if (err)
32510e7b9925SAndrew Lunn return err;
3252fad09c73SVivien Didelot
3253fad09c73SVivien Didelot /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3254fad09c73SVivien Didelot * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3255fad09c73SVivien Didelot * tunneling, determine priority by looking at 802.1p and IP
3256fad09c73SVivien Didelot * priority fields (IP prio has precedence), and set STP state
3257fad09c73SVivien Didelot * to Forwarding.
3258fad09c73SVivien Didelot *
3259fad09c73SVivien Didelot * If this is the CPU link, use DSA or EDSA tagging depending
3260fad09c73SVivien Didelot * on which tagging mode was configured.
3261fad09c73SVivien Didelot *
3262fad09c73SVivien Didelot * If this is a link to another switch, use DSA tagging mode.
3263fad09c73SVivien Didelot *
3264fad09c73SVivien Didelot * If this is the upstream port for this switch, enable
3265fad09c73SVivien Didelot * forwarding of unknown unicasts and multicasts.
3266fad09c73SVivien Didelot */
32677bcad0f0SSteffen Bätz reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3268a89b433bSVivien Didelot MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
32697bcad0f0SSteffen Bätz /* Forward any IPv4 IGMP or IPv6 MLD frames received
32707bcad0f0SSteffen Bätz * by a USER port to the CPU port to allow snooping.
32717bcad0f0SSteffen Bätz */
32727bcad0f0SSteffen Bätz if (dsa_is_user_port(ds, port))
32737bcad0f0SSteffen Bätz reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
32747bcad0f0SSteffen Bätz
3275a89b433bSVivien Didelot err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
32760e7b9925SAndrew Lunn if (err)
32770e7b9925SAndrew Lunn return err;
327856995cbcSAndrew Lunn
3279601aeed3SVivien Didelot err = mv88e6xxx_setup_port_mode(chip, port);
328056995cbcSAndrew Lunn if (err)
328156995cbcSAndrew Lunn return err;
3282fad09c73SVivien Didelot
3283601aeed3SVivien Didelot err = mv88e6xxx_setup_egress_floods(chip, port);
32844314557cSVivien Didelot if (err)
32854314557cSVivien Didelot return err;
32864314557cSVivien Didelot
3287b92ce2f5SAndrew Lunn /* Port Control 2: don't force a good FCS, set the MTU size to
32887af4a361STobias Waldekranz * 10222 bytes, disable 802.1q tags checking, don't discard
32897af4a361STobias Waldekranz * tagged or untagged frames on this port, skip destination
32907af4a361STobias Waldekranz * address lookup on user ports, disable ARP mirroring and don't
32917af4a361STobias Waldekranz * send a copy of all transmitted/received frames on this port
32927af4a361STobias Waldekranz * to the CPU.
3293fad09c73SVivien Didelot */
32947af4a361STobias Waldekranz err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3295a23b2961SAndrew Lunn if (err)
3296a23b2961SAndrew Lunn return err;
3297a23b2961SAndrew Lunn
3298fa371c80SVivien Didelot err = mv88e6xxx_setup_upstream_port(chip, port);
32990e7b9925SAndrew Lunn if (err)
33000e7b9925SAndrew Lunn return err;
3301fad09c73SVivien Didelot
3302d352b20fSTobias Waldekranz /* On chips that support it, set all downstream DSA ports'
3303d352b20fSTobias Waldekranz * VLAN policy to TRAP. In combination with loading
3304d352b20fSTobias Waldekranz * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3305d352b20fSTobias Waldekranz * provides a better isolation barrier between standalone
3306d352b20fSTobias Waldekranz * ports, as the ATU is bypassed on any intermediate switches
3307d352b20fSTobias Waldekranz * between the incoming port and the CPU.
3308d352b20fSTobias Waldekranz */
3309d352b20fSTobias Waldekranz if (dsa_is_downstream_port(ds, port) &&
3310d352b20fSTobias Waldekranz chip->info->ops->port_set_policy) {
3311d352b20fSTobias Waldekranz err = chip->info->ops->port_set_policy(chip, port,
3312d352b20fSTobias Waldekranz MV88E6XXX_POLICY_MAPPING_VTU,
3313d352b20fSTobias Waldekranz MV88E6XXX_POLICY_ACTION_TRAP);
3314d352b20fSTobias Waldekranz if (err)
3315d352b20fSTobias Waldekranz return err;
3316d352b20fSTobias Waldekranz }
3317d352b20fSTobias Waldekranz
3318d352b20fSTobias Waldekranz /* User ports start out in standalone mode and 802.1Q is
3319d352b20fSTobias Waldekranz * therefore disabled. On DSA ports, all valid VIDs are always
3320d352b20fSTobias Waldekranz * loaded in the VTU - therefore, enable 802.1Q in order to take
3321d352b20fSTobias Waldekranz * advantage of VLAN policy on chips that supports it.
3322d352b20fSTobias Waldekranz */
3323a23b2961SAndrew Lunn err = mv88e6xxx_port_set_8021q_mode(chip, port,
3324d352b20fSTobias Waldekranz dsa_is_user_port(ds, port) ?
3325d352b20fSTobias Waldekranz MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3326d352b20fSTobias Waldekranz MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3327d352b20fSTobias Waldekranz if (err)
3328d352b20fSTobias Waldekranz return err;
3329d352b20fSTobias Waldekranz
3330d352b20fSTobias Waldekranz /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3331d352b20fSTobias Waldekranz * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3332d352b20fSTobias Waldekranz * the first free FID. This will be used as the private PVID for
3333d352b20fSTobias Waldekranz * unbridged ports. Shared (DSA and CPU) ports must also be
3334d352b20fSTobias Waldekranz * members of this VID, in order to trap all frames assigned to
3335d352b20fSTobias Waldekranz * it to the CPU.
3336d352b20fSTobias Waldekranz */
3337d352b20fSTobias Waldekranz err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3338d352b20fSTobias Waldekranz MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3339d352b20fSTobias Waldekranz false);
3340a23b2961SAndrew Lunn if (err)
3341a23b2961SAndrew Lunn return err;
3342a23b2961SAndrew Lunn
33435bded825SVladimir Oltean /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
33445bded825SVladimir Oltean * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
33455bded825SVladimir Oltean * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
33465bded825SVladimir Oltean * as the private PVID on ports under a VLAN-unaware bridge.
33475bded825SVladimir Oltean * Shared (DSA and CPU) ports must also be members of it, to translate
33485bded825SVladimir Oltean * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
33495bded825SVladimir Oltean * relying on their port default FID.
33505bded825SVladimir Oltean */
33515bded825SVladimir Oltean err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3352d352b20fSTobias Waldekranz MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
33535bded825SVladimir Oltean false);
33545bded825SVladimir Oltean if (err)
33555bded825SVladimir Oltean return err;
33565bded825SVladimir Oltean
3357cd782656SVivien Didelot if (chip->info->ops->port_set_jumbo_size) {
3358b92ce2f5SAndrew Lunn err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
33595f436666SAndrew Lunn if (err)
33605f436666SAndrew Lunn return err;
33615f436666SAndrew Lunn }
33625f436666SAndrew Lunn
3363041bd545STobias Waldekranz /* Port Association Vector: disable automatic address learning
3364041bd545STobias Waldekranz * on all user ports since they start out in standalone
3365041bd545STobias Waldekranz * mode. When joining a bridge, learning will be configured to
3366041bd545STobias Waldekranz * match the bridge port settings. Enable learning on all
3367041bd545STobias Waldekranz * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3368041bd545STobias Waldekranz * learning process.
3369041bd545STobias Waldekranz *
3370041bd545STobias Waldekranz * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3371041bd545STobias Waldekranz * and RefreshLocked. I.e. setup standard automatic learning.
3372fad09c73SVivien Didelot */
3373041bd545STobias Waldekranz if (dsa_is_user_port(ds, port))
3374fad09c73SVivien Didelot reg = 0;
3375041bd545STobias Waldekranz else
3376041bd545STobias Waldekranz reg = 1 << port;
3377fad09c73SVivien Didelot
33782a4614e4SVivien Didelot err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
33792a4614e4SVivien Didelot reg);
33800e7b9925SAndrew Lunn if (err)
33810e7b9925SAndrew Lunn return err;
3382fad09c73SVivien Didelot
3383fad09c73SVivien Didelot /* Egress rate control 2: disable egress rate control. */
33842cb8cb14SVivien Didelot err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
33852cb8cb14SVivien Didelot 0x0000);
33860e7b9925SAndrew Lunn if (err)
33870e7b9925SAndrew Lunn return err;
3388fad09c73SVivien Didelot
33890898432cSVivien Didelot if (chip->info->ops->port_pause_limit) {
33900898432cSVivien Didelot err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3391b35d322aSAndrew Lunn if (err)
3392b35d322aSAndrew Lunn return err;
3393b35d322aSAndrew Lunn }
3394b35d322aSAndrew Lunn
3395c8c94891SVivien Didelot if (chip->info->ops->port_disable_learn_limit) {
3396c8c94891SVivien Didelot err = chip->info->ops->port_disable_learn_limit(chip, port);
3397c8c94891SVivien Didelot if (err)
3398c8c94891SVivien Didelot return err;
3399c8c94891SVivien Didelot }
3400c8c94891SVivien Didelot
34019dbfb4e1SVivien Didelot if (chip->info->ops->port_disable_pri_override) {
34029dbfb4e1SVivien Didelot err = chip->info->ops->port_disable_pri_override(chip, port);
34030e7b9925SAndrew Lunn if (err)
34040e7b9925SAndrew Lunn return err;
3405ef0a7318SAndrew Lunn }
34062bbb33beSAndrew Lunn
3407ef0a7318SAndrew Lunn if (chip->info->ops->port_tag_remap) {
3408ef0a7318SAndrew Lunn err = chip->info->ops->port_tag_remap(chip, port);
34090e7b9925SAndrew Lunn if (err)
34100e7b9925SAndrew Lunn return err;
3411fad09c73SVivien Didelot }
3412fad09c73SVivien Didelot
3413ef70b111SAndrew Lunn if (chip->info->ops->port_egress_rate_limiting) {
3414ef70b111SAndrew Lunn err = chip->info->ops->port_egress_rate_limiting(chip, port);
34150e7b9925SAndrew Lunn if (err)
34160e7b9925SAndrew Lunn return err;
3417fad09c73SVivien Didelot }
3418fad09c73SVivien Didelot
3419121b8fe2SHubert Feurstein if (chip->info->ops->port_setup_message_port) {
3420121b8fe2SHubert Feurstein err = chip->info->ops->port_setup_message_port(chip, port);
34210e7b9925SAndrew Lunn if (err)
34220e7b9925SAndrew Lunn return err;
3423121b8fe2SHubert Feurstein }
3424fad09c73SVivien Didelot
3425926eae60SHolger Brunck if (chip->info->ops->serdes_set_tx_amplitude) {
342640da0c32SRussell King (Oracle) dp = dsa_to_port(ds, port);
3427926eae60SHolger Brunck if (dp)
3428926eae60SHolger Brunck phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3429926eae60SHolger Brunck
3430926eae60SHolger Brunck if (phy_handle && !of_property_read_u32(phy_handle,
3431926eae60SHolger Brunck "tx-p2p-microvolt",
3432926eae60SHolger Brunck &tx_amp))
3433926eae60SHolger Brunck err = chip->info->ops->serdes_set_tx_amplitude(chip,
3434926eae60SHolger Brunck port, tx_amp);
3435926eae60SHolger Brunck if (phy_handle) {
3436926eae60SHolger Brunck of_node_put(phy_handle);
3437926eae60SHolger Brunck if (err)
3438926eae60SHolger Brunck return err;
3439926eae60SHolger Brunck }
3440926eae60SHolger Brunck }
3441926eae60SHolger Brunck
3442fad09c73SVivien Didelot /* Port based VLAN map: give each port the same default address
3443fad09c73SVivien Didelot * database, and allow bidirectional communication between the
3444fad09c73SVivien Didelot * CPU and DSA port(s), and the other ports.
3445fad09c73SVivien Didelot */
34465bded825SVladimir Oltean err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
34470e7b9925SAndrew Lunn if (err)
34480e7b9925SAndrew Lunn return err;
3449fad09c73SVivien Didelot
3450240ea3efSVivien Didelot err = mv88e6xxx_port_vlan_map(chip, port);
34510e7b9925SAndrew Lunn if (err)
34520e7b9925SAndrew Lunn return err;
3453fad09c73SVivien Didelot
3454fad09c73SVivien Didelot /* Default VLAN ID and priority: don't set a default VLAN
3455fad09c73SVivien Didelot * ID, and set the default packet priority to zero.
3456fad09c73SVivien Didelot */
3457b7929fb3SVivien Didelot return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3458fad09c73SVivien Didelot }
3459fad09c73SVivien Didelot
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)34602a550aecSAndrew Lunn static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
34612a550aecSAndrew Lunn {
34622a550aecSAndrew Lunn struct mv88e6xxx_chip *chip = ds->priv;
34632a550aecSAndrew Lunn
34642a550aecSAndrew Lunn if (chip->info->ops->port_set_jumbo_size)
3465b9c587feSAndrew Lunn return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
34661baf0facSChris Packham else if (chip->info->ops->set_max_frame_size)
3467b9c587feSAndrew Lunn return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
34687e951737SVladimir Oltean return ETH_DATA_LEN;
34692a550aecSAndrew Lunn }
34702a550aecSAndrew Lunn
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)34712a550aecSAndrew Lunn static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
34722a550aecSAndrew Lunn {
34732a550aecSAndrew Lunn struct mv88e6xxx_chip *chip = ds->priv;
34742a550aecSAndrew Lunn int ret = 0;
34752a550aecSAndrew Lunn
34767e951737SVladimir Oltean /* For families where we don't know how to alter the MTU,
34777e951737SVladimir Oltean * just accept any value up to ETH_DATA_LEN
34787e951737SVladimir Oltean */
34797e951737SVladimir Oltean if (!chip->info->ops->port_set_jumbo_size &&
34807e951737SVladimir Oltean !chip->info->ops->set_max_frame_size) {
34817e951737SVladimir Oltean if (new_mtu > ETH_DATA_LEN)
34827e951737SVladimir Oltean return -EINVAL;
34837e951737SVladimir Oltean
34847e951737SVladimir Oltean return 0;
34857e951737SVladimir Oltean }
34867e951737SVladimir Oltean
3487b9c587feSAndrew Lunn if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3488b9c587feSAndrew Lunn new_mtu += EDSA_HLEN;
3489b9c587feSAndrew Lunn
34902a550aecSAndrew Lunn mv88e6xxx_reg_lock(chip);
34912a550aecSAndrew Lunn if (chip->info->ops->port_set_jumbo_size)
34922a550aecSAndrew Lunn ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
34931baf0facSChris Packham else if (chip->info->ops->set_max_frame_size)
34941baf0facSChris Packham ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
34952a550aecSAndrew Lunn mv88e6xxx_reg_unlock(chip);
34962a550aecSAndrew Lunn
34972a550aecSAndrew Lunn return ret;
34982a550aecSAndrew Lunn }
34992a550aecSAndrew Lunn
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)35002cfcd964SVivien Didelot static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
35012cfcd964SVivien Didelot unsigned int ageing_time)
35022cfcd964SVivien Didelot {
350304bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
35042cfcd964SVivien Didelot int err;
35052cfcd964SVivien Didelot
3506c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
3507720c6343SVivien Didelot err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3508c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
35092cfcd964SVivien Didelot
35102cfcd964SVivien Didelot return err;
35112cfcd964SVivien Didelot }
35122cfcd964SVivien Didelot
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3513447b1bb8SVivien Didelot static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3514fad09c73SVivien Didelot {
3515fad09c73SVivien Didelot int err;
3516fad09c73SVivien Didelot
3517de227387SAndrew Lunn /* Initialize the statistics unit */
3518447b1bb8SVivien Didelot if (chip->info->ops->stats_set_histogram) {
3519447b1bb8SVivien Didelot err = chip->info->ops->stats_set_histogram(chip);
3520de227387SAndrew Lunn if (err)
3521de227387SAndrew Lunn return err;
3522447b1bb8SVivien Didelot }
3523de227387SAndrew Lunn
352440cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_clear(chip);
35259729934cSVivien Didelot }
35269729934cSVivien Didelot
3527ea89098eSAndrew Lunn /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3528ea89098eSAndrew Lunn static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3529ea89098eSAndrew Lunn {
3530ea89098eSAndrew Lunn int port;
3531ea89098eSAndrew Lunn int err;
3532ea89098eSAndrew Lunn u16 val;
3533ea89098eSAndrew Lunn
3534ea89098eSAndrew Lunn for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
353560907013SMarek Behún err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3536ea89098eSAndrew Lunn if (err) {
3537ea89098eSAndrew Lunn dev_err(chip->dev,
3538ea89098eSAndrew Lunn "Error reading hidden register: %d\n", err);
3539ea89098eSAndrew Lunn return false;
3540ea89098eSAndrew Lunn }
3541ea89098eSAndrew Lunn if (val != 0x01c0)
3542ea89098eSAndrew Lunn return false;
3543ea89098eSAndrew Lunn }
3544ea89098eSAndrew Lunn
3545ea89098eSAndrew Lunn return true;
3546ea89098eSAndrew Lunn }
3547ea89098eSAndrew Lunn
3548ea89098eSAndrew Lunn /* The 6390 copper ports have an errata which require poking magic
3549ea89098eSAndrew Lunn * values into undocumented hidden registers and then performing a
3550ea89098eSAndrew Lunn * software reset.
3551ea89098eSAndrew Lunn */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3552ea89098eSAndrew Lunn static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3553ea89098eSAndrew Lunn {
3554ea89098eSAndrew Lunn int port;
3555ea89098eSAndrew Lunn int err;
3556ea89098eSAndrew Lunn
3557ea89098eSAndrew Lunn if (mv88e6390_setup_errata_applied(chip))
3558ea89098eSAndrew Lunn return 0;
3559ea89098eSAndrew Lunn
3560ea89098eSAndrew Lunn /* Set the ports into blocking mode */
3561ea89098eSAndrew Lunn for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3562ea89098eSAndrew Lunn err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3563ea89098eSAndrew Lunn if (err)
3564ea89098eSAndrew Lunn return err;
3565ea89098eSAndrew Lunn }
3566ea89098eSAndrew Lunn
3567ea89098eSAndrew Lunn for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
356860907013SMarek Behún err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3569ea89098eSAndrew Lunn if (err)
3570ea89098eSAndrew Lunn return err;
3571ea89098eSAndrew Lunn }
3572ea89098eSAndrew Lunn
3573ea89098eSAndrew Lunn return mv88e6xxx_software_reset(chip);
3574ea89098eSAndrew Lunn }
3575ea89098eSAndrew Lunn
35761fe976d3SPali Rohár /* prod_id for switch families which do not have a PHY model number */
35771fe976d3SPali Rohár static const u16 family_prod_id_table[] = {
35781fe976d3SPali Rohár [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
35791fe976d3SPali Rohár [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3580c5d015b0SMarek Behún [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
35811fe976d3SPali Rohár };
35821fe976d3SPali Rohár
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3583e57e5e77SVivien Didelot static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3584fad09c73SVivien Didelot {
35850dd12d54SAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
35860dd12d54SAndrew Lunn struct mv88e6xxx_chip *chip = mdio_bus->chip;
35871fe976d3SPali Rohár u16 prod_id;
3588e57e5e77SVivien Didelot u16 val;
3589e57e5e77SVivien Didelot int err;
3590fad09c73SVivien Didelot
3591ee26a228SAndrew Lunn if (!chip->info->ops->phy_read)
3592ee26a228SAndrew Lunn return -EOPNOTSUPP;
3593ee26a228SAndrew Lunn
3594c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
3595ee26a228SAndrew Lunn err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3596c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
3597e57e5e77SVivien Didelot
3598ddc49acbSAndrew Lunn /* Some internal PHYs don't have a model number. */
35991fe976d3SPali Rohár if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
36001fe976d3SPali Rohár chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
36011fe976d3SPali Rohár prod_id = family_prod_id_table[chip->info->family];
36021fe976d3SPali Rohár if (prod_id)
36031fe976d3SPali Rohár val |= prod_id >> 4;
3604da9f3301SAndrew Lunn }
3605da9f3301SAndrew Lunn
3606e57e5e77SVivien Didelot return err ? err : val;
3607fad09c73SVivien Didelot }
3608fad09c73SVivien Didelot
mv88e6xxx_mdio_read_c45(struct mii_bus * bus,int phy,int devad,int reg)3609743a19e3SAndrew Lunn static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3610743a19e3SAndrew Lunn int reg)
3611743a19e3SAndrew Lunn {
3612743a19e3SAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3613743a19e3SAndrew Lunn struct mv88e6xxx_chip *chip = mdio_bus->chip;
3614743a19e3SAndrew Lunn u16 val;
3615743a19e3SAndrew Lunn int err;
3616743a19e3SAndrew Lunn
3617743a19e3SAndrew Lunn if (!chip->info->ops->phy_read_c45)
36180dc6bc63SAndrew Lunn return 0xffff;
3619743a19e3SAndrew Lunn
3620743a19e3SAndrew Lunn mv88e6xxx_reg_lock(chip);
3621743a19e3SAndrew Lunn err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3622743a19e3SAndrew Lunn mv88e6xxx_reg_unlock(chip);
3623743a19e3SAndrew Lunn
3624743a19e3SAndrew Lunn return err ? err : val;
3625743a19e3SAndrew Lunn }
3626743a19e3SAndrew Lunn
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3627e57e5e77SVivien Didelot static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3628fad09c73SVivien Didelot {
36290dd12d54SAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
36300dd12d54SAndrew Lunn struct mv88e6xxx_chip *chip = mdio_bus->chip;
3631e57e5e77SVivien Didelot int err;
3632fad09c73SVivien Didelot
3633ee26a228SAndrew Lunn if (!chip->info->ops->phy_write)
3634ee26a228SAndrew Lunn return -EOPNOTSUPP;
3635ee26a228SAndrew Lunn
3636c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
3637ee26a228SAndrew Lunn err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3638c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
3639e57e5e77SVivien Didelot
3640e57e5e77SVivien Didelot return err;
3641fad09c73SVivien Didelot }
3642fad09c73SVivien Didelot
mv88e6xxx_mdio_write_c45(struct mii_bus * bus,int phy,int devad,int reg,u16 val)3643743a19e3SAndrew Lunn static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3644743a19e3SAndrew Lunn int reg, u16 val)
3645743a19e3SAndrew Lunn {
3646743a19e3SAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3647743a19e3SAndrew Lunn struct mv88e6xxx_chip *chip = mdio_bus->chip;
3648743a19e3SAndrew Lunn int err;
3649743a19e3SAndrew Lunn
3650743a19e3SAndrew Lunn if (!chip->info->ops->phy_write_c45)
3651743a19e3SAndrew Lunn return -EOPNOTSUPP;
3652743a19e3SAndrew Lunn
3653743a19e3SAndrew Lunn mv88e6xxx_reg_lock(chip);
3654743a19e3SAndrew Lunn err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3655743a19e3SAndrew Lunn mv88e6xxx_reg_unlock(chip);
3656743a19e3SAndrew Lunn
3657743a19e3SAndrew Lunn return err;
3658743a19e3SAndrew Lunn }
3659743a19e3SAndrew Lunn
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3660fad09c73SVivien Didelot static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3661a3c53be5SAndrew Lunn struct device_node *np,
3662a3c53be5SAndrew Lunn bool external)
3663fad09c73SVivien Didelot {
3664fad09c73SVivien Didelot static int index;
36650dd12d54SAndrew Lunn struct mv88e6xxx_mdio_bus *mdio_bus;
3666fad09c73SVivien Didelot struct mii_bus *bus;
3667fad09c73SVivien Didelot int err;
3668fad09c73SVivien Didelot
36692510babcSAndrew Lunn if (external) {
3670c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
36712510babcSAndrew Lunn err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3672c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
36732510babcSAndrew Lunn
36742510babcSAndrew Lunn if (err)
36752510babcSAndrew Lunn return err;
36762510babcSAndrew Lunn }
36772510babcSAndrew Lunn
3678f53a2ce8SVladimir Oltean bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3679fad09c73SVivien Didelot if (!bus)
3680fad09c73SVivien Didelot return -ENOMEM;
3681fad09c73SVivien Didelot
36820dd12d54SAndrew Lunn mdio_bus = bus->priv;
3683a3c53be5SAndrew Lunn mdio_bus->bus = bus;
36840dd12d54SAndrew Lunn mdio_bus->chip = chip;
3685a3c53be5SAndrew Lunn INIT_LIST_HEAD(&mdio_bus->list);
3686a3c53be5SAndrew Lunn mdio_bus->external = external;
36870dd12d54SAndrew Lunn
3688fad09c73SVivien Didelot if (np) {
3689fad09c73SVivien Didelot bus->name = np->full_name;
3690f7ce9103SRob Herring snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3691fad09c73SVivien Didelot } else {
3692fad09c73SVivien Didelot bus->name = "mv88e6xxx SMI";
3693fad09c73SVivien Didelot snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3694fad09c73SVivien Didelot }
3695fad09c73SVivien Didelot
3696fad09c73SVivien Didelot bus->read = mv88e6xxx_mdio_read;
3697fad09c73SVivien Didelot bus->write = mv88e6xxx_mdio_write;
3698743a19e3SAndrew Lunn bus->read_c45 = mv88e6xxx_mdio_read_c45;
3699743a19e3SAndrew Lunn bus->write_c45 = mv88e6xxx_mdio_write_c45;
3700fad09c73SVivien Didelot bus->parent = chip->dev;
3701a4926c29SMarek Behún bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3702a4926c29SMarek Behún mv88e6xxx_num_ports(chip) - 1,
3703a4926c29SMarek Behún chip->info->phy_base_addr);
3704fad09c73SVivien Didelot
37056f88284fSAndrew Lunn if (!external) {
37066f88284fSAndrew Lunn err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
37076f88284fSAndrew Lunn if (err)
3708f53a2ce8SVladimir Oltean goto out;
37096f88284fSAndrew Lunn }
37106f88284fSAndrew Lunn
3711a3c53be5SAndrew Lunn err = of_mdiobus_register(bus, np);
3712fad09c73SVivien Didelot if (err) {
3713fad09c73SVivien Didelot dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
37146f88284fSAndrew Lunn mv88e6xxx_g2_irq_mdio_free(chip, bus);
3715f53a2ce8SVladimir Oltean goto out;
3716fad09c73SVivien Didelot }
3717fad09c73SVivien Didelot
3718a3c53be5SAndrew Lunn if (external)
3719a3c53be5SAndrew Lunn list_add_tail(&mdio_bus->list, &chip->mdios);
3720a3c53be5SAndrew Lunn else
3721a3c53be5SAndrew Lunn list_add(&mdio_bus->list, &chip->mdios);
3722a3c53be5SAndrew Lunn
3723a3c53be5SAndrew Lunn return 0;
3724f53a2ce8SVladimir Oltean
3725f53a2ce8SVladimir Oltean out:
3726f53a2ce8SVladimir Oltean mdiobus_free(bus);
3727f53a2ce8SVladimir Oltean return err;
3728a3c53be5SAndrew Lunn }
3729a3c53be5SAndrew Lunn
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)37303126aeecSAndrew Lunn static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
37313126aeecSAndrew Lunn
37323126aeecSAndrew Lunn {
373351a04ebfSVladimir Oltean struct mv88e6xxx_mdio_bus *mdio_bus, *p;
37343126aeecSAndrew Lunn struct mii_bus *bus;
37353126aeecSAndrew Lunn
373651a04ebfSVladimir Oltean list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
37373126aeecSAndrew Lunn bus = mdio_bus->bus;
37383126aeecSAndrew Lunn
37396f88284fSAndrew Lunn if (!mdio_bus->external)
37406f88284fSAndrew Lunn mv88e6xxx_g2_irq_mdio_free(chip, bus);
37416f88284fSAndrew Lunn
37423126aeecSAndrew Lunn mdiobus_unregister(bus);
3743f53a2ce8SVladimir Oltean mdiobus_free(bus);
37443126aeecSAndrew Lunn }
37453126aeecSAndrew Lunn }
37463126aeecSAndrew Lunn
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip)37472cb0658dSKlaus Kudielka static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3748a3c53be5SAndrew Lunn {
37492cb0658dSKlaus Kudielka struct device_node *np = chip->dev->of_node;
3750a3c53be5SAndrew Lunn struct device_node *child;
3751a3c53be5SAndrew Lunn int err;
3752a3c53be5SAndrew Lunn
3753a3c53be5SAndrew Lunn /* Always register one mdio bus for the internal/default mdio
3754a3c53be5SAndrew Lunn * bus. This maybe represented in the device tree, but is
3755a3c53be5SAndrew Lunn * optional.
3756a3c53be5SAndrew Lunn */
3757a3c53be5SAndrew Lunn child = of_get_child_by_name(np, "mdio");
3758a3c53be5SAndrew Lunn err = mv88e6xxx_mdio_register(chip, child, false);
375902ded5a1SMiaoqian Lin of_node_put(child);
3760a3c53be5SAndrew Lunn if (err)
3761a3c53be5SAndrew Lunn return err;
3762a3c53be5SAndrew Lunn
3763a3c53be5SAndrew Lunn /* Walk the device tree, and see if there are any other nodes
3764a3c53be5SAndrew Lunn * which say they are compatible with the external mdio
3765a3c53be5SAndrew Lunn * bus.
3766a3c53be5SAndrew Lunn */
3767a3c53be5SAndrew Lunn for_each_available_child_of_node(np, child) {
3768ceb96faeSAndrew Lunn if (of_device_is_compatible(
3769ceb96faeSAndrew Lunn child, "marvell,mv88e6xxx-mdio-external")) {
3770a3c53be5SAndrew Lunn err = mv88e6xxx_mdio_register(chip, child, true);
37713126aeecSAndrew Lunn if (err) {
37723126aeecSAndrew Lunn mv88e6xxx_mdios_unregister(chip);
377378e42040SNishka Dasgupta of_node_put(child);
3774a3c53be5SAndrew Lunn return err;
3775a3c53be5SAndrew Lunn }
3776a3c53be5SAndrew Lunn }
37773126aeecSAndrew Lunn }
3778a3c53be5SAndrew Lunn
3779a3c53be5SAndrew Lunn return 0;
3780a3c53be5SAndrew Lunn }
3781a3c53be5SAndrew Lunn
mv88e6xxx_teardown(struct dsa_switch * ds)3782f1bee740SKlaus Kudielka static void mv88e6xxx_teardown(struct dsa_switch *ds)
3783f1bee740SKlaus Kudielka {
37842cb0658dSKlaus Kudielka struct mv88e6xxx_chip *chip = ds->priv;
37852cb0658dSKlaus Kudielka
3786f1bee740SKlaus Kudielka mv88e6xxx_teardown_devlink_params(ds);
3787f1bee740SKlaus Kudielka dsa_devlink_resources_unregister(ds);
3788f1bee740SKlaus Kudielka mv88e6xxx_teardown_devlink_regions_global(ds);
37892cb0658dSKlaus Kudielka mv88e6xxx_mdios_unregister(chip);
3790f1bee740SKlaus Kudielka }
3791f1bee740SKlaus Kudielka
mv88e6xxx_setup(struct dsa_switch * ds)3792f1bee740SKlaus Kudielka static int mv88e6xxx_setup(struct dsa_switch *ds)
3793f1bee740SKlaus Kudielka {
3794f1bee740SKlaus Kudielka struct mv88e6xxx_chip *chip = ds->priv;
3795f1bee740SKlaus Kudielka u8 cmode;
3796f1bee740SKlaus Kudielka int err;
3797f1bee740SKlaus Kudielka int i;
3798f1bee740SKlaus Kudielka
37992cb0658dSKlaus Kudielka err = mv88e6xxx_mdios_register(chip);
38002cb0658dSKlaus Kudielka if (err)
38012cb0658dSKlaus Kudielka return err;
38022cb0658dSKlaus Kudielka
3803f1bee740SKlaus Kudielka chip->ds = ds;
3804f1bee740SKlaus Kudielka ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3805f1bee740SKlaus Kudielka
3806f1bee740SKlaus Kudielka /* Since virtual bridges are mapped in the PVT, the number we support
3807f1bee740SKlaus Kudielka * depends on the physical switch topology. We need to let DSA figure
3808f1bee740SKlaus Kudielka * that out and therefore we cannot set this at dsa_register_switch()
3809f1bee740SKlaus Kudielka * time.
3810f1bee740SKlaus Kudielka */
3811f1bee740SKlaus Kudielka if (mv88e6xxx_has_pvt(chip))
3812f1bee740SKlaus Kudielka ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3813f1bee740SKlaus Kudielka ds->dst->last_switch - 1;
3814f1bee740SKlaus Kudielka
3815f1bee740SKlaus Kudielka mv88e6xxx_reg_lock(chip);
3816f1bee740SKlaus Kudielka
3817f1bee740SKlaus Kudielka if (chip->info->ops->setup_errata) {
3818f1bee740SKlaus Kudielka err = chip->info->ops->setup_errata(chip);
3819f1bee740SKlaus Kudielka if (err)
3820f1bee740SKlaus Kudielka goto unlock;
3821f1bee740SKlaus Kudielka }
3822f1bee740SKlaus Kudielka
3823f1bee740SKlaus Kudielka /* Cache the cmode of each port. */
3824f1bee740SKlaus Kudielka for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3825f1bee740SKlaus Kudielka if (chip->info->ops->port_get_cmode) {
3826f1bee740SKlaus Kudielka err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3827f1bee740SKlaus Kudielka if (err)
3828f1bee740SKlaus Kudielka goto unlock;
3829f1bee740SKlaus Kudielka
3830f1bee740SKlaus Kudielka chip->ports[i].cmode = cmode;
3831f1bee740SKlaus Kudielka }
3832f1bee740SKlaus Kudielka }
3833f1bee740SKlaus Kudielka
3834f1bee740SKlaus Kudielka err = mv88e6xxx_vtu_setup(chip);
3835f1bee740SKlaus Kudielka if (err)
3836f1bee740SKlaus Kudielka goto unlock;
3837f1bee740SKlaus Kudielka
3838f1bee740SKlaus Kudielka /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3839f1bee740SKlaus Kudielka * VTU, thereby also flushing the STU).
3840f1bee740SKlaus Kudielka */
3841f1bee740SKlaus Kudielka err = mv88e6xxx_stu_setup(chip);
3842f1bee740SKlaus Kudielka if (err)
3843f1bee740SKlaus Kudielka goto unlock;
3844f1bee740SKlaus Kudielka
3845f1bee740SKlaus Kudielka /* Setup Switch Port Registers */
3846f1bee740SKlaus Kudielka for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3847f1bee740SKlaus Kudielka if (dsa_is_unused_port(ds, i))
3848f1bee740SKlaus Kudielka continue;
3849f1bee740SKlaus Kudielka
3850f1bee740SKlaus Kudielka /* Prevent the use of an invalid port. */
3851f1bee740SKlaus Kudielka if (mv88e6xxx_is_invalid_port(chip, i)) {
3852f1bee740SKlaus Kudielka dev_err(chip->dev, "port %d is invalid\n", i);
3853f1bee740SKlaus Kudielka err = -EINVAL;
3854f1bee740SKlaus Kudielka goto unlock;
3855f1bee740SKlaus Kudielka }
3856f1bee740SKlaus Kudielka
3857f1bee740SKlaus Kudielka err = mv88e6xxx_setup_port(chip, i);
3858f1bee740SKlaus Kudielka if (err)
3859f1bee740SKlaus Kudielka goto unlock;
3860f1bee740SKlaus Kudielka }
3861f1bee740SKlaus Kudielka
3862f1bee740SKlaus Kudielka err = mv88e6xxx_irl_setup(chip);
3863f1bee740SKlaus Kudielka if (err)
3864f1bee740SKlaus Kudielka goto unlock;
3865f1bee740SKlaus Kudielka
3866f1bee740SKlaus Kudielka err = mv88e6xxx_mac_setup(chip);
3867f1bee740SKlaus Kudielka if (err)
3868f1bee740SKlaus Kudielka goto unlock;
3869f1bee740SKlaus Kudielka
3870f1bee740SKlaus Kudielka err = mv88e6xxx_phy_setup(chip);
3871f1bee740SKlaus Kudielka if (err)
3872f1bee740SKlaus Kudielka goto unlock;
3873f1bee740SKlaus Kudielka
3874f1bee740SKlaus Kudielka err = mv88e6xxx_pvt_setup(chip);
3875f1bee740SKlaus Kudielka if (err)
3876f1bee740SKlaus Kudielka goto unlock;
3877f1bee740SKlaus Kudielka
3878f1bee740SKlaus Kudielka err = mv88e6xxx_atu_setup(chip);
3879f1bee740SKlaus Kudielka if (err)
3880f1bee740SKlaus Kudielka goto unlock;
3881f1bee740SKlaus Kudielka
3882f1bee740SKlaus Kudielka err = mv88e6xxx_broadcast_setup(chip, 0);
3883f1bee740SKlaus Kudielka if (err)
3884f1bee740SKlaus Kudielka goto unlock;
3885f1bee740SKlaus Kudielka
3886f1bee740SKlaus Kudielka err = mv88e6xxx_pot_setup(chip);
3887f1bee740SKlaus Kudielka if (err)
3888f1bee740SKlaus Kudielka goto unlock;
3889f1bee740SKlaus Kudielka
3890f1bee740SKlaus Kudielka err = mv88e6xxx_rmu_setup(chip);
3891f1bee740SKlaus Kudielka if (err)
3892f1bee740SKlaus Kudielka goto unlock;
3893f1bee740SKlaus Kudielka
3894f1bee740SKlaus Kudielka err = mv88e6xxx_rsvd2cpu_setup(chip);
3895f1bee740SKlaus Kudielka if (err)
3896f1bee740SKlaus Kudielka goto unlock;
3897f1bee740SKlaus Kudielka
3898f1bee740SKlaus Kudielka err = mv88e6xxx_trunk_setup(chip);
3899f1bee740SKlaus Kudielka if (err)
3900f1bee740SKlaus Kudielka goto unlock;
3901f1bee740SKlaus Kudielka
3902f1bee740SKlaus Kudielka err = mv88e6xxx_devmap_setup(chip);
3903f1bee740SKlaus Kudielka if (err)
3904f1bee740SKlaus Kudielka goto unlock;
3905f1bee740SKlaus Kudielka
3906f1bee740SKlaus Kudielka err = mv88e6xxx_pri_setup(chip);
3907f1bee740SKlaus Kudielka if (err)
3908f1bee740SKlaus Kudielka goto unlock;
3909f1bee740SKlaus Kudielka
3910f1bee740SKlaus Kudielka /* Setup PTP Hardware Clock and timestamping */
3911f1bee740SKlaus Kudielka if (chip->info->ptp_support) {
3912f1bee740SKlaus Kudielka err = mv88e6xxx_ptp_setup(chip);
3913f1bee740SKlaus Kudielka if (err)
3914f1bee740SKlaus Kudielka goto unlock;
3915f1bee740SKlaus Kudielka
3916f1bee740SKlaus Kudielka err = mv88e6xxx_hwtstamp_setup(chip);
3917f1bee740SKlaus Kudielka if (err)
3918f1bee740SKlaus Kudielka goto unlock;
3919f1bee740SKlaus Kudielka }
3920f1bee740SKlaus Kudielka
3921f1bee740SKlaus Kudielka err = mv88e6xxx_stats_setup(chip);
3922f1bee740SKlaus Kudielka if (err)
3923f1bee740SKlaus Kudielka goto unlock;
3924f1bee740SKlaus Kudielka
3925f1bee740SKlaus Kudielka unlock:
3926f1bee740SKlaus Kudielka mv88e6xxx_reg_unlock(chip);
3927f1bee740SKlaus Kudielka
3928f1bee740SKlaus Kudielka if (err)
39292cb0658dSKlaus Kudielka goto out_mdios;
3930f1bee740SKlaus Kudielka
3931f1bee740SKlaus Kudielka /* Have to be called without holding the register lock, since
3932f1bee740SKlaus Kudielka * they take the devlink lock, and we later take the locks in
3933f1bee740SKlaus Kudielka * the reverse order when getting/setting parameters or
3934f1bee740SKlaus Kudielka * resource occupancy.
3935f1bee740SKlaus Kudielka */
3936f1bee740SKlaus Kudielka err = mv88e6xxx_setup_devlink_resources(ds);
3937f1bee740SKlaus Kudielka if (err)
39382cb0658dSKlaus Kudielka goto out_mdios;
3939f1bee740SKlaus Kudielka
3940f1bee740SKlaus Kudielka err = mv88e6xxx_setup_devlink_params(ds);
3941f1bee740SKlaus Kudielka if (err)
3942f1bee740SKlaus Kudielka goto out_resources;
3943f1bee740SKlaus Kudielka
3944f1bee740SKlaus Kudielka err = mv88e6xxx_setup_devlink_regions_global(ds);
3945f1bee740SKlaus Kudielka if (err)
3946f1bee740SKlaus Kudielka goto out_params;
3947f1bee740SKlaus Kudielka
3948f1bee740SKlaus Kudielka return 0;
3949f1bee740SKlaus Kudielka
3950f1bee740SKlaus Kudielka out_params:
3951f1bee740SKlaus Kudielka mv88e6xxx_teardown_devlink_params(ds);
3952f1bee740SKlaus Kudielka out_resources:
3953f1bee740SKlaus Kudielka dsa_devlink_resources_unregister(ds);
39542cb0658dSKlaus Kudielka out_mdios:
39552cb0658dSKlaus Kudielka mv88e6xxx_mdios_unregister(chip);
3956f1bee740SKlaus Kudielka
3957f1bee740SKlaus Kudielka return err;
3958f1bee740SKlaus Kudielka }
3959f1bee740SKlaus Kudielka
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)3960f1bee740SKlaus Kudielka static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3961f1bee740SKlaus Kudielka {
3962b92143d4SRussell King (Oracle) struct mv88e6xxx_chip *chip = ds->priv;
3963b92143d4SRussell King (Oracle) int err;
3964b92143d4SRussell King (Oracle)
39653a5fb574SGreg Ungerer if (chip->info->ops->pcs_ops &&
39663a5fb574SGreg Ungerer chip->info->ops->pcs_ops->pcs_init) {
3967b92143d4SRussell King (Oracle) err = chip->info->ops->pcs_ops->pcs_init(chip, port);
3968b92143d4SRussell King (Oracle) if (err)
3969b92143d4SRussell King (Oracle) return err;
3970b92143d4SRussell King (Oracle) }
3971b92143d4SRussell King (Oracle)
3972f1bee740SKlaus Kudielka return mv88e6xxx_setup_devlink_regions_port(ds, port);
3973f1bee740SKlaus Kudielka }
3974f1bee740SKlaus Kudielka
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)3975f1bee740SKlaus Kudielka static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3976f1bee740SKlaus Kudielka {
3977b92143d4SRussell King (Oracle) struct mv88e6xxx_chip *chip = ds->priv;
3978b92143d4SRussell King (Oracle)
3979f1bee740SKlaus Kudielka mv88e6xxx_teardown_devlink_regions_port(ds, port);
3980b92143d4SRussell King (Oracle)
39813a5fb574SGreg Ungerer if (chip->info->ops->pcs_ops &&
39823a5fb574SGreg Ungerer chip->info->ops->pcs_ops->pcs_teardown)
3983b92143d4SRussell King (Oracle) chip->info->ops->pcs_ops->pcs_teardown(chip, port);
3984f1bee740SKlaus Kudielka }
3985f1bee740SKlaus Kudielka
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)3986855b1932SVivien Didelot static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3987855b1932SVivien Didelot {
398804bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
3989855b1932SVivien Didelot
3990855b1932SVivien Didelot return chip->eeprom_len;
3991855b1932SVivien Didelot }
3992855b1932SVivien Didelot
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3993855b1932SVivien Didelot static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3994855b1932SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data)
3995855b1932SVivien Didelot {
399604bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
3997855b1932SVivien Didelot int err;
3998855b1932SVivien Didelot
3999ee4dc2e7SVivien Didelot if (!chip->info->ops->get_eeprom)
4000ee4dc2e7SVivien Didelot return -EOPNOTSUPP;
4001ee4dc2e7SVivien Didelot
4002c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
4003ee4dc2e7SVivien Didelot err = chip->info->ops->get_eeprom(chip, eeprom, data);
4004c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
4005855b1932SVivien Didelot
4006855b1932SVivien Didelot if (err)
4007855b1932SVivien Didelot return err;
4008855b1932SVivien Didelot
4009855b1932SVivien Didelot eeprom->magic = 0xc3ec4951;
4010855b1932SVivien Didelot
4011855b1932SVivien Didelot return 0;
4012855b1932SVivien Didelot }
4013855b1932SVivien Didelot
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4014855b1932SVivien Didelot static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4015855b1932SVivien Didelot struct ethtool_eeprom *eeprom, u8 *data)
4016855b1932SVivien Didelot {
401704bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
4018855b1932SVivien Didelot int err;
4019855b1932SVivien Didelot
4020ee4dc2e7SVivien Didelot if (!chip->info->ops->set_eeprom)
4021ee4dc2e7SVivien Didelot return -EOPNOTSUPP;
4022ee4dc2e7SVivien Didelot
4023855b1932SVivien Didelot if (eeprom->magic != 0xc3ec4951)
4024855b1932SVivien Didelot return -EINVAL;
4025855b1932SVivien Didelot
4026c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
4027ee4dc2e7SVivien Didelot err = chip->info->ops->set_eeprom(chip, eeprom, data);
4028c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
4029855b1932SVivien Didelot
4030855b1932SVivien Didelot return err;
4031855b1932SVivien Didelot }
4032855b1932SVivien Didelot
4033b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6085_ops = {
40344b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6097 */
403593e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
403693e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4037cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4038b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
40397e20cfb5SVivien Didelot .phy_read = mv88e6185_phy_ppu_read,
40407e20cfb5SVivien Didelot .phy_write = mv88e6185_phy_ppu_write,
404108ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
40424efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4043f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4044ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
404545f22f2fSAngelo Dureghello .port_set_policy = mv88e6352_port_set_policy,
404656995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4047a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4048a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
404956995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4050ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
40510898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4052c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
40539dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
40542d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4055121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4056a605a0feSAndrew Lunn .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
405740cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4058dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4059dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4060052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4061fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4062fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4063fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
406451c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
40659e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4066a199d8b6SVivien Didelot .ppu_enable = mv88e6185_g1_ppu_enable,
4067a199d8b6SVivien Didelot .ppu_disable = mv88e6185_g1_ppu_disable,
406817e708baSVivien Didelot .reset = mv88e6185_g1_reset,
40699e5baf9bSVivien Didelot .rmu_disable = mv88e6085_g1_rmu_disable,
4070f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
40710ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4072c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4073c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4074d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6185_phylink_get_caps,
40751baf0facSChris Packham .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4076b3469dd8SVivien Didelot };
4077b3469dd8SVivien Didelot
4078b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6095_ops = {
40794b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6095 */
408093e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
408193e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4082b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
40837e20cfb5SVivien Didelot .phy_read = mv88e6185_phy_ppu_read,
40847e20cfb5SVivien Didelot .phy_write = mv88e6185_phy_ppu_write,
408508ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
40864efe7662SChris Packham .port_sync_link = mv88e6185_port_sync_link,
4087f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
408856995cbcSAndrew Lunn .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4089a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4090a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4091a23b2961SAndrew Lunn .port_set_upstream_port = mv88e6095_port_set_upstream_port,
40922d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4093121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4094a605a0feSAndrew Lunn .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
409540cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4096dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4097dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4098052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
409951c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4100a199d8b6SVivien Didelot .ppu_enable = mv88e6185_g1_ppu_enable,
4101a199d8b6SVivien Didelot .ppu_disable = mv88e6185_g1_ppu_disable,
410217e708baSVivien Didelot .reset = mv88e6185_g1_reset,
4103f1394b78SVivien Didelot .vtu_getnext = mv88e6185_g1_vtu_getnext,
41040ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4105d0b78ab1STobias Waldekranz .phylink_get_caps = mv88e6095_phylink_get_caps,
41064aabe35cSRussell King (Oracle) .pcs_ops = &mv88e6185_pcs_ops,
41071baf0facSChris Packham .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4108b3469dd8SVivien Didelot };
4109b3469dd8SVivien Didelot
41107d381a02SStefan Eichenberger static const struct mv88e6xxx_ops mv88e6097_ops = {
411115da3cc8SStefan Eichenberger /* MV88E6XXX_FAMILY_6097 */
411293e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
411393e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4114cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
41157d381a02SStefan Eichenberger .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4116743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4117743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4118743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4119743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
41207d381a02SStefan Eichenberger .port_set_link = mv88e6xxx_port_set_link,
41214efe7662SChris Packham .port_sync_link = mv88e6185_port_sync_link,
4122f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4123ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
4124585d42bbSTobias Waldekranz .port_set_policy = mv88e6352_port_set_policy,
412556995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4126a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4127a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
412856995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4129ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
41300898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4131c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
41329dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
41332d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4134121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
41357d381a02SStefan Eichenberger .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
413640cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
41377d381a02SStefan Eichenberger .stats_get_sset_count = mv88e6095_stats_get_sset_count,
41387d381a02SStefan Eichenberger .stats_get_strings = mv88e6095_stats_get_strings,
41397d381a02SStefan Eichenberger .stats_get_stats = mv88e6095_stats_get_stats,
4140fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4141fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
414291eaa475SVolodymyr Bendiuga .watchdog_ops = &mv88e6097_watchdog_ops,
414351c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
41445c19bc8bSChris Packham .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
41459e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
414617e708baSVivien Didelot .reset = mv88e6352_g1_reset,
41479e5baf9bSVivien Didelot .rmu_disable = mv88e6085_g1_rmu_disable,
4148f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
41490ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4150d0b78ab1STobias Waldekranz .phylink_get_caps = mv88e6095_phylink_get_caps,
41514aabe35cSRussell King (Oracle) .pcs_ops = &mv88e6185_pcs_ops,
415249c98c1dSTobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
415349c98c1dSTobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
41541baf0facSChris Packham .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
41557d381a02SStefan Eichenberger };
41567d381a02SStefan Eichenberger
4157b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6123_ops = {
41584b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6165 */
415993e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
416093e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4161cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4162b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4163743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4164743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4165743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4166743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
416708ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
41684efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4169f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
417056995cbcSAndrew Lunn .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4171a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4172a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4173c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
41749dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
41752d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4176121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
41770ac64c39SAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
417840cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4179dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4180dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4181052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4182fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4183fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4184fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
418551c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
41869e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
418717e708baSVivien Didelot .reset = mv88e6352_g1_reset,
418823e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
418923e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4190f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
41910ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4192c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4193c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4194d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6185_phylink_get_caps,
41951baf0facSChris Packham .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4196b3469dd8SVivien Didelot };
4197b3469dd8SVivien Didelot
4198b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6131_ops = {
41994b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6185 */
420093e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
420193e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4202b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
42037e20cfb5SVivien Didelot .phy_read = mv88e6185_phy_ppu_read,
42047e20cfb5SVivien Didelot .phy_write = mv88e6185_phy_ppu_write,
420508ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
42064efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4207f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4208ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
420956995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4210a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4211a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6185_port_set_default_forward,
421256995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4213a23b2961SAndrew Lunn .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4214cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4215ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
42160898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
421754186b91SAndrew Lunn .port_set_pause = mv88e6185_port_set_pause,
42182d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4219121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4220a605a0feSAndrew Lunn .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
422140cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4222dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4223dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4224052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4225fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4226fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4227fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
422851c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4229a199d8b6SVivien Didelot .ppu_enable = mv88e6185_g1_ppu_enable,
423002317e68SVivien Didelot .set_cascade_port = mv88e6185_g1_set_cascade_port,
4231a199d8b6SVivien Didelot .ppu_disable = mv88e6185_g1_ppu_disable,
423217e708baSVivien Didelot .reset = mv88e6185_g1_reset,
4233f1394b78SVivien Didelot .vtu_getnext = mv88e6185_g1_vtu_getnext,
42340ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4235d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6185_phylink_get_caps,
4236b3469dd8SVivien Didelot };
4237b3469dd8SVivien Didelot
4238990e27b0SVivien Didelot static const struct mv88e6xxx_ops mv88e6141_ops = {
4239990e27b0SVivien Didelot /* MV88E6XXX_FAMILY_6341 */
424093e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
424193e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4242cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4243990e27b0SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4244990e27b0SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4245990e27b0SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4246743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4247743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4248743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4249743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4250990e27b0SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
42514efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4252990e27b0SVivien Didelot .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4253f365c6f7SRussell King .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
42547cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4255990e27b0SVivien Didelot .port_tag_remap = mv88e6095_port_tag_remap,
42567da467d8SMarek Behún .port_set_policy = mv88e6352_port_set_policy,
4257990e27b0SVivien Didelot .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4258a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4259a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4260990e27b0SVivien Didelot .port_set_ether_type = mv88e6351_port_set_ether_type,
4261cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4262990e27b0SVivien Didelot .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
42630898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4264990e27b0SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4265990e27b0SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
42662d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
42677a3007d2SMarek Behún .port_set_cmode = mv88e6341_port_set_cmode,
4268121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4269990e27b0SVivien Didelot .stats_snapshot = mv88e6390_g1_stats_snapshot,
427011527f3cSMarek Behún .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4271990e27b0SVivien Didelot .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4272990e27b0SVivien Didelot .stats_get_strings = mv88e6320_stats_get_strings,
4273990e27b0SVivien Didelot .stats_get_stats = mv88e6390_stats_get_stats,
4274fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
4275fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
4276990e27b0SVivien Didelot .watchdog_ops = &mv88e6390_watchdog_ops,
4277990e27b0SVivien Didelot .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
42789e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4279d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4280d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4281990e27b0SVivien Didelot .reset = mv88e6352_g1_reset,
428237094887SMarek Behún .rmu_disable = mv88e6390_g1_rmu_disable,
4283c07fff34SMarek Behún .atu_get_hash = mv88e6165_g1_atu_get_hash,
4284c07fff34SMarek Behún .atu_set_hash = mv88e6165_g1_atu_set_hash,
4285f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
42860ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4287c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4288c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4289d3cf7d8fSMarek Behún .serdes_get_lane = mv88e6341_serdes_get_lane,
42904241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4291a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
4292a03b98d6SMarek Behún .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4293a03b98d6SMarek Behún .serdes_get_strings = mv88e6390_serdes_get_strings,
4294a03b98d6SMarek Behún .serdes_get_stats = mv88e6390_serdes_get_stats,
4295953b0dcbSMarek Behún .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4296953b0dcbSMarek Behún .serdes_get_regs = mv88e6390_serdes_get_regs,
4297d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6341_phylink_get_caps,
4298e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
4299990e27b0SVivien Didelot };
4300990e27b0SVivien Didelot
4301b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6161_ops = {
43024b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6165 */
430393e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
430493e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4305cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4306b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4307743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4308743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4309743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4310743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
431108ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
43124efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4313f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4314ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
431545f22f2fSAngelo Dureghello .port_set_policy = mv88e6352_port_set_policy,
431656995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4317a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4318a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
431956995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4320ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
43210898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4322c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
43239dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
43242d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4325121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4326a6da21bbSAndrew Lunn .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
432740cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4328dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4329dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4330052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4331fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4332fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4333fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
433451c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
43359e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
433617e708baSVivien Didelot .reset = mv88e6352_g1_reset,
433723e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
433823e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4339f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
43400ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4341c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4342c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4343a469a612SAndrew Lunn .avb_ops = &mv88e6165_avb_ops,
4344dfa54348SAndrew Lunn .ptp_ops = &mv88e6165_ptp_ops,
4345d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6185_phylink_get_caps,
4346fe230361SAndrew Lunn .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4347b3469dd8SVivien Didelot };
4348b3469dd8SVivien Didelot
4349b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6165_ops = {
43504b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6165 */
435193e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
435293e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4353cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4354b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4355efb3e74dSAndrew Lunn .phy_read = mv88e6165_phy_read,
4356efb3e74dSAndrew Lunn .phy_write = mv88e6165_phy_write,
435708ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
43584efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4359f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4360c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
43619dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
43622d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4363121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4364a605a0feSAndrew Lunn .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
436540cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4366dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4367dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4368052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4369fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4370fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4371fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
437251c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
43739e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
437417e708baSVivien Didelot .reset = mv88e6352_g1_reset,
437523e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
437623e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4377f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
43780ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4379c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4380c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4381a469a612SAndrew Lunn .avb_ops = &mv88e6165_avb_ops,
4382dfa54348SAndrew Lunn .ptp_ops = &mv88e6165_ptp_ops,
4383d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6185_phylink_get_caps,
4384b3469dd8SVivien Didelot };
4385b3469dd8SVivien Didelot
4386b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6171_ops = {
43874b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6351 */
438893e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
438993e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4390cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4391b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4392743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4393743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4394743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4395743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
439608ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
43974efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
439894d66ae6SAndrew Lunn .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4399f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4400ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
440156995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4402a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4403a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
440456995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4405cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4406ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
44070898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4408c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
44099dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
44102d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4411121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4412a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
441340cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4414dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4415dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4416052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4417fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4418fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4419fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
442051c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
44219e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
442217e708baSVivien Didelot .reset = mv88e6352_g1_reset,
442323e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
442423e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4425f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
44260ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4427c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4428c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
44295cc4ed20SGreg Ungerer .phylink_get_caps = mv88e6351_phylink_get_caps,
4430b3469dd8SVivien Didelot };
4431b3469dd8SVivien Didelot
4432b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6172_ops = {
44334b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6352 */
443493e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
443593e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4436cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4437ee4dc2e7SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4438ee4dc2e7SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4439b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4440743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4441743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4442743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4443743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
444408ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
44454efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4446a0a0f622SVivien Didelot .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4447f365c6f7SRussell King .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4448ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
4449f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
445056995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4451a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4452a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
445356995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4454cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4455ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
44560898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4457c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
44589dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
44592d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4460121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4461a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
446240cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4463dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4464dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4465052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4466fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4467fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4468fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
446951c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
44709e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4471d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4472d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
447317e708baSVivien Didelot .reset = mv88e6352_g1_reset,
44749e5baf9bSVivien Didelot .rmu_disable = mv88e6352_g1_rmu_disable,
447523e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
447623e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4477f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
44780ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4479c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4480c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4481d3f88a24SAndrew Lunn .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4482d3f88a24SAndrew Lunn .serdes_get_regs = mv88e6352_serdes_get_regs,
4483a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
4484d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6352_phylink_get_caps,
448585764555SRussell King .pcs_ops = &mv88e6352_pcs_ops,
4486b3469dd8SVivien Didelot };
4487b3469dd8SVivien Didelot
4488b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6175_ops = {
44894b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6351 */
449093e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
449193e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4492cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4493b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4494743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4495743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4496743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4497743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
449808ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
44994efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
450094d66ae6SAndrew Lunn .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4501f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4502ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
450356995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4504a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4505a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
450656995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4507cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4508ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
45090898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4510c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
45119dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
45122d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4513121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4514a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
451540cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4516dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4517dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4518052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4519fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4520fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4521fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
452251c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
45239e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
452417e708baSVivien Didelot .reset = mv88e6352_g1_reset,
452523e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
452623e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4527f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
45280ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4529c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4530c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
45315cc4ed20SGreg Ungerer .phylink_get_caps = mv88e6351_phylink_get_caps,
4532b3469dd8SVivien Didelot };
4533b3469dd8SVivien Didelot
4534b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6176_ops = {
45354b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6352 */
453693e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
453793e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4538cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4539ee4dc2e7SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4540ee4dc2e7SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4541b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4542743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4543743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4544743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4545743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
454608ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
45474efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4548a0a0f622SVivien Didelot .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4549f365c6f7SRussell King .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4550ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
4551f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
455256995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4553a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4554a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
455556995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4556cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4557ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
45580898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4559c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
45609dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
45612d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4562121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4563a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
456440cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4565dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4566dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4567052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4568fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4569fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4570fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
457151c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
45729e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4573d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4574d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
457517e708baSVivien Didelot .reset = mv88e6352_g1_reset,
45769e5baf9bSVivien Didelot .rmu_disable = mv88e6352_g1_rmu_disable,
457723e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
457823e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4579f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
45800ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4581c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4582c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
45834241ef52SVivien Didelot .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4584d3f88a24SAndrew Lunn .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4585d3f88a24SAndrew Lunn .serdes_get_regs = mv88e6352_serdes_get_regs,
4586926eae60SHolger Brunck .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4587a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
4588d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6352_phylink_get_caps,
458985764555SRussell King .pcs_ops = &mv88e6352_pcs_ops,
4590b3469dd8SVivien Didelot };
4591b3469dd8SVivien Didelot
4592b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6185_ops = {
45934b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6185 */
459493e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
459593e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4596b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
45977e20cfb5SVivien Didelot .phy_read = mv88e6185_phy_ppu_read,
45987e20cfb5SVivien Didelot .phy_write = mv88e6185_phy_ppu_write,
459908ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
46004efe7662SChris Packham .port_sync_link = mv88e6185_port_sync_link,
4601f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
460256995cbcSAndrew Lunn .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4603a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4604a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4605ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4606a23b2961SAndrew Lunn .port_set_upstream_port = mv88e6095_port_set_upstream_port,
460754186b91SAndrew Lunn .port_set_pause = mv88e6185_port_set_pause,
46082d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6185_port_get_cmode,
4609121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4610a605a0feSAndrew Lunn .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
461140cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4612dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4613dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4614052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4615fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4616fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4617fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
461851c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
461902317e68SVivien Didelot .set_cascade_port = mv88e6185_g1_set_cascade_port,
4620a199d8b6SVivien Didelot .ppu_enable = mv88e6185_g1_ppu_enable,
4621a199d8b6SVivien Didelot .ppu_disable = mv88e6185_g1_ppu_disable,
462217e708baSVivien Didelot .reset = mv88e6185_g1_reset,
4623f1394b78SVivien Didelot .vtu_getnext = mv88e6185_g1_vtu_getnext,
46240ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4625d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6185_phylink_get_caps,
46264aabe35cSRussell King (Oracle) .pcs_ops = &mv88e6185_pcs_ops,
46271baf0facSChris Packham .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4628b3469dd8SVivien Didelot };
4629b3469dd8SVivien Didelot
46301a3b39ecSAndrew Lunn static const struct mv88e6xxx_ops mv88e6190_ops = {
46314b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6390 */
4632ea89098eSAndrew Lunn .setup_errata = mv88e6390_setup_errata,
4633cd8da8bbSVivien Didelot .irl_init_all = mv88e6390_g2_irl_init_all,
463498fc3c6fSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
463598fc3c6fSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
46361a3b39ecSAndrew Lunn .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4637743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4638743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4639743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4640743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
46411a3b39ecSAndrew Lunn .port_set_link = mv88e6xxx_port_set_link,
46424efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
46431a3b39ecSAndrew Lunn .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4644f365c6f7SRussell King .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
46457cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4646ef0a7318SAndrew Lunn .port_tag_remap = mv88e6390_port_tag_remap,
4647f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
464856995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4649a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4650a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
465156995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4652e8b34c67SChris Packham .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
46530898432cSVivien Didelot .port_pause_limit = mv88e6390_port_pause_limit,
4654c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
46559dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
46562d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4657fdc71eeaSAndrew Lunn .port_set_cmode = mv88e6390_port_set_cmode,
4658121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
465979523473SAndrew Lunn .stats_snapshot = mv88e6390_g1_stats_snapshot,
4660de227387SAndrew Lunn .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4661dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4662dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
4663e0d8b615SAndrew Lunn .stats_get_stats = mv88e6390_stats_get_stats,
4664fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
4665fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
466661303736SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
46676e55f698SAndrew Lunn .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
46689e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4669d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4670d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
467117e708baSVivien Didelot .reset = mv88e6352_g1_reset,
46729e5baf9bSVivien Didelot .rmu_disable = mv88e6390_g1_rmu_disable,
467323e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
467423e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4675931d1822SVivien Didelot .vtu_getnext = mv88e6390_g1_vtu_getnext,
4676931d1822SVivien Didelot .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4677c050f5e9STobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
4678c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
467917deaf5cSMarek Behún .serdes_get_lane = mv88e6390_serdes_get_lane,
46804241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
46814262c38dSAndrew Lunn .serdes_get_strings = mv88e6390_serdes_get_strings,
46824262c38dSAndrew Lunn .serdes_get_stats = mv88e6390_serdes_get_stats,
4683bf3504ceSAndrew Lunn .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4684bf3504ceSAndrew Lunn .serdes_get_regs = mv88e6390_serdes_get_regs,
4685a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
4686d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6390_phylink_get_caps,
4687e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
46881a3b39ecSAndrew Lunn };
46891a3b39ecSAndrew Lunn
46901a3b39ecSAndrew Lunn static const struct mv88e6xxx_ops mv88e6190x_ops = {
46914b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6390 */
4692ea89098eSAndrew Lunn .setup_errata = mv88e6390_setup_errata,
4693cd8da8bbSVivien Didelot .irl_init_all = mv88e6390_g2_irl_init_all,
469498fc3c6fSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
469598fc3c6fSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
46961a3b39ecSAndrew Lunn .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4697743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4698743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4699743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4700743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
47011a3b39ecSAndrew Lunn .port_set_link = mv88e6xxx_port_set_link,
47024efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
47031a3b39ecSAndrew Lunn .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4704f365c6f7SRussell King .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
47057cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4706ef0a7318SAndrew Lunn .port_tag_remap = mv88e6390_port_tag_remap,
4707f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
470856995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4709a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4710a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
471156995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4712e8b34c67SChris Packham .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
47130898432cSVivien Didelot .port_pause_limit = mv88e6390_port_pause_limit,
4714c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
47159dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
47162d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4717fdc71eeaSAndrew Lunn .port_set_cmode = mv88e6390x_port_set_cmode,
4718121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
471979523473SAndrew Lunn .stats_snapshot = mv88e6390_g1_stats_snapshot,
4720de227387SAndrew Lunn .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4721dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4722dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
4723e0d8b615SAndrew Lunn .stats_get_stats = mv88e6390_stats_get_stats,
4724fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
4725fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
472661303736SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
47276e55f698SAndrew Lunn .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
47289e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4729d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4730d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
473117e708baSVivien Didelot .reset = mv88e6352_g1_reset,
47329e5baf9bSVivien Didelot .rmu_disable = mv88e6390_g1_rmu_disable,
473323e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
473423e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4735931d1822SVivien Didelot .vtu_getnext = mv88e6390_g1_vtu_getnext,
4736931d1822SVivien Didelot .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4737c050f5e9STobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
4738c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
473917deaf5cSMarek Behún .serdes_get_lane = mv88e6390x_serdes_get_lane,
47404241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
47414262c38dSAndrew Lunn .serdes_get_strings = mv88e6390_serdes_get_strings,
47424262c38dSAndrew Lunn .serdes_get_stats = mv88e6390_serdes_get_stats,
4743bf3504ceSAndrew Lunn .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4744bf3504ceSAndrew Lunn .serdes_get_regs = mv88e6390_serdes_get_regs,
4745a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
4746d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6390x_phylink_get_caps,
4747e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
47481a3b39ecSAndrew Lunn };
47491a3b39ecSAndrew Lunn
47501a3b39ecSAndrew Lunn static const struct mv88e6xxx_ops mv88e6191_ops = {
47514b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6390 */
4752ea89098eSAndrew Lunn .setup_errata = mv88e6390_setup_errata,
4753cd8da8bbSVivien Didelot .irl_init_all = mv88e6390_g2_irl_init_all,
475498fc3c6fSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
475598fc3c6fSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
47561a3b39ecSAndrew Lunn .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4757743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4758743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4759743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4760743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
47611a3b39ecSAndrew Lunn .port_set_link = mv88e6xxx_port_set_link,
47624efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
47631a3b39ecSAndrew Lunn .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4764f365c6f7SRussell King .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
47657cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4766ef0a7318SAndrew Lunn .port_tag_remap = mv88e6390_port_tag_remap,
476756995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4768a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4769a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
477056995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
47710898432cSVivien Didelot .port_pause_limit = mv88e6390_port_pause_limit,
4772c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
47739dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
47742d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4775fdc71eeaSAndrew Lunn .port_set_cmode = mv88e6390_port_set_cmode,
4776121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
477779523473SAndrew Lunn .stats_snapshot = mv88e6390_g1_stats_snapshot,
4778de227387SAndrew Lunn .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4779dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4780dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
4781e0d8b615SAndrew Lunn .stats_get_stats = mv88e6390_stats_get_stats,
4782fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
4783fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
478461303736SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
47856e55f698SAndrew Lunn .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
47869e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4787d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4788d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
478917e708baSVivien Didelot .reset = mv88e6352_g1_reset,
47909e5baf9bSVivien Didelot .rmu_disable = mv88e6390_g1_rmu_disable,
479123e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
479223e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4793931d1822SVivien Didelot .vtu_getnext = mv88e6390_g1_vtu_getnext,
4794931d1822SVivien Didelot .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4795c050f5e9STobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
4796c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
479717deaf5cSMarek Behún .serdes_get_lane = mv88e6390_serdes_get_lane,
47984241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
47994262c38dSAndrew Lunn .serdes_get_strings = mv88e6390_serdes_get_strings,
48004262c38dSAndrew Lunn .serdes_get_stats = mv88e6390_serdes_get_stats,
4801bf3504ceSAndrew Lunn .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4802bf3504ceSAndrew Lunn .serdes_get_regs = mv88e6390_serdes_get_regs,
48036d2ac8eeSAndrew Lunn .avb_ops = &mv88e6390_avb_ops,
48046d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
4805d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6390_phylink_get_caps,
4806e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
48071a3b39ecSAndrew Lunn };
48081a3b39ecSAndrew Lunn
4809b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6240_ops = {
48104b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6352 */
481193e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
481293e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4813cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4814ee4dc2e7SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4815ee4dc2e7SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4816b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4817743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4818743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4819743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4820743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
482108ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
48224efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
4823a0a0f622SVivien Didelot .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4824f365c6f7SRussell King .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4825ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
4826f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
482756995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4828a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4829a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
483056995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4831cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4832ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
48330898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4834c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
48359dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
48362d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4837121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
4838a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
483940cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4840dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4841dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
4842052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
4843fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
4844fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
4845fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
484651c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
48479e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4848d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4849d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
485017e708baSVivien Didelot .reset = mv88e6352_g1_reset,
48519e5baf9bSVivien Didelot .rmu_disable = mv88e6352_g1_rmu_disable,
485223e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
485323e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4854f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
48550ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4856c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
4857c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
48584241ef52SVivien Didelot .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4859d3f88a24SAndrew Lunn .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4860d3f88a24SAndrew Lunn .serdes_get_regs = mv88e6352_serdes_get_regs,
4861926eae60SHolger Brunck .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4862a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
48630d632c3dSBrandon Streiff .avb_ops = &mv88e6352_avb_ops,
48646d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
4865d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6352_phylink_get_caps,
486685764555SRussell King .pcs_ops = &mv88e6352_pcs_ops,
4867b3469dd8SVivien Didelot };
4868b3469dd8SVivien Didelot
48691f71836fSRasmus Villemoes static const struct mv88e6xxx_ops mv88e6250_ops = {
48701f71836fSRasmus Villemoes /* MV88E6XXX_FAMILY_6250 */
48711f71836fSRasmus Villemoes .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
48721f71836fSRasmus Villemoes .ip_pri_map = mv88e6085_g1_ip_pri_map,
48731f71836fSRasmus Villemoes .irl_init_all = mv88e6352_g2_irl_init_all,
48741f71836fSRasmus Villemoes .get_eeprom = mv88e6xxx_g2_get_eeprom16,
48751f71836fSRasmus Villemoes .set_eeprom = mv88e6xxx_g2_set_eeprom16,
48761f71836fSRasmus Villemoes .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4877743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4878743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4879743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4880743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
48811f71836fSRasmus Villemoes .port_set_link = mv88e6xxx_port_set_link,
48824efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
48831f71836fSRasmus Villemoes .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4884f365c6f7SRussell King .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
48851f71836fSRasmus Villemoes .port_tag_remap = mv88e6095_port_tag_remap,
48861f71836fSRasmus Villemoes .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4887a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4888a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
48891f71836fSRasmus Villemoes .port_set_ether_type = mv88e6351_port_set_ether_type,
48901f71836fSRasmus Villemoes .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
48911f71836fSRasmus Villemoes .port_pause_limit = mv88e6097_port_pause_limit,
48921f71836fSRasmus Villemoes .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
48931f71836fSRasmus Villemoes .stats_snapshot = mv88e6320_g1_stats_snapshot,
48941f71836fSRasmus Villemoes .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
48951f71836fSRasmus Villemoes .stats_get_sset_count = mv88e6250_stats_get_sset_count,
48961f71836fSRasmus Villemoes .stats_get_strings = mv88e6250_stats_get_strings,
48971f71836fSRasmus Villemoes .stats_get_stats = mv88e6250_stats_get_stats,
48981f71836fSRasmus Villemoes .set_cpu_port = mv88e6095_g1_set_cpu_port,
48991f71836fSRasmus Villemoes .set_egress_port = mv88e6095_g1_set_egress_port,
49001f71836fSRasmus Villemoes .watchdog_ops = &mv88e6250_watchdog_ops,
49011f71836fSRasmus Villemoes .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
49021f71836fSRasmus Villemoes .pot_clear = mv88e6xxx_g2_pot_clear,
4903a4702791SMatthias Schiffer .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
4904a4702791SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
49051f71836fSRasmus Villemoes .reset = mv88e6250_g1_reset,
490667c9ed1cSRasmus Villemoes .vtu_getnext = mv88e6185_g1_vtu_getnext,
4907b28f3f3cSRasmus Villemoes .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
490871509614SHubert Feurstein .avb_ops = &mv88e6352_avb_ops,
490971509614SHubert Feurstein .ptp_ops = &mv88e6250_ptp_ops,
4910d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6250_phylink_get_caps,
4911dd4144e5SLukasz Majewski .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
49121f71836fSRasmus Villemoes };
49131f71836fSRasmus Villemoes
49141a3b39ecSAndrew Lunn static const struct mv88e6xxx_ops mv88e6290_ops = {
49154b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6390 */
4916ea89098eSAndrew Lunn .setup_errata = mv88e6390_setup_errata,
4917cd8da8bbSVivien Didelot .irl_init_all = mv88e6390_g2_irl_init_all,
491898fc3c6fSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
491998fc3c6fSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
49201a3b39ecSAndrew Lunn .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4921743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4922743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4923743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4924743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
49251a3b39ecSAndrew Lunn .port_set_link = mv88e6xxx_port_set_link,
49264efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
49271a3b39ecSAndrew Lunn .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4928f365c6f7SRussell King .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
49297cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4930ef0a7318SAndrew Lunn .port_tag_remap = mv88e6390_port_tag_remap,
4931f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
493256995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4933a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4934a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
493556995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
49360898432cSVivien Didelot .port_pause_limit = mv88e6390_port_pause_limit,
4937c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
49389dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
49392d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
4940fdc71eeaSAndrew Lunn .port_set_cmode = mv88e6390_port_set_cmode,
4941121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
494279523473SAndrew Lunn .stats_snapshot = mv88e6390_g1_stats_snapshot,
4943de227387SAndrew Lunn .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4944dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4945dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
4946e0d8b615SAndrew Lunn .stats_get_stats = mv88e6390_stats_get_stats,
4947fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
4948fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
494961303736SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
49506e55f698SAndrew Lunn .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
49519e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
4952d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4953d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
495417e708baSVivien Didelot .reset = mv88e6352_g1_reset,
49559e5baf9bSVivien Didelot .rmu_disable = mv88e6390_g1_rmu_disable,
495623e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
495723e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
4958931d1822SVivien Didelot .vtu_getnext = mv88e6390_g1_vtu_getnext,
4959931d1822SVivien Didelot .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4960c050f5e9STobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
4961c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
496217deaf5cSMarek Behún .serdes_get_lane = mv88e6390_serdes_get_lane,
49634241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
49644262c38dSAndrew Lunn .serdes_get_strings = mv88e6390_serdes_get_strings,
49654262c38dSAndrew Lunn .serdes_get_stats = mv88e6390_serdes_get_stats,
4966bf3504ceSAndrew Lunn .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4967bf3504ceSAndrew Lunn .serdes_get_regs = mv88e6390_serdes_get_regs,
4968a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
49690d632c3dSBrandon Streiff .avb_ops = &mv88e6390_avb_ops,
49709627c981SKurt Kanzenbach .ptp_ops = &mv88e6390_ptp_ops,
4971d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6390_phylink_get_caps,
4972e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
49731a3b39ecSAndrew Lunn };
49741a3b39ecSAndrew Lunn
4975b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6320_ops = {
49764b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6320 */
497793e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
497893e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
4979cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
4980ee4dc2e7SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4981ee4dc2e7SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4982b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4983743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4984743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4985743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4986743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
498708ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
49884efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
498991e87045SSteffen Bätz .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
4990f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4991ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
499256995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4993a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4994a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
499556995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
4996cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4997ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
49980898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
4999c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
50009dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
50012d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5002121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
5003a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
500440cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5005dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5006dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
5007052f947fSAndrew Lunn .stats_get_stats = mv88e6320_stats_get_stats,
5008fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
5009fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
50109c7f37e5SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
501151c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
50129e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
5013d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5014d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
501517e708baSVivien Didelot .reset = mv88e6352_g1_reset,
5016f1394b78SVivien Didelot .vtu_getnext = mv88e6185_g1_vtu_getnext,
50170ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5018a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
50190d632c3dSBrandon Streiff .avb_ops = &mv88e6352_avb_ops,
50206d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
50217019a641SSteffen Bätz .phylink_get_caps = mv88e632x_phylink_get_caps,
5022b3469dd8SVivien Didelot };
5023b3469dd8SVivien Didelot
5024b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6321_ops = {
5025bd807204SVivien Didelot /* MV88E6XXX_FAMILY_6320 */
502693e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
502793e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
5028cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
5029ee4dc2e7SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5030ee4dc2e7SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5031b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5032743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5033743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5034743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5035743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
503608ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
50374efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
503891e87045SSteffen Bätz .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5039f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5040ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
504156995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5042a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5043a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
504456995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
5045cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5046ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
50470898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
5048c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
50499dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
50502d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5051121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
5052a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
505340cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5054dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5055dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
5056052f947fSAndrew Lunn .stats_get_stats = mv88e6320_stats_get_stats,
5057fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
5058fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
50599c7f37e5SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
506066863178SAngelo Dureghello .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5061d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5062d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
506317e708baSVivien Didelot .reset = mv88e6352_g1_reset,
5064f1394b78SVivien Didelot .vtu_getnext = mv88e6185_g1_vtu_getnext,
50650ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5066a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
50670d632c3dSBrandon Streiff .avb_ops = &mv88e6352_avb_ops,
50686d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
50697019a641SSteffen Bätz .phylink_get_caps = mv88e632x_phylink_get_caps,
5070b3469dd8SVivien Didelot };
5071b3469dd8SVivien Didelot
507216e329aeSVivien Didelot static const struct mv88e6xxx_ops mv88e6341_ops = {
507316e329aeSVivien Didelot /* MV88E6XXX_FAMILY_6341 */
507493e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
507593e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
5076cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
507716e329aeSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
507816e329aeSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
507916e329aeSVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5080743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5081743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5082743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5083743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
508416e329aeSVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
50854efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
508616e329aeSVivien Didelot .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5087f365c6f7SRussell King .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
50887cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6341_port_max_speed_mode,
508916e329aeSVivien Didelot .port_tag_remap = mv88e6095_port_tag_remap,
50907da467d8SMarek Behún .port_set_policy = mv88e6352_port_set_policy,
509116e329aeSVivien Didelot .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5092a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5093a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
509416e329aeSVivien Didelot .port_set_ether_type = mv88e6351_port_set_ether_type,
5095cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
509616e329aeSVivien Didelot .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
50970898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
509816e329aeSVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
509916e329aeSVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
51002d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
51017a3007d2SMarek Behún .port_set_cmode = mv88e6341_port_set_cmode,
5102121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
510316e329aeSVivien Didelot .stats_snapshot = mv88e6390_g1_stats_snapshot,
510411527f3cSMarek Behún .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
510516e329aeSVivien Didelot .stats_get_sset_count = mv88e6320_stats_get_sset_count,
510616e329aeSVivien Didelot .stats_get_strings = mv88e6320_stats_get_strings,
510716e329aeSVivien Didelot .stats_get_stats = mv88e6390_stats_get_stats,
5108fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
5109fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
511016e329aeSVivien Didelot .watchdog_ops = &mv88e6390_watchdog_ops,
511116e329aeSVivien Didelot .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
51129e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
5113d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5114d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
511516e329aeSVivien Didelot .reset = mv88e6352_g1_reset,
511637094887SMarek Behún .rmu_disable = mv88e6390_g1_rmu_disable,
5117c07fff34SMarek Behún .atu_get_hash = mv88e6165_g1_atu_get_hash,
5118c07fff34SMarek Behún .atu_set_hash = mv88e6165_g1_atu_set_hash,
5119f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
51200ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5121c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
5122c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5123d3cf7d8fSMarek Behún .serdes_get_lane = mv88e6341_serdes_get_lane,
51244241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5125a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
51260d632c3dSBrandon Streiff .avb_ops = &mv88e6390_avb_ops,
51276d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
5128a03b98d6SMarek Behún .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5129a03b98d6SMarek Behún .serdes_get_strings = mv88e6390_serdes_get_strings,
5130a03b98d6SMarek Behún .serdes_get_stats = mv88e6390_serdes_get_stats,
5131953b0dcbSMarek Behún .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5132953b0dcbSMarek Behún .serdes_get_regs = mv88e6390_serdes_get_regs,
5133d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6341_phylink_get_caps,
5134e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
513516e329aeSVivien Didelot };
513616e329aeSVivien Didelot
5137b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6350_ops = {
51384b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6351 */
513993e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
514093e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
5141cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
5142b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5143743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5144743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5145743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5146743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
514708ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
51484efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
514994d66ae6SAndrew Lunn .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5150f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5151ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
515256995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5153a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5154a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
515556995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
5156cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5157ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
51580898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
5159c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
51609dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
51612d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5162121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
5163a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
516440cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5165dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5166dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
5167052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
5168fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
5169fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
5170fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
517151c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
51729e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
517317e708baSVivien Didelot .reset = mv88e6352_g1_reset,
517423e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
517523e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
5176f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
51770ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5178c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
5179c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
51805cc4ed20SGreg Ungerer .phylink_get_caps = mv88e6351_phylink_get_caps,
5181b3469dd8SVivien Didelot };
5182b3469dd8SVivien Didelot
5183b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6351_ops = {
51844b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6351 */
518593e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
518693e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
5187cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
5188b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5189743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5190743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5191743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5192743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
519308ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
51944efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
519594d66ae6SAndrew Lunn .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5196f365c6f7SRussell King .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5197ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
519856995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5199a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5200a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
520156995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
5202cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5203ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
52040898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
5205c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
52069dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
52072d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5208121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
5209a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
521040cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5211dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5212dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
5213052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
5214fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
5215fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
5216fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
521751c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
52189e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
521917e708baSVivien Didelot .reset = mv88e6352_g1_reset,
522023e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
522123e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
5222f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
52230ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5224c050f5e9STobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
5225c050f5e9STobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
52260d632c3dSBrandon Streiff .avb_ops = &mv88e6352_avb_ops,
52276d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
52285cc4ed20SGreg Ungerer .phylink_get_caps = mv88e6351_phylink_get_caps,
5229b3469dd8SVivien Didelot };
5230b3469dd8SVivien Didelot
5231b3469dd8SVivien Didelot static const struct mv88e6xxx_ops mv88e6352_ops = {
52324b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6352 */
523393e18d61SVivien Didelot .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
523493e18d61SVivien Didelot .ip_pri_map = mv88e6085_g1_ip_pri_map,
5235cd8da8bbSVivien Didelot .irl_init_all = mv88e6352_g2_irl_init_all,
5236ee4dc2e7SVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5237ee4dc2e7SVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5238b073d4e2SVivien Didelot .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5239743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5240743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5241743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5242743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
524308ef7f10SVivien Didelot .port_set_link = mv88e6xxx_port_set_link,
52444efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
5245a0a0f622SVivien Didelot .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5246f365c6f7SRussell King .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5247ef0a7318SAndrew Lunn .port_tag_remap = mv88e6095_port_tag_remap,
5248f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
524956995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5250a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5251a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
525256995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
5253cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5254ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
52550898432cSVivien Didelot .port_pause_limit = mv88e6097_port_pause_limit,
5256c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
52579dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
52582d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5259121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
5260a605a0feSAndrew Lunn .stats_snapshot = mv88e6320_g1_stats_snapshot,
526140cff8fcSAndrew Lunn .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5262dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5263dfafe449SAndrew Lunn .stats_get_strings = mv88e6095_stats_get_strings,
5264052f947fSAndrew Lunn .stats_get_stats = mv88e6095_stats_get_stats,
5265fa8d1179SVivien Didelot .set_cpu_port = mv88e6095_g1_set_cpu_port,
5266fa8d1179SVivien Didelot .set_egress_port = mv88e6095_g1_set_egress_port,
5267fcd25166SAndrew Lunn .watchdog_ops = &mv88e6097_watchdog_ops,
526851c901a7SVivien Didelot .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
52699e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
5270d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5271d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
527217e708baSVivien Didelot .reset = mv88e6352_g1_reset,
52739e5baf9bSVivien Didelot .rmu_disable = mv88e6352_g1_rmu_disable,
527423e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
527523e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
5276f1394b78SVivien Didelot .vtu_getnext = mv88e6352_g1_vtu_getnext,
52770ad5daf6SVivien Didelot .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
527849c98c1dSTobias Waldekranz .stu_getnext = mv88e6352_g1_stu_getnext,
527949c98c1dSTobias Waldekranz .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
52804241ef52SVivien Didelot .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5281a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
52820d632c3dSBrandon Streiff .avb_ops = &mv88e6352_avb_ops,
52836d2ac8eeSAndrew Lunn .ptp_ops = &mv88e6352_ptp_ops,
5284cda9f4aaSAndrew Lunn .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5285cda9f4aaSAndrew Lunn .serdes_get_strings = mv88e6352_serdes_get_strings,
5286cda9f4aaSAndrew Lunn .serdes_get_stats = mv88e6352_serdes_get_stats,
5287d3f88a24SAndrew Lunn .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5288d3f88a24SAndrew Lunn .serdes_get_regs = mv88e6352_serdes_get_regs,
5289926eae60SHolger Brunck .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5290d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6352_phylink_get_caps,
529185764555SRussell King .pcs_ops = &mv88e6352_pcs_ops,
5292b3469dd8SVivien Didelot };
5293b3469dd8SVivien Didelot
52941a3b39ecSAndrew Lunn static const struct mv88e6xxx_ops mv88e6390_ops = {
52954b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6390 */
5296ea89098eSAndrew Lunn .setup_errata = mv88e6390_setup_errata,
5297cd8da8bbSVivien Didelot .irl_init_all = mv88e6390_g2_irl_init_all,
529898fc3c6fSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
529998fc3c6fSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
53001a3b39ecSAndrew Lunn .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5301743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5302743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5303743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5304743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
53051a3b39ecSAndrew Lunn .port_set_link = mv88e6xxx_port_set_link,
53064efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
53071a3b39ecSAndrew Lunn .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5308f365c6f7SRussell King .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
53097cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5310ef0a7318SAndrew Lunn .port_tag_remap = mv88e6390_port_tag_remap,
5311f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
531256995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5313a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5314a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
531556995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
5316cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5317ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
53180898432cSVivien Didelot .port_pause_limit = mv88e6390_port_pause_limit,
5319c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
53209dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
53212d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5322fdc71eeaSAndrew Lunn .port_set_cmode = mv88e6390_port_set_cmode,
5323121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
532479523473SAndrew Lunn .stats_snapshot = mv88e6390_g1_stats_snapshot,
5325de227387SAndrew Lunn .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5326dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5327dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
5328e0d8b615SAndrew Lunn .stats_get_stats = mv88e6390_stats_get_stats,
5329fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
5330fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
533161303736SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
53326e55f698SAndrew Lunn .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
53339e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
5334d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5335d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
533617e708baSVivien Didelot .reset = mv88e6352_g1_reset,
53379e5baf9bSVivien Didelot .rmu_disable = mv88e6390_g1_rmu_disable,
533823e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
533923e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
5340931d1822SVivien Didelot .vtu_getnext = mv88e6390_g1_vtu_getnext,
5341931d1822SVivien Didelot .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
534249c98c1dSTobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
534349c98c1dSTobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
534417deaf5cSMarek Behún .serdes_get_lane = mv88e6390_serdes_get_lane,
53454241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5346a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
53470d632c3dSBrandon Streiff .avb_ops = &mv88e6390_avb_ops,
53489627c981SKurt Kanzenbach .ptp_ops = &mv88e6390_ptp_ops,
53490df95287SNikita Yushchenko .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
53500df95287SNikita Yushchenko .serdes_get_strings = mv88e6390_serdes_get_strings,
53510df95287SNikita Yushchenko .serdes_get_stats = mv88e6390_serdes_get_stats,
5352bf3504ceSAndrew Lunn .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5353bf3504ceSAndrew Lunn .serdes_get_regs = mv88e6390_serdes_get_regs,
5354d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6390_phylink_get_caps,
5355e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
53561a3b39ecSAndrew Lunn };
53571a3b39ecSAndrew Lunn
53581a3b39ecSAndrew Lunn static const struct mv88e6xxx_ops mv88e6390x_ops = {
53594b325d8cSAndrew Lunn /* MV88E6XXX_FAMILY_6390 */
5360ea89098eSAndrew Lunn .setup_errata = mv88e6390_setup_errata,
5361cd8da8bbSVivien Didelot .irl_init_all = mv88e6390_g2_irl_init_all,
536298fc3c6fSVivien Didelot .get_eeprom = mv88e6xxx_g2_get_eeprom8,
536398fc3c6fSVivien Didelot .set_eeprom = mv88e6xxx_g2_set_eeprom8,
53641a3b39ecSAndrew Lunn .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5365743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5366743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5367743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5368743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
53691a3b39ecSAndrew Lunn .port_set_link = mv88e6xxx_port_set_link,
53704efe7662SChris Packham .port_sync_link = mv88e6xxx_port_sync_link,
53711a3b39ecSAndrew Lunn .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5372f365c6f7SRussell King .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
53737cbbee05SAndrew Lunn .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5374ef0a7318SAndrew Lunn .port_tag_remap = mv88e6390_port_tag_remap,
5375f3a2cd32SVivien Didelot .port_set_policy = mv88e6352_port_set_policy,
537656995cbcSAndrew Lunn .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5377a8b659e7SVladimir Oltean .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5378a8b659e7SVladimir Oltean .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
537956995cbcSAndrew Lunn .port_set_ether_type = mv88e6351_port_set_ether_type,
5380cd782656SVivien Didelot .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5381ef70b111SAndrew Lunn .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
53820898432cSVivien Didelot .port_pause_limit = mv88e6390_port_pause_limit,
5383c8c94891SVivien Didelot .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
53849dbfb4e1SVivien Didelot .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
53852d2e1dd2SAndrew Lunn .port_get_cmode = mv88e6352_port_get_cmode,
5386b3dce4daSAndrew Lunn .port_set_cmode = mv88e6390x_port_set_cmode,
5387121b8fe2SHubert Feurstein .port_setup_message_port = mv88e6xxx_setup_message_port,
538879523473SAndrew Lunn .stats_snapshot = mv88e6390_g1_stats_snapshot,
5389de227387SAndrew Lunn .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5390dfafe449SAndrew Lunn .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5391dfafe449SAndrew Lunn .stats_get_strings = mv88e6320_stats_get_strings,
5392e0d8b615SAndrew Lunn .stats_get_stats = mv88e6390_stats_get_stats,
5393fa8d1179SVivien Didelot .set_cpu_port = mv88e6390_g1_set_cpu_port,
5394fa8d1179SVivien Didelot .set_egress_port = mv88e6390_g1_set_egress_port,
539561303736SAndrew Lunn .watchdog_ops = &mv88e6390_watchdog_ops,
53966e55f698SAndrew Lunn .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
53979e907d73SVivien Didelot .pot_clear = mv88e6xxx_g2_pot_clear,
5398d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5399d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
540017e708baSVivien Didelot .reset = mv88e6352_g1_reset,
54019e5baf9bSVivien Didelot .rmu_disable = mv88e6390_g1_rmu_disable,
540223e8b470SAndrew Lunn .atu_get_hash = mv88e6165_g1_atu_get_hash,
540323e8b470SAndrew Lunn .atu_set_hash = mv88e6165_g1_atu_set_hash,
5404931d1822SVivien Didelot .vtu_getnext = mv88e6390_g1_vtu_getnext,
5405931d1822SVivien Didelot .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
540649c98c1dSTobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
540749c98c1dSTobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
540817deaf5cSMarek Behún .serdes_get_lane = mv88e6390x_serdes_get_lane,
54094241ef52SVivien Didelot .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
54104262c38dSAndrew Lunn .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
54114262c38dSAndrew Lunn .serdes_get_strings = mv88e6390_serdes_get_strings,
54124262c38dSAndrew Lunn .serdes_get_stats = mv88e6390_serdes_get_stats,
5413bf3504ceSAndrew Lunn .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5414bf3504ceSAndrew Lunn .serdes_get_regs = mv88e6390_serdes_get_regs,
5415a73ccd61SBrandon Streiff .gpio_ops = &mv88e6352_gpio_ops,
54160d632c3dSBrandon Streiff .avb_ops = &mv88e6390_avb_ops,
54179627c981SKurt Kanzenbach .ptp_ops = &mv88e6390_ptp_ops,
5418d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6390x_phylink_get_caps,
5419e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6390_pcs_ops,
54201a3b39ecSAndrew Lunn };
54211a3b39ecSAndrew Lunn
5422de776d0dSPavana Sharma static const struct mv88e6xxx_ops mv88e6393x_ops = {
5423de776d0dSPavana Sharma /* MV88E6XXX_FAMILY_6393 */
5424de776d0dSPavana Sharma .irl_init_all = mv88e6390_g2_irl_init_all,
5425de776d0dSPavana Sharma .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5426de776d0dSPavana Sharma .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5427de776d0dSPavana Sharma .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5428743a19e3SAndrew Lunn .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5429743a19e3SAndrew Lunn .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5430743a19e3SAndrew Lunn .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5431743a19e3SAndrew Lunn .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5432de776d0dSPavana Sharma .port_set_link = mv88e6xxx_port_set_link,
5433de776d0dSPavana Sharma .port_sync_link = mv88e6xxx_port_sync_link,
5434de776d0dSPavana Sharma .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5435de776d0dSPavana Sharma .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5436de776d0dSPavana Sharma .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5437de776d0dSPavana Sharma .port_tag_remap = mv88e6390_port_tag_remap,
54386584b260SMarek Behún .port_set_policy = mv88e6393x_port_set_policy,
5439de776d0dSPavana Sharma .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5440de776d0dSPavana Sharma .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5441de776d0dSPavana Sharma .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5442de776d0dSPavana Sharma .port_set_ether_type = mv88e6393x_port_set_ether_type,
5443de776d0dSPavana Sharma .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5444de776d0dSPavana Sharma .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5445de776d0dSPavana Sharma .port_pause_limit = mv88e6390_port_pause_limit,
5446de776d0dSPavana Sharma .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5447de776d0dSPavana Sharma .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5448de776d0dSPavana Sharma .port_get_cmode = mv88e6352_port_get_cmode,
5449de776d0dSPavana Sharma .port_set_cmode = mv88e6393x_port_set_cmode,
5450de776d0dSPavana Sharma .port_setup_message_port = mv88e6xxx_setup_message_port,
5451de776d0dSPavana Sharma .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5452de776d0dSPavana Sharma .stats_snapshot = mv88e6390_g1_stats_snapshot,
5453de776d0dSPavana Sharma .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5454de776d0dSPavana Sharma .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5455de776d0dSPavana Sharma .stats_get_strings = mv88e6320_stats_get_strings,
5456de776d0dSPavana Sharma .stats_get_stats = mv88e6390_stats_get_stats,
5457de776d0dSPavana Sharma /* .set_cpu_port is missing because this family does not support a global
5458de776d0dSPavana Sharma * CPU port, only per port CPU port which is set via
5459de776d0dSPavana Sharma * .port_set_upstream_port method.
5460de776d0dSPavana Sharma */
5461de776d0dSPavana Sharma .set_egress_port = mv88e6393x_set_egress_port,
5462089b91a0SGustav Ekelund .watchdog_ops = &mv88e6393x_watchdog_ops,
5463de776d0dSPavana Sharma .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5464de776d0dSPavana Sharma .pot_clear = mv88e6xxx_g2_pot_clear,
5465d1e3dc19SMatthias Schiffer .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5466d1e3dc19SMatthias Schiffer .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5467de776d0dSPavana Sharma .reset = mv88e6352_g1_reset,
5468de776d0dSPavana Sharma .rmu_disable = mv88e6390_g1_rmu_disable,
5469de776d0dSPavana Sharma .atu_get_hash = mv88e6165_g1_atu_get_hash,
5470de776d0dSPavana Sharma .atu_set_hash = mv88e6165_g1_atu_set_hash,
5471de776d0dSPavana Sharma .vtu_getnext = mv88e6390_g1_vtu_getnext,
5472de776d0dSPavana Sharma .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
547349c98c1dSTobias Waldekranz .stu_getnext = mv88e6390_g1_stu_getnext,
547449c98c1dSTobias Waldekranz .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5475de776d0dSPavana Sharma .serdes_get_lane = mv88e6393x_serdes_get_lane,
5476de776d0dSPavana Sharma .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5477de776d0dSPavana Sharma /* TODO: serdes stats */
5478de776d0dSPavana Sharma .gpio_ops = &mv88e6352_gpio_ops,
5479de776d0dSPavana Sharma .avb_ops = &mv88e6390_avb_ops,
5480de776d0dSPavana Sharma .ptp_ops = &mv88e6352_ptp_ops,
5481d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6393x_phylink_get_caps,
5482e5b732a2SRussell King (Oracle) .pcs_ops = &mv88e6393x_pcs_ops,
5483de776d0dSPavana Sharma };
5484de776d0dSPavana Sharma
5485fad09c73SVivien Didelot static const struct mv88e6xxx_info mv88e6xxx_table[] = {
548671d94a43SMatthias Schiffer [MV88E6020] = {
548771d94a43SMatthias Schiffer .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
548871d94a43SMatthias Schiffer .family = MV88E6XXX_FAMILY_6250,
548971d94a43SMatthias Schiffer .name = "Marvell 88E6020",
549071d94a43SMatthias Schiffer .num_databases = 64,
549123e1c686SMichael Krummsdorf /* Ports 2-4 are not routed to pins
549223e1c686SMichael Krummsdorf * => usable ports 0, 1, 5, 6
549323e1c686SMichael Krummsdorf */
549423e1c686SMichael Krummsdorf .num_ports = 7,
549571d94a43SMatthias Schiffer .num_internal_phys = 2,
549623e1c686SMichael Krummsdorf .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
549771d94a43SMatthias Schiffer .max_vid = 4095,
549871d94a43SMatthias Schiffer .port_base_addr = 0x8,
549971d94a43SMatthias Schiffer .phy_base_addr = 0x0,
550071d94a43SMatthias Schiffer .global1_addr = 0xf,
550171d94a43SMatthias Schiffer .global2_addr = 0x7,
550271d94a43SMatthias Schiffer .age_time_coeff = 15000,
550371d94a43SMatthias Schiffer .g1_irqs = 9,
550471d94a43SMatthias Schiffer .g2_irqs = 5,
550571d94a43SMatthias Schiffer .atu_move_port_mask = 0xf,
550671d94a43SMatthias Schiffer .dual_chip = true,
550771d94a43SMatthias Schiffer .ops = &mv88e6250_ops,
550871d94a43SMatthias Schiffer },
550971d94a43SMatthias Schiffer
5510372188c8SLukasz Majewski [MV88E6071] = {
5511372188c8SLukasz Majewski .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5512372188c8SLukasz Majewski .family = MV88E6XXX_FAMILY_6250,
5513372188c8SLukasz Majewski .name = "Marvell 88E6071",
5514372188c8SLukasz Majewski .num_databases = 64,
5515372188c8SLukasz Majewski .num_ports = 7,
5516372188c8SLukasz Majewski .num_internal_phys = 5,
5517372188c8SLukasz Majewski .max_vid = 4095,
5518372188c8SLukasz Majewski .port_base_addr = 0x08,
5519372188c8SLukasz Majewski .phy_base_addr = 0x00,
5520372188c8SLukasz Majewski .global1_addr = 0x0f,
5521372188c8SLukasz Majewski .global2_addr = 0x07,
5522372188c8SLukasz Majewski .age_time_coeff = 15000,
5523372188c8SLukasz Majewski .g1_irqs = 9,
5524372188c8SLukasz Majewski .g2_irqs = 5,
5525372188c8SLukasz Majewski .atu_move_port_mask = 0xf,
5526372188c8SLukasz Majewski .dual_chip = true,
5527372188c8SLukasz Majewski .ops = &mv88e6250_ops,
5528372188c8SLukasz Majewski },
5529372188c8SLukasz Majewski
5530fad09c73SVivien Didelot [MV88E6085] = {
5531107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5532fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6097,
5533fad09c73SVivien Didelot .name = "Marvell 88E6085",
5534fad09c73SVivien Didelot .num_databases = 4096,
5535d9ea5620SAndrew Lunn .num_macs = 8192,
5536fad09c73SVivien Didelot .num_ports = 10,
5537bc393155SAndrew Lunn .num_internal_phys = 5,
55383cf3c846SVivien Didelot .max_vid = 4095,
5539c050f5e9STobias Waldekranz .max_sid = 63,
5540fad09c73SVivien Didelot .port_base_addr = 0x10,
55419255bacdSAndrew Lunn .phy_base_addr = 0x0,
5542a935c052SVivien Didelot .global1_addr = 0x1b,
55439069c13aSVivien Didelot .global2_addr = 0x1c,
5544acddbd21SVivien Didelot .age_time_coeff = 15000,
5545dc30c35bSAndrew Lunn .g1_irqs = 8,
5546d6c5e6afSVivien Didelot .g2_irqs = 10,
5547e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5548f3645652SVivien Didelot .pvt = true,
5549b3e05aa1SVivien Didelot .multi_chip = true,
5550b3469dd8SVivien Didelot .ops = &mv88e6085_ops,
5551fad09c73SVivien Didelot },
5552fad09c73SVivien Didelot
5553fad09c73SVivien Didelot [MV88E6095] = {
5554107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5555fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6095,
5556fad09c73SVivien Didelot .name = "Marvell 88E6095/88E6095F",
5557fad09c73SVivien Didelot .num_databases = 256,
5558d9ea5620SAndrew Lunn .num_macs = 8192,
5559fad09c73SVivien Didelot .num_ports = 11,
5560bc393155SAndrew Lunn .num_internal_phys = 0,
55613cf3c846SVivien Didelot .max_vid = 4095,
5562fad09c73SVivien Didelot .port_base_addr = 0x10,
55639255bacdSAndrew Lunn .phy_base_addr = 0x0,
5564a935c052SVivien Didelot .global1_addr = 0x1b,
55659069c13aSVivien Didelot .global2_addr = 0x1c,
5566acddbd21SVivien Didelot .age_time_coeff = 15000,
5567dc30c35bSAndrew Lunn .g1_irqs = 8,
5568e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5569b3e05aa1SVivien Didelot .multi_chip = true,
5570b3469dd8SVivien Didelot .ops = &mv88e6095_ops,
5571fad09c73SVivien Didelot },
5572fad09c73SVivien Didelot
55737d381a02SStefan Eichenberger [MV88E6097] = {
5574107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
55757d381a02SStefan Eichenberger .family = MV88E6XXX_FAMILY_6097,
55767d381a02SStefan Eichenberger .name = "Marvell 88E6097/88E6097F",
55777d381a02SStefan Eichenberger .num_databases = 4096,
5578d9ea5620SAndrew Lunn .num_macs = 8192,
55797d381a02SStefan Eichenberger .num_ports = 11,
5580bc393155SAndrew Lunn .num_internal_phys = 8,
55813cf3c846SVivien Didelot .max_vid = 4095,
558249c98c1dSTobias Waldekranz .max_sid = 63,
55837d381a02SStefan Eichenberger .port_base_addr = 0x10,
55849255bacdSAndrew Lunn .phy_base_addr = 0x0,
55857d381a02SStefan Eichenberger .global1_addr = 0x1b,
55869069c13aSVivien Didelot .global2_addr = 0x1c,
55877d381a02SStefan Eichenberger .age_time_coeff = 15000,
5588c534178bSStefan Eichenberger .g1_irqs = 8,
5589d6c5e6afSVivien Didelot .g2_irqs = 10,
5590e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5591f3645652SVivien Didelot .pvt = true,
5592b3e05aa1SVivien Didelot .multi_chip = true,
5593670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
55947d381a02SStefan Eichenberger .ops = &mv88e6097_ops,
55957d381a02SStefan Eichenberger },
55967d381a02SStefan Eichenberger
5597fad09c73SVivien Didelot [MV88E6123] = {
5598107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5599fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6165,
5600fad09c73SVivien Didelot .name = "Marvell 88E6123",
5601fad09c73SVivien Didelot .num_databases = 4096,
5602d9ea5620SAndrew Lunn .num_macs = 1024,
5603fad09c73SVivien Didelot .num_ports = 3,
5604bc393155SAndrew Lunn .num_internal_phys = 5,
56053cf3c846SVivien Didelot .max_vid = 4095,
5606c050f5e9STobias Waldekranz .max_sid = 63,
5607fad09c73SVivien Didelot .port_base_addr = 0x10,
56089255bacdSAndrew Lunn .phy_base_addr = 0x0,
5609a935c052SVivien Didelot .global1_addr = 0x1b,
56109069c13aSVivien Didelot .global2_addr = 0x1c,
5611acddbd21SVivien Didelot .age_time_coeff = 15000,
5612dc30c35bSAndrew Lunn .g1_irqs = 9,
5613d6c5e6afSVivien Didelot .g2_irqs = 10,
5614e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5615f3645652SVivien Didelot .pvt = true,
5616b3e05aa1SVivien Didelot .multi_chip = true,
5617670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5618b3469dd8SVivien Didelot .ops = &mv88e6123_ops,
5619fad09c73SVivien Didelot },
5620fad09c73SVivien Didelot
5621fad09c73SVivien Didelot [MV88E6131] = {
5622107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5623fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6185,
5624fad09c73SVivien Didelot .name = "Marvell 88E6131",
5625fad09c73SVivien Didelot .num_databases = 256,
5626d9ea5620SAndrew Lunn .num_macs = 8192,
5627fad09c73SVivien Didelot .num_ports = 8,
5628bc393155SAndrew Lunn .num_internal_phys = 0,
56293cf3c846SVivien Didelot .max_vid = 4095,
5630fad09c73SVivien Didelot .port_base_addr = 0x10,
56319255bacdSAndrew Lunn .phy_base_addr = 0x0,
5632a935c052SVivien Didelot .global1_addr = 0x1b,
56339069c13aSVivien Didelot .global2_addr = 0x1c,
5634acddbd21SVivien Didelot .age_time_coeff = 15000,
5635dc30c35bSAndrew Lunn .g1_irqs = 9,
5636e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5637b3e05aa1SVivien Didelot .multi_chip = true,
5638b3469dd8SVivien Didelot .ops = &mv88e6131_ops,
5639fad09c73SVivien Didelot },
5640fad09c73SVivien Didelot
5641990e27b0SVivien Didelot [MV88E6141] = {
5642107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5643990e27b0SVivien Didelot .family = MV88E6XXX_FAMILY_6341,
564479a68b26SUwe Kleine-König .name = "Marvell 88E6141",
56456cc5dde9SMarek Behún .num_databases = 256,
5646d9ea5620SAndrew Lunn .num_macs = 2048,
5647990e27b0SVivien Didelot .num_ports = 6,
5648bc393155SAndrew Lunn .num_internal_phys = 5,
5649a73ccd61SBrandon Streiff .num_gpio = 11,
56503cf3c846SVivien Didelot .max_vid = 4095,
5651c050f5e9STobias Waldekranz .max_sid = 63,
5652990e27b0SVivien Didelot .port_base_addr = 0x10,
56539255bacdSAndrew Lunn .phy_base_addr = 0x10,
5654990e27b0SVivien Didelot .global1_addr = 0x1b,
56559069c13aSVivien Didelot .global2_addr = 0x1c,
5656990e27b0SVivien Didelot .age_time_coeff = 3750,
5657990e27b0SVivien Didelot .atu_move_port_mask = 0x1f,
5658adfccf11SAndrew Lunn .g1_irqs = 9,
5659d6c5e6afSVivien Didelot .g2_irqs = 10,
5660f3645652SVivien Didelot .pvt = true,
5661b3e05aa1SVivien Didelot .multi_chip = true,
5662670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5663990e27b0SVivien Didelot .ops = &mv88e6141_ops,
5664990e27b0SVivien Didelot },
5665990e27b0SVivien Didelot
5666fad09c73SVivien Didelot [MV88E6161] = {
5667107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5668fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6165,
5669fad09c73SVivien Didelot .name = "Marvell 88E6161",
5670fad09c73SVivien Didelot .num_databases = 4096,
5671d9ea5620SAndrew Lunn .num_macs = 1024,
5672fad09c73SVivien Didelot .num_ports = 6,
5673bc393155SAndrew Lunn .num_internal_phys = 5,
56743cf3c846SVivien Didelot .max_vid = 4095,
5675c050f5e9STobias Waldekranz .max_sid = 63,
5676fad09c73SVivien Didelot .port_base_addr = 0x10,
56779255bacdSAndrew Lunn .phy_base_addr = 0x0,
5678a935c052SVivien Didelot .global1_addr = 0x1b,
56799069c13aSVivien Didelot .global2_addr = 0x1c,
5680acddbd21SVivien Didelot .age_time_coeff = 15000,
5681dc30c35bSAndrew Lunn .g1_irqs = 9,
5682d6c5e6afSVivien Didelot .g2_irqs = 10,
5683e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5684f3645652SVivien Didelot .pvt = true,
5685b3e05aa1SVivien Didelot .multi_chip = true,
5686670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5687dfa54348SAndrew Lunn .ptp_support = true,
5688b3469dd8SVivien Didelot .ops = &mv88e6161_ops,
5689fad09c73SVivien Didelot },
5690fad09c73SVivien Didelot
5691fad09c73SVivien Didelot [MV88E6165] = {
5692107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5693fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6165,
5694fad09c73SVivien Didelot .name = "Marvell 88E6165",
5695fad09c73SVivien Didelot .num_databases = 4096,
5696d9ea5620SAndrew Lunn .num_macs = 8192,
5697fad09c73SVivien Didelot .num_ports = 6,
5698bc393155SAndrew Lunn .num_internal_phys = 0,
56993cf3c846SVivien Didelot .max_vid = 4095,
5700c050f5e9STobias Waldekranz .max_sid = 63,
5701fad09c73SVivien Didelot .port_base_addr = 0x10,
57029255bacdSAndrew Lunn .phy_base_addr = 0x0,
5703a935c052SVivien Didelot .global1_addr = 0x1b,
57049069c13aSVivien Didelot .global2_addr = 0x1c,
5705acddbd21SVivien Didelot .age_time_coeff = 15000,
5706dc30c35bSAndrew Lunn .g1_irqs = 9,
5707d6c5e6afSVivien Didelot .g2_irqs = 10,
5708e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5709f3645652SVivien Didelot .pvt = true,
5710b3e05aa1SVivien Didelot .multi_chip = true,
5711dfa54348SAndrew Lunn .ptp_support = true,
5712b3469dd8SVivien Didelot .ops = &mv88e6165_ops,
5713fad09c73SVivien Didelot },
5714fad09c73SVivien Didelot
5715fad09c73SVivien Didelot [MV88E6171] = {
5716107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5717fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6351,
5718fad09c73SVivien Didelot .name = "Marvell 88E6171",
5719fad09c73SVivien Didelot .num_databases = 4096,
5720d9ea5620SAndrew Lunn .num_macs = 8192,
5721fad09c73SVivien Didelot .num_ports = 7,
5722bc393155SAndrew Lunn .num_internal_phys = 5,
57233cf3c846SVivien Didelot .max_vid = 4095,
5724c050f5e9STobias Waldekranz .max_sid = 63,
5725fad09c73SVivien Didelot .port_base_addr = 0x10,
57269255bacdSAndrew Lunn .phy_base_addr = 0x0,
5727a935c052SVivien Didelot .global1_addr = 0x1b,
57289069c13aSVivien Didelot .global2_addr = 0x1c,
5729acddbd21SVivien Didelot .age_time_coeff = 15000,
5730dc30c35bSAndrew Lunn .g1_irqs = 9,
5731d6c5e6afSVivien Didelot .g2_irqs = 10,
5732e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5733f3645652SVivien Didelot .pvt = true,
5734b3e05aa1SVivien Didelot .multi_chip = true,
5735670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5736b3469dd8SVivien Didelot .ops = &mv88e6171_ops,
5737fad09c73SVivien Didelot },
5738fad09c73SVivien Didelot
5739fad09c73SVivien Didelot [MV88E6172] = {
5740107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5741fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6352,
5742fad09c73SVivien Didelot .name = "Marvell 88E6172",
5743fad09c73SVivien Didelot .num_databases = 4096,
5744d9ea5620SAndrew Lunn .num_macs = 8192,
5745fad09c73SVivien Didelot .num_ports = 7,
5746bc393155SAndrew Lunn .num_internal_phys = 5,
5747a73ccd61SBrandon Streiff .num_gpio = 15,
57483cf3c846SVivien Didelot .max_vid = 4095,
5749c050f5e9STobias Waldekranz .max_sid = 63,
5750fad09c73SVivien Didelot .port_base_addr = 0x10,
57519255bacdSAndrew Lunn .phy_base_addr = 0x0,
5752a935c052SVivien Didelot .global1_addr = 0x1b,
57539069c13aSVivien Didelot .global2_addr = 0x1c,
5754acddbd21SVivien Didelot .age_time_coeff = 15000,
5755dc30c35bSAndrew Lunn .g1_irqs = 9,
5756d6c5e6afSVivien Didelot .g2_irqs = 10,
5757e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5758f3645652SVivien Didelot .pvt = true,
5759b3e05aa1SVivien Didelot .multi_chip = true,
5760670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5761b3469dd8SVivien Didelot .ops = &mv88e6172_ops,
5762fad09c73SVivien Didelot },
5763fad09c73SVivien Didelot
5764fad09c73SVivien Didelot [MV88E6175] = {
5765107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5766fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6351,
5767fad09c73SVivien Didelot .name = "Marvell 88E6175",
5768fad09c73SVivien Didelot .num_databases = 4096,
5769d9ea5620SAndrew Lunn .num_macs = 8192,
5770fad09c73SVivien Didelot .num_ports = 7,
5771bc393155SAndrew Lunn .num_internal_phys = 5,
57723cf3c846SVivien Didelot .max_vid = 4095,
5773c050f5e9STobias Waldekranz .max_sid = 63,
5774fad09c73SVivien Didelot .port_base_addr = 0x10,
57759255bacdSAndrew Lunn .phy_base_addr = 0x0,
5776a935c052SVivien Didelot .global1_addr = 0x1b,
57779069c13aSVivien Didelot .global2_addr = 0x1c,
5778acddbd21SVivien Didelot .age_time_coeff = 15000,
5779dc30c35bSAndrew Lunn .g1_irqs = 9,
5780d6c5e6afSVivien Didelot .g2_irqs = 10,
5781e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5782f3645652SVivien Didelot .pvt = true,
5783b3e05aa1SVivien Didelot .multi_chip = true,
5784670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5785b3469dd8SVivien Didelot .ops = &mv88e6175_ops,
5786fad09c73SVivien Didelot },
5787fad09c73SVivien Didelot
5788fad09c73SVivien Didelot [MV88E6176] = {
5789107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5790fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6352,
5791fad09c73SVivien Didelot .name = "Marvell 88E6176",
5792fad09c73SVivien Didelot .num_databases = 4096,
5793d9ea5620SAndrew Lunn .num_macs = 8192,
5794fad09c73SVivien Didelot .num_ports = 7,
5795bc393155SAndrew Lunn .num_internal_phys = 5,
5796a73ccd61SBrandon Streiff .num_gpio = 15,
57973cf3c846SVivien Didelot .max_vid = 4095,
5798c050f5e9STobias Waldekranz .max_sid = 63,
5799fad09c73SVivien Didelot .port_base_addr = 0x10,
58009255bacdSAndrew Lunn .phy_base_addr = 0x0,
5801a935c052SVivien Didelot .global1_addr = 0x1b,
58029069c13aSVivien Didelot .global2_addr = 0x1c,
5803acddbd21SVivien Didelot .age_time_coeff = 15000,
5804dc30c35bSAndrew Lunn .g1_irqs = 9,
5805d6c5e6afSVivien Didelot .g2_irqs = 10,
5806e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5807f3645652SVivien Didelot .pvt = true,
5808b3e05aa1SVivien Didelot .multi_chip = true,
5809670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5810b3469dd8SVivien Didelot .ops = &mv88e6176_ops,
5811fad09c73SVivien Didelot },
5812fad09c73SVivien Didelot
5813fad09c73SVivien Didelot [MV88E6185] = {
5814107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5815fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6185,
5816fad09c73SVivien Didelot .name = "Marvell 88E6185",
5817fad09c73SVivien Didelot .num_databases = 256,
5818d9ea5620SAndrew Lunn .num_macs = 8192,
5819fad09c73SVivien Didelot .num_ports = 10,
5820bc393155SAndrew Lunn .num_internal_phys = 0,
58213cf3c846SVivien Didelot .max_vid = 4095,
5822fad09c73SVivien Didelot .port_base_addr = 0x10,
58239255bacdSAndrew Lunn .phy_base_addr = 0x0,
5824a935c052SVivien Didelot .global1_addr = 0x1b,
58259069c13aSVivien Didelot .global2_addr = 0x1c,
5826acddbd21SVivien Didelot .age_time_coeff = 15000,
5827dc30c35bSAndrew Lunn .g1_irqs = 8,
5828e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5829b3e05aa1SVivien Didelot .multi_chip = true,
5830670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5831b3469dd8SVivien Didelot .ops = &mv88e6185_ops,
5832fad09c73SVivien Didelot },
5833fad09c73SVivien Didelot
58341a3b39ecSAndrew Lunn [MV88E6190] = {
5835107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
58361a3b39ecSAndrew Lunn .family = MV88E6XXX_FAMILY_6390,
58371a3b39ecSAndrew Lunn .name = "Marvell 88E6190",
58381a3b39ecSAndrew Lunn .num_databases = 4096,
5839d9ea5620SAndrew Lunn .num_macs = 16384,
58401a3b39ecSAndrew Lunn .num_ports = 11, /* 10 + Z80 */
584195150f29SHeiner Kallweit .num_internal_phys = 9,
5842a73ccd61SBrandon Streiff .num_gpio = 16,
5843931d1822SVivien Didelot .max_vid = 8191,
584449c98c1dSTobias Waldekranz .max_sid = 63,
58451a3b39ecSAndrew Lunn .port_base_addr = 0x0,
58469255bacdSAndrew Lunn .phy_base_addr = 0x0,
58471a3b39ecSAndrew Lunn .global1_addr = 0x1b,
58489069c13aSVivien Didelot .global2_addr = 0x1c,
5849b91e055cSAndrew Lunn .age_time_coeff = 3750,
58501a3b39ecSAndrew Lunn .g1_irqs = 9,
5851d6c5e6afSVivien Didelot .g2_irqs = 14,
5852f3645652SVivien Didelot .pvt = true,
5853b3e05aa1SVivien Didelot .multi_chip = true,
5854e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
58551a3b39ecSAndrew Lunn .ops = &mv88e6190_ops,
58561a3b39ecSAndrew Lunn },
58571a3b39ecSAndrew Lunn
58581a3b39ecSAndrew Lunn [MV88E6190X] = {
5859107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
58601a3b39ecSAndrew Lunn .family = MV88E6XXX_FAMILY_6390,
58611a3b39ecSAndrew Lunn .name = "Marvell 88E6190X",
58621a3b39ecSAndrew Lunn .num_databases = 4096,
5863d9ea5620SAndrew Lunn .num_macs = 16384,
58641a3b39ecSAndrew Lunn .num_ports = 11, /* 10 + Z80 */
586595150f29SHeiner Kallweit .num_internal_phys = 9,
5866a73ccd61SBrandon Streiff .num_gpio = 16,
5867931d1822SVivien Didelot .max_vid = 8191,
586849c98c1dSTobias Waldekranz .max_sid = 63,
58691a3b39ecSAndrew Lunn .port_base_addr = 0x0,
58709255bacdSAndrew Lunn .phy_base_addr = 0x0,
58711a3b39ecSAndrew Lunn .global1_addr = 0x1b,
58729069c13aSVivien Didelot .global2_addr = 0x1c,
5873b91e055cSAndrew Lunn .age_time_coeff = 3750,
58741a3b39ecSAndrew Lunn .g1_irqs = 9,
5875d6c5e6afSVivien Didelot .g2_irqs = 14,
5876e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
5877f3645652SVivien Didelot .pvt = true,
5878b3e05aa1SVivien Didelot .multi_chip = true,
58791a3b39ecSAndrew Lunn .ops = &mv88e6190x_ops,
58801a3b39ecSAndrew Lunn },
58811a3b39ecSAndrew Lunn
58821a3b39ecSAndrew Lunn [MV88E6191] = {
5883107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
58841a3b39ecSAndrew Lunn .family = MV88E6XXX_FAMILY_6390,
58851a3b39ecSAndrew Lunn .name = "Marvell 88E6191",
58861a3b39ecSAndrew Lunn .num_databases = 4096,
5887d9ea5620SAndrew Lunn .num_macs = 16384,
58881a3b39ecSAndrew Lunn .num_ports = 11, /* 10 + Z80 */
588995150f29SHeiner Kallweit .num_internal_phys = 9,
5890931d1822SVivien Didelot .max_vid = 8191,
589149c98c1dSTobias Waldekranz .max_sid = 63,
58921a3b39ecSAndrew Lunn .port_base_addr = 0x0,
58939255bacdSAndrew Lunn .phy_base_addr = 0x0,
58941a3b39ecSAndrew Lunn .global1_addr = 0x1b,
58959069c13aSVivien Didelot .global2_addr = 0x1c,
5896b91e055cSAndrew Lunn .age_time_coeff = 3750,
5897443d5a1bSAndrew Lunn .g1_irqs = 9,
5898d6c5e6afSVivien Didelot .g2_irqs = 14,
5899e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
5900f3645652SVivien Didelot .pvt = true,
5901b3e05aa1SVivien Didelot .multi_chip = true,
59022fa8d3afSBrandon Streiff .ptp_support = true,
59032cf4cefbSVivien Didelot .ops = &mv88e6191_ops,
59041a3b39ecSAndrew Lunn },
59051a3b39ecSAndrew Lunn
5906de776d0dSPavana Sharma [MV88E6191X] = {
5907de776d0dSPavana Sharma .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5908de776d0dSPavana Sharma .family = MV88E6XXX_FAMILY_6393,
5909de776d0dSPavana Sharma .name = "Marvell 88E6191X",
5910de776d0dSPavana Sharma .num_databases = 4096,
5911de776d0dSPavana Sharma .num_ports = 11, /* 10 + Z80 */
59122f934939SAlexis Lothoré .num_internal_phys = 8,
59132f934939SAlexis Lothoré .internal_phys_offset = 1,
5914de776d0dSPavana Sharma .max_vid = 8191,
591549c98c1dSTobias Waldekranz .max_sid = 63,
5916de776d0dSPavana Sharma .port_base_addr = 0x0,
5917de776d0dSPavana Sharma .phy_base_addr = 0x0,
5918de776d0dSPavana Sharma .global1_addr = 0x1b,
5919de776d0dSPavana Sharma .global2_addr = 0x1c,
5920de776d0dSPavana Sharma .age_time_coeff = 3750,
5921de776d0dSPavana Sharma .g1_irqs = 10,
5922de776d0dSPavana Sharma .g2_irqs = 14,
5923de776d0dSPavana Sharma .atu_move_port_mask = 0x1f,
5924de776d0dSPavana Sharma .pvt = true,
5925de776d0dSPavana Sharma .multi_chip = true,
5926de776d0dSPavana Sharma .ptp_support = true,
5927de776d0dSPavana Sharma .ops = &mv88e6393x_ops,
5928de776d0dSPavana Sharma },
5929de776d0dSPavana Sharma
5930de776d0dSPavana Sharma [MV88E6193X] = {
5931de776d0dSPavana Sharma .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5932de776d0dSPavana Sharma .family = MV88E6XXX_FAMILY_6393,
5933de776d0dSPavana Sharma .name = "Marvell 88E6193X",
5934de776d0dSPavana Sharma .num_databases = 4096,
5935de776d0dSPavana Sharma .num_ports = 11, /* 10 + Z80 */
59362f934939SAlexis Lothoré .num_internal_phys = 8,
59372f934939SAlexis Lothoré .internal_phys_offset = 1,
5938de776d0dSPavana Sharma .max_vid = 8191,
593949c98c1dSTobias Waldekranz .max_sid = 63,
5940de776d0dSPavana Sharma .port_base_addr = 0x0,
5941de776d0dSPavana Sharma .phy_base_addr = 0x0,
5942de776d0dSPavana Sharma .global1_addr = 0x1b,
5943de776d0dSPavana Sharma .global2_addr = 0x1c,
5944de776d0dSPavana Sharma .age_time_coeff = 3750,
5945de776d0dSPavana Sharma .g1_irqs = 10,
5946de776d0dSPavana Sharma .g2_irqs = 14,
5947de776d0dSPavana Sharma .atu_move_port_mask = 0x1f,
5948de776d0dSPavana Sharma .pvt = true,
5949de776d0dSPavana Sharma .multi_chip = true,
5950de776d0dSPavana Sharma .ptp_support = true,
5951de776d0dSPavana Sharma .ops = &mv88e6393x_ops,
5952de776d0dSPavana Sharma },
5953de776d0dSPavana Sharma
595449022647SHubert Feurstein [MV88E6220] = {
595549022647SHubert Feurstein .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
595649022647SHubert Feurstein .family = MV88E6XXX_FAMILY_6250,
595749022647SHubert Feurstein .name = "Marvell 88E6220",
595849022647SHubert Feurstein .num_databases = 64,
595949022647SHubert Feurstein
596049022647SHubert Feurstein /* Ports 2-4 are not routed to pins
596149022647SHubert Feurstein * => usable ports 0, 1, 5, 6
596249022647SHubert Feurstein */
596349022647SHubert Feurstein .num_ports = 7,
596449022647SHubert Feurstein .num_internal_phys = 2,
5965c857486aSHubert Feurstein .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
596649022647SHubert Feurstein .max_vid = 4095,
596749022647SHubert Feurstein .port_base_addr = 0x08,
596849022647SHubert Feurstein .phy_base_addr = 0x00,
596949022647SHubert Feurstein .global1_addr = 0x0f,
597049022647SHubert Feurstein .global2_addr = 0x07,
597149022647SHubert Feurstein .age_time_coeff = 15000,
597249022647SHubert Feurstein .g1_irqs = 9,
597349022647SHubert Feurstein .g2_irqs = 10,
597449022647SHubert Feurstein .atu_move_port_mask = 0xf,
597549022647SHubert Feurstein .dual_chip = true,
597671509614SHubert Feurstein .ptp_support = true,
597749022647SHubert Feurstein .ops = &mv88e6250_ops,
597849022647SHubert Feurstein },
597949022647SHubert Feurstein
5980fad09c73SVivien Didelot [MV88E6240] = {
5981107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5982fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6352,
5983fad09c73SVivien Didelot .name = "Marvell 88E6240",
5984fad09c73SVivien Didelot .num_databases = 4096,
5985d9ea5620SAndrew Lunn .num_macs = 8192,
5986fad09c73SVivien Didelot .num_ports = 7,
5987bc393155SAndrew Lunn .num_internal_phys = 5,
5988a73ccd61SBrandon Streiff .num_gpio = 15,
59893cf3c846SVivien Didelot .max_vid = 4095,
5990c050f5e9STobias Waldekranz .max_sid = 63,
5991fad09c73SVivien Didelot .port_base_addr = 0x10,
59929255bacdSAndrew Lunn .phy_base_addr = 0x0,
5993a935c052SVivien Didelot .global1_addr = 0x1b,
59949069c13aSVivien Didelot .global2_addr = 0x1c,
5995acddbd21SVivien Didelot .age_time_coeff = 15000,
5996dc30c35bSAndrew Lunn .g1_irqs = 9,
5997d6c5e6afSVivien Didelot .g2_irqs = 10,
5998e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
5999f3645652SVivien Didelot .pvt = true,
6000b3e05aa1SVivien Didelot .multi_chip = true,
6001670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
60022fa8d3afSBrandon Streiff .ptp_support = true,
6003b3469dd8SVivien Didelot .ops = &mv88e6240_ops,
6004fad09c73SVivien Didelot },
6005fad09c73SVivien Didelot
60061f71836fSRasmus Villemoes [MV88E6250] = {
60071f71836fSRasmus Villemoes .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
60081f71836fSRasmus Villemoes .family = MV88E6XXX_FAMILY_6250,
60091f71836fSRasmus Villemoes .name = "Marvell 88E6250",
60101f71836fSRasmus Villemoes .num_databases = 64,
60111f71836fSRasmus Villemoes .num_ports = 7,
60121f71836fSRasmus Villemoes .num_internal_phys = 5,
60131f71836fSRasmus Villemoes .max_vid = 4095,
60141f71836fSRasmus Villemoes .port_base_addr = 0x08,
60151f71836fSRasmus Villemoes .phy_base_addr = 0x00,
60161f71836fSRasmus Villemoes .global1_addr = 0x0f,
60171f71836fSRasmus Villemoes .global2_addr = 0x07,
60181f71836fSRasmus Villemoes .age_time_coeff = 15000,
60191f71836fSRasmus Villemoes .g1_irqs = 9,
60201f71836fSRasmus Villemoes .g2_irqs = 10,
60211f71836fSRasmus Villemoes .atu_move_port_mask = 0xf,
60221f71836fSRasmus Villemoes .dual_chip = true,
602371509614SHubert Feurstein .ptp_support = true,
60241f71836fSRasmus Villemoes .ops = &mv88e6250_ops,
60251f71836fSRasmus Villemoes },
60261f71836fSRasmus Villemoes
60271a3b39ecSAndrew Lunn [MV88E6290] = {
6028107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
60291a3b39ecSAndrew Lunn .family = MV88E6XXX_FAMILY_6390,
60301a3b39ecSAndrew Lunn .name = "Marvell 88E6290",
60311a3b39ecSAndrew Lunn .num_databases = 4096,
60321a3b39ecSAndrew Lunn .num_ports = 11, /* 10 + Z80 */
603395150f29SHeiner Kallweit .num_internal_phys = 9,
6034a73ccd61SBrandon Streiff .num_gpio = 16,
6035931d1822SVivien Didelot .max_vid = 8191,
6036c050f5e9STobias Waldekranz .max_sid = 63,
60371a3b39ecSAndrew Lunn .port_base_addr = 0x0,
60389255bacdSAndrew Lunn .phy_base_addr = 0x0,
60391a3b39ecSAndrew Lunn .global1_addr = 0x1b,
60409069c13aSVivien Didelot .global2_addr = 0x1c,
6041b91e055cSAndrew Lunn .age_time_coeff = 3750,
60421a3b39ecSAndrew Lunn .g1_irqs = 9,
6043d6c5e6afSVivien Didelot .g2_irqs = 14,
6044e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
6045f3645652SVivien Didelot .pvt = true,
6046b3e05aa1SVivien Didelot .multi_chip = true,
60472fa8d3afSBrandon Streiff .ptp_support = true,
60481a3b39ecSAndrew Lunn .ops = &mv88e6290_ops,
60491a3b39ecSAndrew Lunn },
60501a3b39ecSAndrew Lunn
6051fad09c73SVivien Didelot [MV88E6320] = {
6052107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6053fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6320,
6054fad09c73SVivien Didelot .name = "Marvell 88E6320",
6055fad09c73SVivien Didelot .num_databases = 4096,
6056d9ea5620SAndrew Lunn .num_macs = 8192,
6057fad09c73SVivien Didelot .num_ports = 7,
6058bc393155SAndrew Lunn .num_internal_phys = 5,
6059a73ccd61SBrandon Streiff .num_gpio = 15,
60603cf3c846SVivien Didelot .max_vid = 4095,
6061fad09c73SVivien Didelot .port_base_addr = 0x10,
60629255bacdSAndrew Lunn .phy_base_addr = 0x0,
6063a935c052SVivien Didelot .global1_addr = 0x1b,
60649069c13aSVivien Didelot .global2_addr = 0x1c,
6065acddbd21SVivien Didelot .age_time_coeff = 15000,
6066dc30c35bSAndrew Lunn .g1_irqs = 8,
6067bc393155SAndrew Lunn .g2_irqs = 10,
6068e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
6069f3645652SVivien Didelot .pvt = true,
6070b3e05aa1SVivien Didelot .multi_chip = true,
6071670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
60722fa8d3afSBrandon Streiff .ptp_support = true,
6073b3469dd8SVivien Didelot .ops = &mv88e6320_ops,
6074fad09c73SVivien Didelot },
6075fad09c73SVivien Didelot
6076fad09c73SVivien Didelot [MV88E6321] = {
6077107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6078fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6320,
6079fad09c73SVivien Didelot .name = "Marvell 88E6321",
6080fad09c73SVivien Didelot .num_databases = 4096,
6081d9ea5620SAndrew Lunn .num_macs = 8192,
6082fad09c73SVivien Didelot .num_ports = 7,
6083bc393155SAndrew Lunn .num_internal_phys = 5,
6084a73ccd61SBrandon Streiff .num_gpio = 15,
60853cf3c846SVivien Didelot .max_vid = 4095,
6086fad09c73SVivien Didelot .port_base_addr = 0x10,
60879255bacdSAndrew Lunn .phy_base_addr = 0x0,
6088a935c052SVivien Didelot .global1_addr = 0x1b,
60899069c13aSVivien Didelot .global2_addr = 0x1c,
6090acddbd21SVivien Didelot .age_time_coeff = 15000,
6091dc30c35bSAndrew Lunn .g1_irqs = 8,
6092bc393155SAndrew Lunn .g2_irqs = 10,
6093e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
6094b3e05aa1SVivien Didelot .multi_chip = true,
6095670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
60962fa8d3afSBrandon Streiff .ptp_support = true,
6097b3469dd8SVivien Didelot .ops = &mv88e6321_ops,
6098fad09c73SVivien Didelot },
6099fad09c73SVivien Didelot
6100a75961d0SGregory CLEMENT [MV88E6341] = {
6101107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6102a75961d0SGregory CLEMENT .family = MV88E6XXX_FAMILY_6341,
6103a75961d0SGregory CLEMENT .name = "Marvell 88E6341",
61046cc5dde9SMarek Behún .num_databases = 256,
6105d9ea5620SAndrew Lunn .num_macs = 2048,
6106bc393155SAndrew Lunn .num_internal_phys = 5,
6107a75961d0SGregory CLEMENT .num_ports = 6,
6108a73ccd61SBrandon Streiff .num_gpio = 11,
61093cf3c846SVivien Didelot .max_vid = 4095,
6110c050f5e9STobias Waldekranz .max_sid = 63,
6111a75961d0SGregory CLEMENT .port_base_addr = 0x10,
61129255bacdSAndrew Lunn .phy_base_addr = 0x10,
6113a75961d0SGregory CLEMENT .global1_addr = 0x1b,
61149069c13aSVivien Didelot .global2_addr = 0x1c,
6115a75961d0SGregory CLEMENT .age_time_coeff = 3750,
6116e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
6117adfccf11SAndrew Lunn .g1_irqs = 9,
6118d6c5e6afSVivien Didelot .g2_irqs = 10,
6119f3645652SVivien Didelot .pvt = true,
6120b3e05aa1SVivien Didelot .multi_chip = true,
6121670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
61222fa8d3afSBrandon Streiff .ptp_support = true,
6123a75961d0SGregory CLEMENT .ops = &mv88e6341_ops,
6124a75961d0SGregory CLEMENT },
6125a75961d0SGregory CLEMENT
6126fad09c73SVivien Didelot [MV88E6350] = {
6127107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6128fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6351,
6129fad09c73SVivien Didelot .name = "Marvell 88E6350",
6130fad09c73SVivien Didelot .num_databases = 4096,
6131d9ea5620SAndrew Lunn .num_macs = 8192,
6132fad09c73SVivien Didelot .num_ports = 7,
6133bc393155SAndrew Lunn .num_internal_phys = 5,
61343cf3c846SVivien Didelot .max_vid = 4095,
6135c050f5e9STobias Waldekranz .max_sid = 63,
6136fad09c73SVivien Didelot .port_base_addr = 0x10,
61379255bacdSAndrew Lunn .phy_base_addr = 0x0,
6138a935c052SVivien Didelot .global1_addr = 0x1b,
61399069c13aSVivien Didelot .global2_addr = 0x1c,
6140acddbd21SVivien Didelot .age_time_coeff = 15000,
6141dc30c35bSAndrew Lunn .g1_irqs = 9,
6142d6c5e6afSVivien Didelot .g2_irqs = 10,
6143e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
6144f3645652SVivien Didelot .pvt = true,
6145b3e05aa1SVivien Didelot .multi_chip = true,
6146670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6147b3469dd8SVivien Didelot .ops = &mv88e6350_ops,
6148fad09c73SVivien Didelot },
6149fad09c73SVivien Didelot
6150fad09c73SVivien Didelot [MV88E6351] = {
6151107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6152fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6351,
6153fad09c73SVivien Didelot .name = "Marvell 88E6351",
6154fad09c73SVivien Didelot .num_databases = 4096,
6155d9ea5620SAndrew Lunn .num_macs = 8192,
6156fad09c73SVivien Didelot .num_ports = 7,
6157bc393155SAndrew Lunn .num_internal_phys = 5,
61583cf3c846SVivien Didelot .max_vid = 4095,
6159c050f5e9STobias Waldekranz .max_sid = 63,
6160fad09c73SVivien Didelot .port_base_addr = 0x10,
61619255bacdSAndrew Lunn .phy_base_addr = 0x0,
6162a935c052SVivien Didelot .global1_addr = 0x1b,
61639069c13aSVivien Didelot .global2_addr = 0x1c,
6164acddbd21SVivien Didelot .age_time_coeff = 15000,
6165dc30c35bSAndrew Lunn .g1_irqs = 9,
6166d6c5e6afSVivien Didelot .g2_irqs = 10,
6167e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
6168f3645652SVivien Didelot .pvt = true,
6169b3e05aa1SVivien Didelot .multi_chip = true,
6170670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6171b3469dd8SVivien Didelot .ops = &mv88e6351_ops,
6172fad09c73SVivien Didelot },
6173fad09c73SVivien Didelot
6174fad09c73SVivien Didelot [MV88E6352] = {
6175107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6176fad09c73SVivien Didelot .family = MV88E6XXX_FAMILY_6352,
6177fad09c73SVivien Didelot .name = "Marvell 88E6352",
6178fad09c73SVivien Didelot .num_databases = 4096,
6179d9ea5620SAndrew Lunn .num_macs = 8192,
6180fad09c73SVivien Didelot .num_ports = 7,
6181bc393155SAndrew Lunn .num_internal_phys = 5,
6182a73ccd61SBrandon Streiff .num_gpio = 15,
61833cf3c846SVivien Didelot .max_vid = 4095,
618449c98c1dSTobias Waldekranz .max_sid = 63,
6185fad09c73SVivien Didelot .port_base_addr = 0x10,
61869255bacdSAndrew Lunn .phy_base_addr = 0x0,
6187a935c052SVivien Didelot .global1_addr = 0x1b,
61889069c13aSVivien Didelot .global2_addr = 0x1c,
6189acddbd21SVivien Didelot .age_time_coeff = 15000,
6190dc30c35bSAndrew Lunn .g1_irqs = 9,
6191d6c5e6afSVivien Didelot .g2_irqs = 10,
6192e606ca36SVivien Didelot .atu_move_port_mask = 0xf,
6193f3645652SVivien Didelot .pvt = true,
6194b3e05aa1SVivien Didelot .multi_chip = true,
6195670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
61962fa8d3afSBrandon Streiff .ptp_support = true,
6197b3469dd8SVivien Didelot .ops = &mv88e6352_ops,
6198fad09c73SVivien Didelot },
619912899f29SAlexis Lothoré [MV88E6361] = {
620012899f29SAlexis Lothoré .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
620112899f29SAlexis Lothoré .family = MV88E6XXX_FAMILY_6393,
620212899f29SAlexis Lothoré .name = "Marvell 88E6361",
620312899f29SAlexis Lothoré .num_databases = 4096,
620412899f29SAlexis Lothoré .num_macs = 16384,
620512899f29SAlexis Lothoré .num_ports = 11,
620612899f29SAlexis Lothoré /* Ports 1, 2 and 8 are not routed */
620712899f29SAlexis Lothoré .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
620812899f29SAlexis Lothoré .num_internal_phys = 5,
620912899f29SAlexis Lothoré .internal_phys_offset = 3,
621012899f29SAlexis Lothoré .max_vid = 4095,
621112899f29SAlexis Lothoré .max_sid = 63,
621212899f29SAlexis Lothoré .port_base_addr = 0x0,
621312899f29SAlexis Lothoré .phy_base_addr = 0x0,
621412899f29SAlexis Lothoré .global1_addr = 0x1b,
621512899f29SAlexis Lothoré .global2_addr = 0x1c,
621612899f29SAlexis Lothoré .age_time_coeff = 3750,
621712899f29SAlexis Lothoré .g1_irqs = 10,
621812899f29SAlexis Lothoré .g2_irqs = 14,
621912899f29SAlexis Lothoré .atu_move_port_mask = 0x1f,
622012899f29SAlexis Lothoré .pvt = true,
622112899f29SAlexis Lothoré .multi_chip = true,
622212899f29SAlexis Lothoré .ptp_support = true,
622312899f29SAlexis Lothoré .ops = &mv88e6393x_ops,
622412899f29SAlexis Lothoré },
62251a3b39ecSAndrew Lunn [MV88E6390] = {
6226107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
62271a3b39ecSAndrew Lunn .family = MV88E6XXX_FAMILY_6390,
62281a3b39ecSAndrew Lunn .name = "Marvell 88E6390",
62291a3b39ecSAndrew Lunn .num_databases = 4096,
6230d9ea5620SAndrew Lunn .num_macs = 16384,
62311a3b39ecSAndrew Lunn .num_ports = 11, /* 10 + Z80 */
623295150f29SHeiner Kallweit .num_internal_phys = 9,
6233a73ccd61SBrandon Streiff .num_gpio = 16,
6234931d1822SVivien Didelot .max_vid = 8191,
623549c98c1dSTobias Waldekranz .max_sid = 63,
62361a3b39ecSAndrew Lunn .port_base_addr = 0x0,
62379255bacdSAndrew Lunn .phy_base_addr = 0x0,
62381a3b39ecSAndrew Lunn .global1_addr = 0x1b,
62399069c13aSVivien Didelot .global2_addr = 0x1c,
6240b91e055cSAndrew Lunn .age_time_coeff = 3750,
62411a3b39ecSAndrew Lunn .g1_irqs = 9,
6242d6c5e6afSVivien Didelot .g2_irqs = 14,
6243e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
6244f3645652SVivien Didelot .pvt = true,
6245b3e05aa1SVivien Didelot .multi_chip = true,
6246670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
62472fa8d3afSBrandon Streiff .ptp_support = true,
62481a3b39ecSAndrew Lunn .ops = &mv88e6390_ops,
62491a3b39ecSAndrew Lunn },
62501a3b39ecSAndrew Lunn [MV88E6390X] = {
6251107fcc10SVivien Didelot .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
62521a3b39ecSAndrew Lunn .family = MV88E6XXX_FAMILY_6390,
62531a3b39ecSAndrew Lunn .name = "Marvell 88E6390X",
62541a3b39ecSAndrew Lunn .num_databases = 4096,
6255d9ea5620SAndrew Lunn .num_macs = 16384,
62561a3b39ecSAndrew Lunn .num_ports = 11, /* 10 + Z80 */
625795150f29SHeiner Kallweit .num_internal_phys = 9,
6258a73ccd61SBrandon Streiff .num_gpio = 16,
6259931d1822SVivien Didelot .max_vid = 8191,
626049c98c1dSTobias Waldekranz .max_sid = 63,
62611a3b39ecSAndrew Lunn .port_base_addr = 0x0,
62629255bacdSAndrew Lunn .phy_base_addr = 0x0,
62631a3b39ecSAndrew Lunn .global1_addr = 0x1b,
62649069c13aSVivien Didelot .global2_addr = 0x1c,
6265b91e055cSAndrew Lunn .age_time_coeff = 3750,
62661a3b39ecSAndrew Lunn .g1_irqs = 9,
6267d6c5e6afSVivien Didelot .g2_irqs = 14,
6268e606ca36SVivien Didelot .atu_move_port_mask = 0x1f,
6269f3645652SVivien Didelot .pvt = true,
6270b3e05aa1SVivien Didelot .multi_chip = true,
6271670bb80fSTobias Waldekranz .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
62722fa8d3afSBrandon Streiff .ptp_support = true,
62731a3b39ecSAndrew Lunn .ops = &mv88e6390x_ops,
62741a3b39ecSAndrew Lunn },
6275de776d0dSPavana Sharma
6276de776d0dSPavana Sharma [MV88E6393X] = {
6277de776d0dSPavana Sharma .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6278de776d0dSPavana Sharma .family = MV88E6XXX_FAMILY_6393,
6279de776d0dSPavana Sharma .name = "Marvell 88E6393X",
6280de776d0dSPavana Sharma .num_databases = 4096,
6281de776d0dSPavana Sharma .num_ports = 11, /* 10 + Z80 */
62822f934939SAlexis Lothoré .num_internal_phys = 8,
62832f934939SAlexis Lothoré .internal_phys_offset = 1,
6284de776d0dSPavana Sharma .max_vid = 8191,
628549c98c1dSTobias Waldekranz .max_sid = 63,
6286de776d0dSPavana Sharma .port_base_addr = 0x0,
6287de776d0dSPavana Sharma .phy_base_addr = 0x0,
6288de776d0dSPavana Sharma .global1_addr = 0x1b,
6289de776d0dSPavana Sharma .global2_addr = 0x1c,
6290de776d0dSPavana Sharma .age_time_coeff = 3750,
6291de776d0dSPavana Sharma .g1_irqs = 10,
6292de776d0dSPavana Sharma .g2_irqs = 14,
6293de776d0dSPavana Sharma .atu_move_port_mask = 0x1f,
6294de776d0dSPavana Sharma .pvt = true,
6295de776d0dSPavana Sharma .multi_chip = true,
6296de776d0dSPavana Sharma .ptp_support = true,
6297de776d0dSPavana Sharma .ops = &mv88e6393x_ops,
6298de776d0dSPavana Sharma },
6299fad09c73SVivien Didelot };
6300fad09c73SVivien Didelot
mv88e6xxx_lookup_info(unsigned int prod_num)6301fad09c73SVivien Didelot static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6302fad09c73SVivien Didelot {
6303fad09c73SVivien Didelot int i;
6304fad09c73SVivien Didelot
6305fad09c73SVivien Didelot for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6306fad09c73SVivien Didelot if (mv88e6xxx_table[i].prod_num == prod_num)
6307fad09c73SVivien Didelot return &mv88e6xxx_table[i];
6308fad09c73SVivien Didelot
6309fad09c73SVivien Didelot return NULL;
6310fad09c73SVivien Didelot }
6311fad09c73SVivien Didelot
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)6312fad09c73SVivien Didelot static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6313fad09c73SVivien Didelot {
6314fad09c73SVivien Didelot const struct mv88e6xxx_info *info;
63158f6345b2SVivien Didelot unsigned int prod_num, rev;
63168f6345b2SVivien Didelot u16 id;
63178f6345b2SVivien Didelot int err;
6318fad09c73SVivien Didelot
6319c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
6320107fcc10SVivien Didelot err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6321c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
63228f6345b2SVivien Didelot if (err)
63238f6345b2SVivien Didelot return err;
6324fad09c73SVivien Didelot
6325107fcc10SVivien Didelot prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6326107fcc10SVivien Didelot rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6327fad09c73SVivien Didelot
6328fad09c73SVivien Didelot info = mv88e6xxx_lookup_info(prod_num);
6329fad09c73SVivien Didelot if (!info)
6330fad09c73SVivien Didelot return -ENODEV;
6331fad09c73SVivien Didelot
6332fad09c73SVivien Didelot /* Update the compatible info with the probed one */
6333fad09c73SVivien Didelot chip->info = info;
6334fad09c73SVivien Didelot
6335fad09c73SVivien Didelot dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6336fad09c73SVivien Didelot chip->info->prod_num, chip->info->name, rev);
6337fad09c73SVivien Didelot
6338fad09c73SVivien Didelot return 0;
6339fad09c73SVivien Didelot }
6340fad09c73SVivien Didelot
mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip * chip,struct mdio_device * mdiodev)63415da66099SNathan Rossi static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
63425da66099SNathan Rossi struct mdio_device *mdiodev)
63435da66099SNathan Rossi {
63445da66099SNathan Rossi int err;
63455da66099SNathan Rossi
63465da66099SNathan Rossi /* dual_chip takes precedence over single/multi-chip modes */
63475da66099SNathan Rossi if (chip->info->dual_chip)
63485da66099SNathan Rossi return -EINVAL;
63495da66099SNathan Rossi
63505da66099SNathan Rossi /* If the mdio addr is 16 indicating the first port address of a switch
63515da66099SNathan Rossi * (e.g. mv88e6*41) in single chip addressing mode the device may be
63525da66099SNathan Rossi * configured in single chip addressing mode. Setup the smi access as
63535da66099SNathan Rossi * single chip addressing mode and attempt to detect the model of the
63545da66099SNathan Rossi * switch, if this fails the device is not configured in single chip
63555da66099SNathan Rossi * addressing mode.
63565da66099SNathan Rossi */
63575da66099SNathan Rossi if (mdiodev->addr != 16)
63585da66099SNathan Rossi return -EINVAL;
63595da66099SNathan Rossi
63605da66099SNathan Rossi err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
63615da66099SNathan Rossi if (err)
63625da66099SNathan Rossi return err;
63635da66099SNathan Rossi
63645da66099SNathan Rossi return mv88e6xxx_detect(chip);
63655da66099SNathan Rossi }
63665da66099SNathan Rossi
mv88e6xxx_alloc_chip(struct device * dev)6367fad09c73SVivien Didelot static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6368fad09c73SVivien Didelot {
6369fad09c73SVivien Didelot struct mv88e6xxx_chip *chip;
6370fad09c73SVivien Didelot
6371fad09c73SVivien Didelot chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6372fad09c73SVivien Didelot if (!chip)
6373fad09c73SVivien Didelot return NULL;
6374fad09c73SVivien Didelot
6375fad09c73SVivien Didelot chip->dev = dev;
6376fad09c73SVivien Didelot
6377fad09c73SVivien Didelot mutex_init(&chip->reg_lock);
6378a3c53be5SAndrew Lunn INIT_LIST_HEAD(&chip->mdios);
6379da7dc875SVivien Didelot idr_init(&chip->policies);
6380acaf4d2eSTobias Waldekranz INIT_LIST_HEAD(&chip->msts);
6381fad09c73SVivien Didelot
6382fad09c73SVivien Didelot return chip;
6383fad09c73SVivien Didelot }
6384fad09c73SVivien Didelot
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)63855ed4e3ebSFlorian Fainelli static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
63864d776482SFlorian Fainelli int port,
63874d776482SFlorian Fainelli enum dsa_tag_protocol m)
63887b314362SAndrew Lunn {
638904bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
63902bbb33beSAndrew Lunn
6391670bb80fSTobias Waldekranz return chip->tag_protocol;
63927b314362SAndrew Lunn }
63937b314362SAndrew Lunn
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)6394bacf93b0SVladimir Oltean static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
63959a99bef5STobias Waldekranz enum dsa_tag_protocol proto)
63969a99bef5STobias Waldekranz {
63979a99bef5STobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
63989a99bef5STobias Waldekranz enum dsa_tag_protocol old_protocol;
6399bacf93b0SVladimir Oltean struct dsa_port *cpu_dp;
64009a99bef5STobias Waldekranz int err;
64019a99bef5STobias Waldekranz
64029a99bef5STobias Waldekranz switch (proto) {
64039a99bef5STobias Waldekranz case DSA_TAG_PROTO_EDSA:
64049a99bef5STobias Waldekranz switch (chip->info->edsa_support) {
64059a99bef5STobias Waldekranz case MV88E6XXX_EDSA_UNSUPPORTED:
64069a99bef5STobias Waldekranz return -EPROTONOSUPPORT;
64079a99bef5STobias Waldekranz case MV88E6XXX_EDSA_UNDOCUMENTED:
64089a99bef5STobias Waldekranz dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
64099a99bef5STobias Waldekranz fallthrough;
64109a99bef5STobias Waldekranz case MV88E6XXX_EDSA_SUPPORTED:
64119a99bef5STobias Waldekranz break;
64129a99bef5STobias Waldekranz }
64139a99bef5STobias Waldekranz break;
64149a99bef5STobias Waldekranz case DSA_TAG_PROTO_DSA:
64159a99bef5STobias Waldekranz break;
64169a99bef5STobias Waldekranz default:
64179a99bef5STobias Waldekranz return -EPROTONOSUPPORT;
64189a99bef5STobias Waldekranz }
64199a99bef5STobias Waldekranz
64209a99bef5STobias Waldekranz old_protocol = chip->tag_protocol;
64219a99bef5STobias Waldekranz chip->tag_protocol = proto;
64229a99bef5STobias Waldekranz
64239a99bef5STobias Waldekranz mv88e6xxx_reg_lock(chip);
6424bacf93b0SVladimir Oltean dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6425bacf93b0SVladimir Oltean err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6426bacf93b0SVladimir Oltean if (err) {
6427bacf93b0SVladimir Oltean mv88e6xxx_reg_unlock(chip);
6428bacf93b0SVladimir Oltean goto unwind;
6429bacf93b0SVladimir Oltean }
6430bacf93b0SVladimir Oltean }
64319a99bef5STobias Waldekranz mv88e6xxx_reg_unlock(chip);
64329a99bef5STobias Waldekranz
6433bacf93b0SVladimir Oltean return 0;
6434bacf93b0SVladimir Oltean
6435bacf93b0SVladimir Oltean unwind:
64369a99bef5STobias Waldekranz chip->tag_protocol = old_protocol;
64379a99bef5STobias Waldekranz
6438bacf93b0SVladimir Oltean mv88e6xxx_reg_lock(chip);
6439bacf93b0SVladimir Oltean dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6440bacf93b0SVladimir Oltean mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6441bacf93b0SVladimir Oltean mv88e6xxx_reg_unlock(chip);
6442bacf93b0SVladimir Oltean
64439a99bef5STobias Waldekranz return err;
64449a99bef5STobias Waldekranz }
64459a99bef5STobias Waldekranz
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6446a52b2da7SVladimir Oltean static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6447c2693363SVladimir Oltean const struct switchdev_obj_port_mdb *mdb,
6448c2693363SVladimir Oltean struct dsa_db db)
64497df8fbddSVivien Didelot {
645004bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
6451a52b2da7SVladimir Oltean int err;
64527df8fbddSVivien Didelot
6453c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
6454a52b2da7SVladimir Oltean err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6455a52b2da7SVladimir Oltean MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6456c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
6457a52b2da7SVladimir Oltean
6458a52b2da7SVladimir Oltean return err;
64597df8fbddSVivien Didelot }
64607df8fbddSVivien Didelot
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)64617df8fbddSVivien Didelot static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6462c2693363SVladimir Oltean const struct switchdev_obj_port_mdb *mdb,
6463c2693363SVladimir Oltean struct dsa_db db)
64647df8fbddSVivien Didelot {
646504bed143SVivien Didelot struct mv88e6xxx_chip *chip = ds->priv;
64667df8fbddSVivien Didelot int err;
64677df8fbddSVivien Didelot
6468c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
6469d8291a95SVivien Didelot err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6470c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
64717df8fbddSVivien Didelot
64727df8fbddSVivien Didelot return err;
64737df8fbddSVivien Didelot }
64747df8fbddSVivien Didelot
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)6475f0942e00SIwan R Timmer static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6476f0942e00SIwan R Timmer struct dsa_mall_mirror_tc_entry *mirror,
64770148bb50SVladimir Oltean bool ingress,
64780148bb50SVladimir Oltean struct netlink_ext_ack *extack)
6479f0942e00SIwan R Timmer {
6480f0942e00SIwan R Timmer enum mv88e6xxx_egress_direction direction = ingress ?
6481f0942e00SIwan R Timmer MV88E6XXX_EGRESS_DIR_INGRESS :
6482f0942e00SIwan R Timmer MV88E6XXX_EGRESS_DIR_EGRESS;
6483f0942e00SIwan R Timmer struct mv88e6xxx_chip *chip = ds->priv;
6484f0942e00SIwan R Timmer bool other_mirrors = false;
6485f0942e00SIwan R Timmer int i;
6486f0942e00SIwan R Timmer int err;
6487f0942e00SIwan R Timmer
6488f0942e00SIwan R Timmer mutex_lock(&chip->reg_lock);
6489f0942e00SIwan R Timmer if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6490f0942e00SIwan R Timmer mirror->to_local_port) {
6491f0942e00SIwan R Timmer for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6492f0942e00SIwan R Timmer other_mirrors |= ingress ?
6493f0942e00SIwan R Timmer chip->ports[i].mirror_ingress :
6494f0942e00SIwan R Timmer chip->ports[i].mirror_egress;
6495f0942e00SIwan R Timmer
6496f0942e00SIwan R Timmer /* Can't change egress port when other mirror is active */
6497f0942e00SIwan R Timmer if (other_mirrors) {
6498f0942e00SIwan R Timmer err = -EBUSY;
6499f0942e00SIwan R Timmer goto out;
6500f0942e00SIwan R Timmer }
6501f0942e00SIwan R Timmer
65022fda45f0SMarek Behún err = mv88e6xxx_set_egress_port(chip, direction,
6503f0942e00SIwan R Timmer mirror->to_local_port);
6504f0942e00SIwan R Timmer if (err)
6505f0942e00SIwan R Timmer goto out;
6506f0942e00SIwan R Timmer }
6507f0942e00SIwan R Timmer
6508f0942e00SIwan R Timmer err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6509f0942e00SIwan R Timmer out:
6510f0942e00SIwan R Timmer mutex_unlock(&chip->reg_lock);
6511f0942e00SIwan R Timmer
6512f0942e00SIwan R Timmer return err;
6513f0942e00SIwan R Timmer }
6514f0942e00SIwan R Timmer
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)6515f0942e00SIwan R Timmer static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6516f0942e00SIwan R Timmer struct dsa_mall_mirror_tc_entry *mirror)
6517f0942e00SIwan R Timmer {
6518f0942e00SIwan R Timmer enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6519f0942e00SIwan R Timmer MV88E6XXX_EGRESS_DIR_INGRESS :
6520f0942e00SIwan R Timmer MV88E6XXX_EGRESS_DIR_EGRESS;
6521f0942e00SIwan R Timmer struct mv88e6xxx_chip *chip = ds->priv;
6522f0942e00SIwan R Timmer bool other_mirrors = false;
6523f0942e00SIwan R Timmer int i;
6524f0942e00SIwan R Timmer
6525f0942e00SIwan R Timmer mutex_lock(&chip->reg_lock);
6526f0942e00SIwan R Timmer if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6527f0942e00SIwan R Timmer dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6528f0942e00SIwan R Timmer
6529f0942e00SIwan R Timmer for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6530f0942e00SIwan R Timmer other_mirrors |= mirror->ingress ?
6531f0942e00SIwan R Timmer chip->ports[i].mirror_ingress :
6532f0942e00SIwan R Timmer chip->ports[i].mirror_egress;
6533f0942e00SIwan R Timmer
6534f0942e00SIwan R Timmer /* Reset egress port when no other mirror is active */
6535f0942e00SIwan R Timmer if (!other_mirrors) {
65362fda45f0SMarek Behún if (mv88e6xxx_set_egress_port(chip, direction,
65372fda45f0SMarek Behún dsa_upstream_port(ds, port)))
6538f0942e00SIwan R Timmer dev_err(ds->dev, "failed to set egress port\n");
6539f0942e00SIwan R Timmer }
6540f0942e00SIwan R Timmer
6541f0942e00SIwan R Timmer mutex_unlock(&chip->reg_lock);
6542f0942e00SIwan R Timmer }
6543f0942e00SIwan R Timmer
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6544a8b659e7SVladimir Oltean static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6545a8b659e7SVladimir Oltean struct switchdev_brport_flags flags,
6546a8b659e7SVladimir Oltean struct netlink_ext_ack *extack)
6547a8b659e7SVladimir Oltean {
6548a8b659e7SVladimir Oltean struct mv88e6xxx_chip *chip = ds->priv;
6549a8b659e7SVladimir Oltean const struct mv88e6xxx_ops *ops;
6550a8b659e7SVladimir Oltean
65518d1d8298STobias Waldekranz if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6552830763b9SHans J. Schultz BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6553a8b659e7SVladimir Oltean return -EINVAL;
6554a8b659e7SVladimir Oltean
6555a8b659e7SVladimir Oltean ops = chip->info->ops;
6556a8b659e7SVladimir Oltean
6557a8b659e7SVladimir Oltean if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6558a8b659e7SVladimir Oltean return -EINVAL;
6559a8b659e7SVladimir Oltean
6560a8b659e7SVladimir Oltean if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6561a8b659e7SVladimir Oltean return -EINVAL;
6562a8b659e7SVladimir Oltean
6563a8b659e7SVladimir Oltean return 0;
6564a8b659e7SVladimir Oltean }
6565a8b659e7SVladimir Oltean
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6566a8b659e7SVladimir Oltean static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6567a8b659e7SVladimir Oltean struct switchdev_brport_flags flags,
6568a8b659e7SVladimir Oltean struct netlink_ext_ack *extack)
65694f85901fSRussell King {
65704f85901fSRussell King struct mv88e6xxx_chip *chip = ds->priv;
6571e06a9af0SHans J. Schultz int err = 0;
65724f85901fSRussell King
6573c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
6574a8b659e7SVladimir Oltean
6575041bd545STobias Waldekranz if (flags.mask & BR_LEARNING) {
6576041bd545STobias Waldekranz bool learning = !!(flags.val & BR_LEARNING);
6577041bd545STobias Waldekranz u16 pav = learning ? (1 << port) : 0;
6578041bd545STobias Waldekranz
6579041bd545STobias Waldekranz err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6580041bd545STobias Waldekranz if (err)
6581041bd545STobias Waldekranz goto out;
6582041bd545STobias Waldekranz }
6583041bd545STobias Waldekranz
6584a8b659e7SVladimir Oltean if (flags.mask & BR_FLOOD) {
6585a8b659e7SVladimir Oltean bool unicast = !!(flags.val & BR_FLOOD);
6586a8b659e7SVladimir Oltean
6587a8b659e7SVladimir Oltean err = chip->info->ops->port_set_ucast_flood(chip, port,
6588a8b659e7SVladimir Oltean unicast);
6589a8b659e7SVladimir Oltean if (err)
6590a8b659e7SVladimir Oltean goto out;
6591a8b659e7SVladimir Oltean }
6592a8b659e7SVladimir Oltean
6593a8b659e7SVladimir Oltean if (flags.mask & BR_MCAST_FLOOD) {
6594a8b659e7SVladimir Oltean bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6595a8b659e7SVladimir Oltean
6596a8b659e7SVladimir Oltean err = chip->info->ops->port_set_mcast_flood(chip, port,
65974f85901fSRussell King multicast);
6598a8b659e7SVladimir Oltean if (err)
6599a8b659e7SVladimir Oltean goto out;
6600a8b659e7SVladimir Oltean }
6601a8b659e7SVladimir Oltean
66028d1d8298STobias Waldekranz if (flags.mask & BR_BCAST_FLOOD) {
66038d1d8298STobias Waldekranz bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
66048d1d8298STobias Waldekranz
66058d1d8298STobias Waldekranz err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
66068d1d8298STobias Waldekranz if (err)
66078d1d8298STobias Waldekranz goto out;
66088d1d8298STobias Waldekranz }
66098d1d8298STobias Waldekranz
6610830763b9SHans J. Schultz if (flags.mask & BR_PORT_MAB) {
6611830763b9SHans J. Schultz bool mab = !!(flags.val & BR_PORT_MAB);
6612830763b9SHans J. Schultz
6613830763b9SHans J. Schultz mv88e6xxx_port_set_mab(chip, port, mab);
6614830763b9SHans J. Schultz }
6615830763b9SHans J. Schultz
661634ea415fSHans Schultz if (flags.mask & BR_PORT_LOCKED) {
661734ea415fSHans Schultz bool locked = !!(flags.val & BR_PORT_LOCKED);
661834ea415fSHans Schultz
661934ea415fSHans Schultz err = mv88e6xxx_port_set_lock(chip, port, locked);
662034ea415fSHans Schultz if (err)
662134ea415fSHans Schultz goto out;
662234ea415fSHans Schultz }
6623a8b659e7SVladimir Oltean out:
6624a8b659e7SVladimir Oltean mv88e6xxx_reg_unlock(chip);
6625a8b659e7SVladimir Oltean
6626a8b659e7SVladimir Oltean return err;
6627a8b659e7SVladimir Oltean }
6628a8b659e7SVladimir Oltean
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)662957e661aaSTobias Waldekranz static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6630dedd6a00SVladimir Oltean struct dsa_lag lag,
66312e359b00SVladimir Oltean struct netdev_lag_upper_info *info,
66322e359b00SVladimir Oltean struct netlink_ext_ack *extack)
663357e661aaSTobias Waldekranz {
6634b80dc51bSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
663557e661aaSTobias Waldekranz struct dsa_port *dp;
6636dedd6a00SVladimir Oltean int members = 0;
663757e661aaSTobias Waldekranz
66382e359b00SVladimir Oltean if (!mv88e6xxx_has_lag(chip)) {
66392e359b00SVladimir Oltean NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6640b80dc51bSTobias Waldekranz return false;
66412e359b00SVladimir Oltean }
6642b80dc51bSTobias Waldekranz
6643dedd6a00SVladimir Oltean if (!lag.id)
664457e661aaSTobias Waldekranz return false;
664557e661aaSTobias Waldekranz
6646dedd6a00SVladimir Oltean dsa_lag_foreach_port(dp, ds->dst, &lag)
664757e661aaSTobias Waldekranz /* Includes the port joining the LAG */
664857e661aaSTobias Waldekranz members++;
664957e661aaSTobias Waldekranz
66502e359b00SVladimir Oltean if (members > 8) {
66512e359b00SVladimir Oltean NL_SET_ERR_MSG_MOD(extack,
66522e359b00SVladimir Oltean "Cannot offload more than 8 LAG ports");
665357e661aaSTobias Waldekranz return false;
66542e359b00SVladimir Oltean }
665557e661aaSTobias Waldekranz
665657e661aaSTobias Waldekranz /* We could potentially relax this to include active
665757e661aaSTobias Waldekranz * backup in the future.
665857e661aaSTobias Waldekranz */
66592e359b00SVladimir Oltean if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
66602e359b00SVladimir Oltean NL_SET_ERR_MSG_MOD(extack,
66612e359b00SVladimir Oltean "Can only offload LAG using hash TX type");
666257e661aaSTobias Waldekranz return false;
66632e359b00SVladimir Oltean }
666457e661aaSTobias Waldekranz
666557e661aaSTobias Waldekranz /* Ideally we would also validate that the hash type matches
666657e661aaSTobias Waldekranz * the hardware. Alas, this is always set to unknown on team
666757e661aaSTobias Waldekranz * interfaces.
666857e661aaSTobias Waldekranz */
666957e661aaSTobias Waldekranz return true;
667057e661aaSTobias Waldekranz }
667157e661aaSTobias Waldekranz
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct dsa_lag lag)6672dedd6a00SVladimir Oltean static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
667357e661aaSTobias Waldekranz {
667457e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
667557e661aaSTobias Waldekranz struct dsa_port *dp;
667657e661aaSTobias Waldekranz u16 map = 0;
667757e661aaSTobias Waldekranz int id;
667857e661aaSTobias Waldekranz
66793d4a0a2aSVladimir Oltean /* DSA LAG IDs are one-based, hardware is zero-based */
6680dedd6a00SVladimir Oltean id = lag.id - 1;
668157e661aaSTobias Waldekranz
668257e661aaSTobias Waldekranz /* Build the map of all ports to distribute flows destined for
668357e661aaSTobias Waldekranz * this LAG. This can be either a local user port, or a DSA
668457e661aaSTobias Waldekranz * port if the LAG port is on a remote chip.
668557e661aaSTobias Waldekranz */
6686dedd6a00SVladimir Oltean dsa_lag_foreach_port(dp, ds->dst, &lag)
668757e661aaSTobias Waldekranz map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
668857e661aaSTobias Waldekranz
668957e661aaSTobias Waldekranz return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
669057e661aaSTobias Waldekranz }
669157e661aaSTobias Waldekranz
669257e661aaSTobias Waldekranz static const u8 mv88e6xxx_lag_mask_table[8][8] = {
669357e661aaSTobias Waldekranz /* Row number corresponds to the number of active members in a
669457e661aaSTobias Waldekranz * LAG. Each column states which of the eight hash buckets are
669557e661aaSTobias Waldekranz * mapped to the column:th port in the LAG.
669657e661aaSTobias Waldekranz *
669757e661aaSTobias Waldekranz * Example: In a LAG with three active ports, the second port
669857e661aaSTobias Waldekranz * ([2][1]) would be selected for traffic mapped to buckets
669957e661aaSTobias Waldekranz * 3,4,5 (0x38).
670057e661aaSTobias Waldekranz */
670157e661aaSTobias Waldekranz { 0xff, 0, 0, 0, 0, 0, 0, 0 },
670257e661aaSTobias Waldekranz { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
670357e661aaSTobias Waldekranz { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
670457e661aaSTobias Waldekranz { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
670557e661aaSTobias Waldekranz { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
670657e661aaSTobias Waldekranz { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
670757e661aaSTobias Waldekranz { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
670857e661aaSTobias Waldekranz { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
670957e661aaSTobias Waldekranz };
671057e661aaSTobias Waldekranz
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)671157e661aaSTobias Waldekranz static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
671257e661aaSTobias Waldekranz int num_tx, int nth)
671357e661aaSTobias Waldekranz {
671457e661aaSTobias Waldekranz u8 active = 0;
671557e661aaSTobias Waldekranz int i;
671657e661aaSTobias Waldekranz
671757e661aaSTobias Waldekranz num_tx = num_tx <= 8 ? num_tx : 8;
671857e661aaSTobias Waldekranz if (nth < num_tx)
671957e661aaSTobias Waldekranz active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
672057e661aaSTobias Waldekranz
672157e661aaSTobias Waldekranz for (i = 0; i < 8; i++) {
672257e661aaSTobias Waldekranz if (BIT(i) & active)
672357e661aaSTobias Waldekranz mask[i] |= BIT(port);
672457e661aaSTobias Waldekranz }
672557e661aaSTobias Waldekranz }
672657e661aaSTobias Waldekranz
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)672757e661aaSTobias Waldekranz static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
672857e661aaSTobias Waldekranz {
672957e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
673057e661aaSTobias Waldekranz unsigned int id, num_tx;
673157e661aaSTobias Waldekranz struct dsa_port *dp;
6732dedd6a00SVladimir Oltean struct dsa_lag *lag;
673357e661aaSTobias Waldekranz int i, err, nth;
673457e661aaSTobias Waldekranz u16 mask[8];
673557e661aaSTobias Waldekranz u16 ivec;
673657e661aaSTobias Waldekranz
673757e661aaSTobias Waldekranz /* Assume no port is a member of any LAG. */
673857e661aaSTobias Waldekranz ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
673957e661aaSTobias Waldekranz
674057e661aaSTobias Waldekranz /* Disable all masks for ports that _are_ members of a LAG. */
6741b99dbdf0SVladimir Oltean dsa_switch_for_each_port(dp, ds) {
6742dedd6a00SVladimir Oltean if (!dp->lag)
674357e661aaSTobias Waldekranz continue;
674457e661aaSTobias Waldekranz
674557e661aaSTobias Waldekranz ivec &= ~BIT(dp->index);
674657e661aaSTobias Waldekranz }
674757e661aaSTobias Waldekranz
674857e661aaSTobias Waldekranz for (i = 0; i < 8; i++)
674957e661aaSTobias Waldekranz mask[i] = ivec;
675057e661aaSTobias Waldekranz
675157e661aaSTobias Waldekranz /* Enable the correct subset of masks for all LAG ports that
675257e661aaSTobias Waldekranz * are in the Tx set.
675357e661aaSTobias Waldekranz */
675457e661aaSTobias Waldekranz dsa_lags_foreach_id(id, ds->dst) {
6755dedd6a00SVladimir Oltean lag = dsa_lag_by_id(ds->dst, id);
6756dedd6a00SVladimir Oltean if (!lag)
675757e661aaSTobias Waldekranz continue;
675857e661aaSTobias Waldekranz
675957e661aaSTobias Waldekranz num_tx = 0;
6760dedd6a00SVladimir Oltean dsa_lag_foreach_port(dp, ds->dst, lag) {
676157e661aaSTobias Waldekranz if (dp->lag_tx_enabled)
676257e661aaSTobias Waldekranz num_tx++;
676357e661aaSTobias Waldekranz }
676457e661aaSTobias Waldekranz
676557e661aaSTobias Waldekranz if (!num_tx)
676657e661aaSTobias Waldekranz continue;
676757e661aaSTobias Waldekranz
676857e661aaSTobias Waldekranz nth = 0;
6769dedd6a00SVladimir Oltean dsa_lag_foreach_port(dp, ds->dst, lag) {
677057e661aaSTobias Waldekranz if (!dp->lag_tx_enabled)
677157e661aaSTobias Waldekranz continue;
677257e661aaSTobias Waldekranz
677357e661aaSTobias Waldekranz if (dp->ds == ds)
677457e661aaSTobias Waldekranz mv88e6xxx_lag_set_port_mask(mask, dp->index,
677557e661aaSTobias Waldekranz num_tx, nth);
677657e661aaSTobias Waldekranz
677757e661aaSTobias Waldekranz nth++;
677857e661aaSTobias Waldekranz }
677957e661aaSTobias Waldekranz }
678057e661aaSTobias Waldekranz
678157e661aaSTobias Waldekranz for (i = 0; i < 8; i++) {
678257e661aaSTobias Waldekranz err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
678357e661aaSTobias Waldekranz if (err)
678457e661aaSTobias Waldekranz return err;
678557e661aaSTobias Waldekranz }
678657e661aaSTobias Waldekranz
678757e661aaSTobias Waldekranz return 0;
678857e661aaSTobias Waldekranz }
678957e661aaSTobias Waldekranz
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct dsa_lag lag)679057e661aaSTobias Waldekranz static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6791dedd6a00SVladimir Oltean struct dsa_lag lag)
679257e661aaSTobias Waldekranz {
679357e661aaSTobias Waldekranz int err;
679457e661aaSTobias Waldekranz
679557e661aaSTobias Waldekranz err = mv88e6xxx_lag_sync_masks(ds);
679657e661aaSTobias Waldekranz
679757e661aaSTobias Waldekranz if (!err)
6798dedd6a00SVladimir Oltean err = mv88e6xxx_lag_sync_map(ds, lag);
679957e661aaSTobias Waldekranz
680057e661aaSTobias Waldekranz return err;
680157e661aaSTobias Waldekranz }
680257e661aaSTobias Waldekranz
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)680357e661aaSTobias Waldekranz static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
680457e661aaSTobias Waldekranz {
680557e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
680657e661aaSTobias Waldekranz int err;
680757e661aaSTobias Waldekranz
680857e661aaSTobias Waldekranz mv88e6xxx_reg_lock(chip);
680957e661aaSTobias Waldekranz err = mv88e6xxx_lag_sync_masks(ds);
681057e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
681157e661aaSTobias Waldekranz return err;
681257e661aaSTobias Waldekranz }
681357e661aaSTobias Waldekranz
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)681457e661aaSTobias Waldekranz static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6815dedd6a00SVladimir Oltean struct dsa_lag lag,
68162e359b00SVladimir Oltean struct netdev_lag_upper_info *info,
68172e359b00SVladimir Oltean struct netlink_ext_ack *extack)
681857e661aaSTobias Waldekranz {
681957e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
682057e661aaSTobias Waldekranz int err, id;
682157e661aaSTobias Waldekranz
68222e359b00SVladimir Oltean if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
682357e661aaSTobias Waldekranz return -EOPNOTSUPP;
682457e661aaSTobias Waldekranz
68253d4a0a2aSVladimir Oltean /* DSA LAG IDs are one-based */
6826dedd6a00SVladimir Oltean id = lag.id - 1;
682757e661aaSTobias Waldekranz
682857e661aaSTobias Waldekranz mv88e6xxx_reg_lock(chip);
682957e661aaSTobias Waldekranz
683057e661aaSTobias Waldekranz err = mv88e6xxx_port_set_trunk(chip, port, true, id);
683157e661aaSTobias Waldekranz if (err)
683257e661aaSTobias Waldekranz goto err_unlock;
683357e661aaSTobias Waldekranz
6834dedd6a00SVladimir Oltean err = mv88e6xxx_lag_sync_masks_map(ds, lag);
683557e661aaSTobias Waldekranz if (err)
683657e661aaSTobias Waldekranz goto err_clear_trunk;
683757e661aaSTobias Waldekranz
683857e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
683957e661aaSTobias Waldekranz return 0;
684057e661aaSTobias Waldekranz
684157e661aaSTobias Waldekranz err_clear_trunk:
684257e661aaSTobias Waldekranz mv88e6xxx_port_set_trunk(chip, port, false, 0);
684357e661aaSTobias Waldekranz err_unlock:
684457e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
684557e661aaSTobias Waldekranz return err;
684657e661aaSTobias Waldekranz }
684757e661aaSTobias Waldekranz
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)684857e661aaSTobias Waldekranz static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6849dedd6a00SVladimir Oltean struct dsa_lag lag)
685057e661aaSTobias Waldekranz {
685157e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
685257e661aaSTobias Waldekranz int err_sync, err_trunk;
685357e661aaSTobias Waldekranz
685457e661aaSTobias Waldekranz mv88e6xxx_reg_lock(chip);
6855dedd6a00SVladimir Oltean err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
685657e661aaSTobias Waldekranz err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
685757e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
685857e661aaSTobias Waldekranz return err_sync ? : err_trunk;
685957e661aaSTobias Waldekranz }
686057e661aaSTobias Waldekranz
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)686157e661aaSTobias Waldekranz static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
686257e661aaSTobias Waldekranz int port)
686357e661aaSTobias Waldekranz {
686457e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
686557e661aaSTobias Waldekranz int err;
686657e661aaSTobias Waldekranz
686757e661aaSTobias Waldekranz mv88e6xxx_reg_lock(chip);
686857e661aaSTobias Waldekranz err = mv88e6xxx_lag_sync_masks(ds);
686957e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
687057e661aaSTobias Waldekranz return err;
687157e661aaSTobias Waldekranz }
687257e661aaSTobias Waldekranz
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)687357e661aaSTobias Waldekranz static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6874dedd6a00SVladimir Oltean int port, struct dsa_lag lag,
68752e359b00SVladimir Oltean struct netdev_lag_upper_info *info,
68762e359b00SVladimir Oltean struct netlink_ext_ack *extack)
687757e661aaSTobias Waldekranz {
687857e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
687957e661aaSTobias Waldekranz int err;
688057e661aaSTobias Waldekranz
68812e359b00SVladimir Oltean if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
688257e661aaSTobias Waldekranz return -EOPNOTSUPP;
688357e661aaSTobias Waldekranz
688457e661aaSTobias Waldekranz mv88e6xxx_reg_lock(chip);
688557e661aaSTobias Waldekranz
6886dedd6a00SVladimir Oltean err = mv88e6xxx_lag_sync_masks_map(ds, lag);
688757e661aaSTobias Waldekranz if (err)
688857e661aaSTobias Waldekranz goto unlock;
688957e661aaSTobias Waldekranz
689057e661aaSTobias Waldekranz err = mv88e6xxx_pvt_map(chip, sw_index, port);
689157e661aaSTobias Waldekranz
689257e661aaSTobias Waldekranz unlock:
689357e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
689457e661aaSTobias Waldekranz return err;
689557e661aaSTobias Waldekranz }
689657e661aaSTobias Waldekranz
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag)689757e661aaSTobias Waldekranz static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6898dedd6a00SVladimir Oltean int port, struct dsa_lag lag)
689957e661aaSTobias Waldekranz {
690057e661aaSTobias Waldekranz struct mv88e6xxx_chip *chip = ds->priv;
690157e661aaSTobias Waldekranz int err_sync, err_pvt;
690257e661aaSTobias Waldekranz
690357e661aaSTobias Waldekranz mv88e6xxx_reg_lock(chip);
6904dedd6a00SVladimir Oltean err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
690557e661aaSTobias Waldekranz err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
690657e661aaSTobias Waldekranz mv88e6xxx_reg_unlock(chip);
690757e661aaSTobias Waldekranz return err_sync ? : err_pvt;
690857e661aaSTobias Waldekranz }
690957e661aaSTobias Waldekranz
6910a82f67afSFlorian Fainelli static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
69117b314362SAndrew Lunn .get_tag_protocol = mv88e6xxx_get_tag_protocol,
69129a99bef5STobias Waldekranz .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6913fad09c73SVivien Didelot .setup = mv88e6xxx_setup,
691423e8b470SAndrew Lunn .teardown = mv88e6xxx_teardown,
6915fd292c18SVladimir Oltean .port_setup = mv88e6xxx_port_setup,
6916fd292c18SVladimir Oltean .port_teardown = mv88e6xxx_port_teardown,
6917d4ebf12bSRussell King (Oracle) .phylink_get_caps = mv88e6xxx_get_caps,
6918b92143d4SRussell King (Oracle) .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6919267d7692SRussell King (Oracle) .phylink_mac_prepare = mv88e6xxx_mac_prepare,
6920c9a2356fSRussell King .phylink_mac_config = mv88e6xxx_mac_config,
6921267d7692SRussell King (Oracle) .phylink_mac_finish = mv88e6xxx_mac_finish,
6922c9a2356fSRussell King .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6923c9a2356fSRussell King .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6924fad09c73SVivien Didelot .get_strings = mv88e6xxx_get_strings,
6925fad09c73SVivien Didelot .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6926fad09c73SVivien Didelot .get_sset_count = mv88e6xxx_get_sset_count,
69272a550aecSAndrew Lunn .port_max_mtu = mv88e6xxx_get_max_mtu,
69282a550aecSAndrew Lunn .port_change_mtu = mv88e6xxx_change_mtu,
692908f50061SVivien Didelot .get_mac_eee = mv88e6xxx_get_mac_eee,
693008f50061SVivien Didelot .set_mac_eee = mv88e6xxx_set_mac_eee,
6931fad09c73SVivien Didelot .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6932fad09c73SVivien Didelot .get_eeprom = mv88e6xxx_get_eeprom,
6933fad09c73SVivien Didelot .set_eeprom = mv88e6xxx_set_eeprom,
6934fad09c73SVivien Didelot .get_regs_len = mv88e6xxx_get_regs_len,
6935fad09c73SVivien Didelot .get_regs = mv88e6xxx_get_regs,
6936da7dc875SVivien Didelot .get_rxnfc = mv88e6xxx_get_rxnfc,
6937da7dc875SVivien Didelot .set_rxnfc = mv88e6xxx_set_rxnfc,
69382cfcd964SVivien Didelot .set_ageing_time = mv88e6xxx_set_ageing_time,
6939fad09c73SVivien Didelot .port_bridge_join = mv88e6xxx_port_bridge_join,
6940fad09c73SVivien Didelot .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6941a8b659e7SVladimir Oltean .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6942a8b659e7SVladimir Oltean .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6943fad09c73SVivien Didelot .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6944acaf4d2eSTobias Waldekranz .port_mst_state_set = mv88e6xxx_port_mst_state_set,
6945749efcb8SVivien Didelot .port_fast_age = mv88e6xxx_port_fast_age,
6946acaf4d2eSTobias Waldekranz .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
6947fad09c73SVivien Didelot .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6948fad09c73SVivien Didelot .port_vlan_add = mv88e6xxx_port_vlan_add,
6949fad09c73SVivien Didelot .port_vlan_del = mv88e6xxx_port_vlan_del,
6950acaf4d2eSTobias Waldekranz .vlan_msti_set = mv88e6xxx_vlan_msti_set,
6951fad09c73SVivien Didelot .port_fdb_add = mv88e6xxx_port_fdb_add,
6952fad09c73SVivien Didelot .port_fdb_del = mv88e6xxx_port_fdb_del,
6953fad09c73SVivien Didelot .port_fdb_dump = mv88e6xxx_port_fdb_dump,
69547df8fbddSVivien Didelot .port_mdb_add = mv88e6xxx_port_mdb_add,
69557df8fbddSVivien Didelot .port_mdb_del = mv88e6xxx_port_mdb_del,
6956f0942e00SIwan R Timmer .port_mirror_add = mv88e6xxx_port_mirror_add,
6957f0942e00SIwan R Timmer .port_mirror_del = mv88e6xxx_port_mirror_del,
6958aec5ac88SVivien Didelot .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6959aec5ac88SVivien Didelot .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6960c6fe0ad2SBrandon Streiff .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6961c6fe0ad2SBrandon Streiff .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6962c6fe0ad2SBrandon Streiff .port_txtstamp = mv88e6xxx_port_txtstamp,
6963c6fe0ad2SBrandon Streiff .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6964c6fe0ad2SBrandon Streiff .get_ts_info = mv88e6xxx_get_ts_info,
696523e8b470SAndrew Lunn .devlink_param_get = mv88e6xxx_devlink_param_get,
696623e8b470SAndrew Lunn .devlink_param_set = mv88e6xxx_devlink_param_set,
696793157307SAndrew Lunn .devlink_info_get = mv88e6xxx_devlink_info_get,
696857e661aaSTobias Waldekranz .port_lag_change = mv88e6xxx_port_lag_change,
696957e661aaSTobias Waldekranz .port_lag_join = mv88e6xxx_port_lag_join,
697057e661aaSTobias Waldekranz .port_lag_leave = mv88e6xxx_port_lag_leave,
697157e661aaSTobias Waldekranz .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
697257e661aaSTobias Waldekranz .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
697357e661aaSTobias Waldekranz .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6974fad09c73SVivien Didelot };
6975fad09c73SVivien Didelot
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)697655ed0ce0SFlorian Fainelli static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6977fad09c73SVivien Didelot {
6978fad09c73SVivien Didelot struct device *dev = chip->dev;
6979fad09c73SVivien Didelot struct dsa_switch *ds;
6980fad09c73SVivien Didelot
69817e99e347SVivien Didelot ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6982fad09c73SVivien Didelot if (!ds)
6983fad09c73SVivien Didelot return -ENOMEM;
6984fad09c73SVivien Didelot
69857e99e347SVivien Didelot ds->dev = dev;
69867e99e347SVivien Didelot ds->num_ports = mv88e6xxx_num_ports(chip);
6987fad09c73SVivien Didelot ds->priv = chip;
6988877b7cb0SAndrew Lunn ds->dev = dev;
69899d490b4eSVivien Didelot ds->ops = &mv88e6xxx_switch_ops;
69909ff74f24SVivien Didelot ds->ageing_time_min = chip->info->age_time_coeff;
69919ff74f24SVivien Didelot ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6992fad09c73SVivien Didelot
699357e661aaSTobias Waldekranz /* Some chips support up to 32, but that requires enabling the
699457e661aaSTobias Waldekranz * 5-bit port mode, which we do not support. 640k^W16 ought to
699557e661aaSTobias Waldekranz * be enough for anyone.
699657e661aaSTobias Waldekranz */
6997b80dc51bSTobias Waldekranz ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
699857e661aaSTobias Waldekranz
6999fad09c73SVivien Didelot dev_set_drvdata(dev, ds);
7000fad09c73SVivien Didelot
700123c9ee49SVivien Didelot return dsa_register_switch(ds);
7002fad09c73SVivien Didelot }
7003fad09c73SVivien Didelot
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)7004fad09c73SVivien Didelot static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7005fad09c73SVivien Didelot {
7006fad09c73SVivien Didelot dsa_unregister_switch(chip->ds);
7007fad09c73SVivien Didelot }
7008fad09c73SVivien Didelot
pdata_device_get_match_data(struct device * dev)7009877b7cb0SAndrew Lunn static const void *pdata_device_get_match_data(struct device *dev)
7010877b7cb0SAndrew Lunn {
7011877b7cb0SAndrew Lunn const struct of_device_id *matches = dev->driver->of_match_table;
7012877b7cb0SAndrew Lunn const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7013877b7cb0SAndrew Lunn
7014877b7cb0SAndrew Lunn for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7015877b7cb0SAndrew Lunn matches++) {
7016877b7cb0SAndrew Lunn if (!strcmp(pdata->compatible, matches->compatible))
7017877b7cb0SAndrew Lunn return matches->data;
7018877b7cb0SAndrew Lunn }
7019877b7cb0SAndrew Lunn return NULL;
7020877b7cb0SAndrew Lunn }
7021877b7cb0SAndrew Lunn
7022bcd3d9d9SMiquel Raynal /* There is no suspend to RAM support at DSA level yet, the switch configuration
7023bcd3d9d9SMiquel Raynal * would be lost after a power cycle so prevent it to be suspended.
7024bcd3d9d9SMiquel Raynal */
mv88e6xxx_suspend(struct device * dev)7025bcd3d9d9SMiquel Raynal static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7026bcd3d9d9SMiquel Raynal {
7027bcd3d9d9SMiquel Raynal return -EOPNOTSUPP;
7028bcd3d9d9SMiquel Raynal }
7029bcd3d9d9SMiquel Raynal
mv88e6xxx_resume(struct device * dev)7030bcd3d9d9SMiquel Raynal static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7031bcd3d9d9SMiquel Raynal {
7032bcd3d9d9SMiquel Raynal return 0;
7033bcd3d9d9SMiquel Raynal }
7034bcd3d9d9SMiquel Raynal
7035bcd3d9d9SMiquel Raynal static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7036bcd3d9d9SMiquel Raynal
mv88e6xxx_probe(struct mdio_device * mdiodev)7037fad09c73SVivien Didelot static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7038fad09c73SVivien Didelot {
7039877b7cb0SAndrew Lunn struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
70407ddae24fSDavid S. Miller const struct mv88e6xxx_info *compat_info = NULL;
7041fad09c73SVivien Didelot struct device *dev = &mdiodev->dev;
7042fad09c73SVivien Didelot struct device_node *np = dev->of_node;
7043fad09c73SVivien Didelot struct mv88e6xxx_chip *chip;
7044877b7cb0SAndrew Lunn int port;
7045fad09c73SVivien Didelot int err;
7046fad09c73SVivien Didelot
70477bb8c996SAndrew Lunn if (!np && !pdata)
70487bb8c996SAndrew Lunn return -EINVAL;
70497bb8c996SAndrew Lunn
7050877b7cb0SAndrew Lunn if (np)
7051fad09c73SVivien Didelot compat_info = of_device_get_match_data(dev);
7052877b7cb0SAndrew Lunn
7053877b7cb0SAndrew Lunn if (pdata) {
7054877b7cb0SAndrew Lunn compat_info = pdata_device_get_match_data(dev);
7055877b7cb0SAndrew Lunn
7056877b7cb0SAndrew Lunn if (!pdata->netdev)
7057877b7cb0SAndrew Lunn return -EINVAL;
7058877b7cb0SAndrew Lunn
7059877b7cb0SAndrew Lunn for (port = 0; port < DSA_MAX_PORTS; port++) {
7060877b7cb0SAndrew Lunn if (!(pdata->enabled_ports & (1 << port)))
7061877b7cb0SAndrew Lunn continue;
7062877b7cb0SAndrew Lunn if (strcmp(pdata->cd.port_names[port], "cpu"))
7063877b7cb0SAndrew Lunn continue;
7064877b7cb0SAndrew Lunn pdata->cd.netdev[port] = &pdata->netdev->dev;
7065877b7cb0SAndrew Lunn break;
7066877b7cb0SAndrew Lunn }
7067877b7cb0SAndrew Lunn }
7068877b7cb0SAndrew Lunn
7069fad09c73SVivien Didelot if (!compat_info)
7070fad09c73SVivien Didelot return -EINVAL;
7071fad09c73SVivien Didelot
7072fad09c73SVivien Didelot chip = mv88e6xxx_alloc_chip(dev);
7073877b7cb0SAndrew Lunn if (!chip) {
7074877b7cb0SAndrew Lunn err = -ENOMEM;
7075877b7cb0SAndrew Lunn goto out;
7076877b7cb0SAndrew Lunn }
7077fad09c73SVivien Didelot
7078fad09c73SVivien Didelot chip->info = compat_info;
7079fad09c73SVivien Didelot
7080b4308f04SAndrew Lunn chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7081877b7cb0SAndrew Lunn if (IS_ERR(chip->reset)) {
7082877b7cb0SAndrew Lunn err = PTR_ERR(chip->reset);
7083877b7cb0SAndrew Lunn goto out;
7084877b7cb0SAndrew Lunn }
70857b75e49dSBaruch Siach if (chip->reset)
70863c27f3d5SAndreas Svensson usleep_range(10000, 20000);
7087b4308f04SAndrew Lunn
70885da66099SNathan Rossi /* Detect if the device is configured in single chip addressing mode,
70895da66099SNathan Rossi * otherwise continue with address specific smi init/detection.
70905da66099SNathan Rossi */
70915da66099SNathan Rossi err = mv88e6xxx_single_chip_detect(chip, mdiodev);
70925da66099SNathan Rossi if (err) {
70935da66099SNathan Rossi err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
70945da66099SNathan Rossi if (err)
70955da66099SNathan Rossi goto out;
70965da66099SNathan Rossi
7097fad09c73SVivien Didelot err = mv88e6xxx_detect(chip);
7098fad09c73SVivien Didelot if (err)
7099877b7cb0SAndrew Lunn goto out;
71005da66099SNathan Rossi }
7101fad09c73SVivien Didelot
7102670bb80fSTobias Waldekranz if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7103670bb80fSTobias Waldekranz chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7104670bb80fSTobias Waldekranz else
7105670bb80fSTobias Waldekranz chip->tag_protocol = DSA_TAG_PROTO_DSA;
7106670bb80fSTobias Waldekranz
7107e57e5e77SVivien Didelot mv88e6xxx_phy_init(chip);
7108e57e5e77SVivien Didelot
710900baabe5SAndrew Lunn if (chip->info->ops->get_eeprom) {
711000baabe5SAndrew Lunn if (np)
711100baabe5SAndrew Lunn of_property_read_u32(np, "eeprom-length",
711200baabe5SAndrew Lunn &chip->eeprom_len);
711300baabe5SAndrew Lunn else
711400baabe5SAndrew Lunn chip->eeprom_len = pdata->eeprom_len;
711500baabe5SAndrew Lunn }
7116fad09c73SVivien Didelot
7117c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
7118dc30c35bSAndrew Lunn err = mv88e6xxx_switch_reset(chip);
7119c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
7120fad09c73SVivien Didelot if (err)
7121dc30c35bSAndrew Lunn goto out;
7122fad09c73SVivien Didelot
7123a27415deSAndrew Lunn if (np) {
7124dc30c35bSAndrew Lunn chip->irq = of_irq_get(np, 0);
7125dc30c35bSAndrew Lunn if (chip->irq == -EPROBE_DEFER) {
7126dc30c35bSAndrew Lunn err = chip->irq;
7127dc30c35bSAndrew Lunn goto out;
7128fad09c73SVivien Didelot }
7129a27415deSAndrew Lunn }
7130a27415deSAndrew Lunn
7131a27415deSAndrew Lunn if (pdata)
7132a27415deSAndrew Lunn chip->irq = pdata->irq;
7133fad09c73SVivien Didelot
7134294d711eSAndrew Lunn /* Has to be performed before the MDIO bus is created, because
7135a708767eSUwe Kleine-König * the PHYs will link their interrupts to these interrupt
7136294d711eSAndrew Lunn * controllers
7137dc30c35bSAndrew Lunn */
7138c9acece0SRasmus Villemoes mv88e6xxx_reg_lock(chip);
7139294d711eSAndrew Lunn if (chip->irq > 0)
7140dc30c35bSAndrew Lunn err = mv88e6xxx_g1_irq_setup(chip);
7141294d711eSAndrew Lunn else
7142294d711eSAndrew Lunn err = mv88e6xxx_irq_poll_setup(chip);
7143c9acece0SRasmus Villemoes mv88e6xxx_reg_unlock(chip);
7144dc30c35bSAndrew Lunn
7145dc30c35bSAndrew Lunn if (err)
7146dc30c35bSAndrew Lunn goto out;
7147dc30c35bSAndrew Lunn
7148d6c5e6afSVivien Didelot if (chip->info->g2_irqs > 0) {
7149dc30c35bSAndrew Lunn err = mv88e6xxx_g2_irq_setup(chip);
7150dc30c35bSAndrew Lunn if (err)
7151dc30c35bSAndrew Lunn goto out_g1_irq;
7152dc30c35bSAndrew Lunn }
71530977644cSAndrew Lunn
71540977644cSAndrew Lunn err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
71550977644cSAndrew Lunn if (err)
71560977644cSAndrew Lunn goto out_g2_irq;
715762eb1162SAndrew Lunn
715862eb1162SAndrew Lunn err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
715962eb1162SAndrew Lunn if (err)
716062eb1162SAndrew Lunn goto out_g1_atu_prob_irq;
7161dc30c35bSAndrew Lunn
71622cb0658dSKlaus Kudielka err = mv88e6xxx_register_switch(chip);
7163dc30c35bSAndrew Lunn if (err)
716462eb1162SAndrew Lunn goto out_g1_vtu_prob_irq;
7165dc30c35bSAndrew Lunn
7166fad09c73SVivien Didelot return 0;
7167dc30c35bSAndrew Lunn
716862eb1162SAndrew Lunn out_g1_vtu_prob_irq:
716962eb1162SAndrew Lunn mv88e6xxx_g1_vtu_prob_irq_free(chip);
71700977644cSAndrew Lunn out_g1_atu_prob_irq:
71710977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_free(chip);
7172dc30c35bSAndrew Lunn out_g2_irq:
7173294d711eSAndrew Lunn if (chip->info->g2_irqs > 0)
7174dc30c35bSAndrew Lunn mv88e6xxx_g2_irq_free(chip);
7175dc30c35bSAndrew Lunn out_g1_irq:
7176294d711eSAndrew Lunn if (chip->irq > 0)
7177dc30c35bSAndrew Lunn mv88e6xxx_g1_irq_free(chip);
7178294d711eSAndrew Lunn else
7179294d711eSAndrew Lunn mv88e6xxx_irq_poll_free(chip);
7180dc30c35bSAndrew Lunn out:
7181877b7cb0SAndrew Lunn if (pdata)
7182877b7cb0SAndrew Lunn dev_put(pdata->netdev);
7183877b7cb0SAndrew Lunn
7184dc30c35bSAndrew Lunn return err;
7185fad09c73SVivien Didelot }
7186fad09c73SVivien Didelot
mv88e6xxx_remove(struct mdio_device * mdiodev)7187fad09c73SVivien Didelot static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7188fad09c73SVivien Didelot {
7189fad09c73SVivien Didelot struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
71900650bf52SVladimir Oltean struct mv88e6xxx_chip *chip;
71910650bf52SVladimir Oltean
71920650bf52SVladimir Oltean if (!ds)
71930650bf52SVladimir Oltean return;
71940650bf52SVladimir Oltean
71950650bf52SVladimir Oltean chip = ds->priv;
7196fad09c73SVivien Didelot
7197c6fe0ad2SBrandon Streiff if (chip->info->ptp_support) {
7198c6fe0ad2SBrandon Streiff mv88e6xxx_hwtstamp_free(chip);
71992fa8d3afSBrandon Streiff mv88e6xxx_ptp_free(chip);
7200c6fe0ad2SBrandon Streiff }
72012fa8d3afSBrandon Streiff
7202930188ceSAndrew Lunn mv88e6xxx_phy_destroy(chip);
7203fad09c73SVivien Didelot mv88e6xxx_unregister_switch(chip);
7204dc30c35bSAndrew Lunn
720562eb1162SAndrew Lunn mv88e6xxx_g1_vtu_prob_irq_free(chip);
72060977644cSAndrew Lunn mv88e6xxx_g1_atu_prob_irq_free(chip);
720776f38f1fSAndrew Lunn
7208d6c5e6afSVivien Didelot if (chip->info->g2_irqs > 0)
7209dc30c35bSAndrew Lunn mv88e6xxx_g2_irq_free(chip);
721076f38f1fSAndrew Lunn
721176f38f1fSAndrew Lunn if (chip->irq > 0)
7212dc30c35bSAndrew Lunn mv88e6xxx_g1_irq_free(chip);
721376f38f1fSAndrew Lunn else
721476f38f1fSAndrew Lunn mv88e6xxx_irq_poll_free(chip);
72150650bf52SVladimir Oltean }
72160650bf52SVladimir Oltean
mv88e6xxx_shutdown(struct mdio_device * mdiodev)72170650bf52SVladimir Oltean static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
72180650bf52SVladimir Oltean {
72190650bf52SVladimir Oltean struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
72200650bf52SVladimir Oltean
72210650bf52SVladimir Oltean if (!ds)
72220650bf52SVladimir Oltean return;
72230650bf52SVladimir Oltean
72240650bf52SVladimir Oltean dsa_switch_shutdown(ds);
72250650bf52SVladimir Oltean
72260650bf52SVladimir Oltean dev_set_drvdata(&mdiodev->dev, NULL);
7227fad09c73SVivien Didelot }
7228fad09c73SVivien Didelot
7229fad09c73SVivien Didelot static const struct of_device_id mv88e6xxx_of_match[] = {
7230fad09c73SVivien Didelot {
7231fad09c73SVivien Didelot .compatible = "marvell,mv88e6085",
7232fad09c73SVivien Didelot .data = &mv88e6xxx_table[MV88E6085],
7233fad09c73SVivien Didelot },
72341a3b39ecSAndrew Lunn {
72351a3b39ecSAndrew Lunn .compatible = "marvell,mv88e6190",
72361a3b39ecSAndrew Lunn .data = &mv88e6xxx_table[MV88E6190],
72371a3b39ecSAndrew Lunn },
72381f71836fSRasmus Villemoes {
72391f71836fSRasmus Villemoes .compatible = "marvell,mv88e6250",
72401f71836fSRasmus Villemoes .data = &mv88e6xxx_table[MV88E6250],
72411f71836fSRasmus Villemoes },
7242fad09c73SVivien Didelot { /* sentinel */ },
7243fad09c73SVivien Didelot };
7244fad09c73SVivien Didelot
7245fad09c73SVivien Didelot MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7246fad09c73SVivien Didelot
7247fad09c73SVivien Didelot static struct mdio_driver mv88e6xxx_driver = {
7248fad09c73SVivien Didelot .probe = mv88e6xxx_probe,
7249fad09c73SVivien Didelot .remove = mv88e6xxx_remove,
72500650bf52SVladimir Oltean .shutdown = mv88e6xxx_shutdown,
7251fad09c73SVivien Didelot .mdiodrv.driver = {
7252fad09c73SVivien Didelot .name = "mv88e6085",
7253fad09c73SVivien Didelot .of_match_table = mv88e6xxx_of_match,
7254bcd3d9d9SMiquel Raynal .pm = &mv88e6xxx_pm_ops,
7255fad09c73SVivien Didelot },
7256fad09c73SVivien Didelot };
7257fad09c73SVivien Didelot
72587324d50eSAndrew Lunn mdio_module_driver(mv88e6xxx_driver);
7259fad09c73SVivien Didelot
7260fad09c73SVivien Didelot MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7261fad09c73SVivien Didelot MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7262fad09c73SVivien Didelot MODULE_LICENSE("GPL");
7263