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12

/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dxlnx,usb2.yaml44 interrupts = <0x0 0x39 0x1>;
45 reg = <0xee000000 0xc00>;
H A Drenesas,usb-xhci.yaml114 reg = <0xee000000 0xc00>;
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1010rdb_32b.dtsi41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1010rdb_36b.dtsi41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,ifc.yaml21 pattern: "^memory-controller@[0-9a-f]+$"
89 reg = <0x0 0xffe1e000 0 0x2000>;
94 ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
95 <0x1 0x0 0x0 0xffa00000 0x00010000>,
96 <0x3 0x0 0x0 0xffb00000 0x00020000>;
98 flash@0,0 {
102 reg = <0x0 0x0 0x2000000>;
106 partition@0 {
108 reg = <0x0 0x02000000>;
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c13 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
14 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
15 #define SERDES_COMLANE_REGS 0x0a00
16 #define SERDES_WIZ_REGS 0x1fc0
18 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
19 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
20 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
21 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
22 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
23 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
[all …]
/openbmc/u-boot/include/configs/
H A Dxpedite550x.h30 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39 #define SPD_EEPROM_ADDRESS 0x54
40 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
64 #define CONFIG_SYS_CCSRBAR 0xef000000
70 #define CONFIG_SYS_MEMTEST_START 0x10000000
71 #define CONFIG_SYS_MEMTEST_END 0x20000000
[all …]
H A Dxpedite537x.h30 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
40 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
41 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
55 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
56 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
65 #define CONFIG_SYS_CCSRBAR 0xef000000
71 #define CONFIG_SYS_MEMTEST_START 0x10000000
[all …]
H A DP1010RDB.h19 #define CONFIG_SPL_TEXT_BASE 0xD0001000
20 #define CONFIG_SPL_PAD_TO 0x18000
23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
37 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
42 #define CONFIG_SPL_TEXT_BASE 0xD0001000
43 #define CONFIG_SPL_PAD_TO 0x18000
46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
65 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
[all …]
H A Dp1_p2_rdb_pc.h16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77990.dtsi19 #size-cells = <0>;
21 a53_0: cpu@0 {
23 reg = <0>;
39 L2_CA53: cache-controller-0 {
49 #clock-cells = <0>;
51 clock-frequency = <0>;
76 reg = <0 0xe6020000 0 0x0c>;
86 reg = <0 0xe6050000 0 0x50>;
90 gpio-ranges = <&pfc 0 0 18>;
101 reg = <0 0xe6051000 0 0x50>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/openbmc/u-boot/doc/
H A DREADME.b4860qds75 for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
122 SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
134 SW1 [1.1] = 0
139 SW2 [1.1] = 0
147 SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
159 SW1 [1.1] = 0
164 SW2 [1.1] = 0
172 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
173 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
174 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
[all …]
/openbmc/qemu/hw/arm/
H A Dmps3r.c83 #define PERIPHBASE 0xf0000000
136 .base = 0x00000000,
137 .size = 0x00008000,
138 .mrindex = 0,
142 .base = 0x08000000,
143 .size = 0x00800000,
148 .base = 0x10000000,
149 .size = 0x00080000,
153 .base = 0x20000000,
158 .base = 0xee000000,
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
67 #size-cells = <0>;
[all …]
H A Dr8a77990.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
67 #size-cells = <0>;
[all …]

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