Lines Matching +full:0 +full:xee000000
30 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39 #define SPD_EEPROM_ADDRESS 0x54
40 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
64 #define CONFIG_SYS_CCSRBAR 0xef000000
70 #define CONFIG_SYS_MEMTEST_START 0x10000000
71 #define CONFIG_SYS_MEMTEST_END 0x20000000
84 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
85 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
86 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
87 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
88 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
89 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
90 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
91 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
92 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
100 #define CONFIG_SYS_NAND_BASE 0xef800000
101 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
110 #define CONFIG_SYS_FLASH_BASE 0xf8000000
111 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
117 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
118 {0xf7f40000, 0xc0000} }
124 /* NOR Flash 0 on CS0 */
172 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
173 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
186 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
187 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
188 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
201 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
202 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
204 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
205 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
208 #define CONFIG_SYS_I2C_LM75_ADDR 0x48
211 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
214 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
221 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
226 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
227 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
228 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
229 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
235 /* PCA9557 @ 0x18*/
236 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
237 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232…
238 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
239 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232…
240 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
241 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
243 /* PCA9557 @ 0x1e*/
244 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
245 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
246 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
247 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
248 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
249 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
250 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
252 /* PCA9557 @ 0x1f */
253 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
254 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
255 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
256 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
257 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
258 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
259 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
260 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
264 * Memory space is mapped 1-1, but I/O space must start from 0.
268 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
270 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
271 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
272 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
273 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
296 #define TSEC1_PHYIDX 0
303 #define TSEC2_PHYIDX 0
310 #define TSEC3_PHYIDX 0
322 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
323 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
338 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
339 #define CONFIG_ENV_SIZE 0x8000
356 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
357 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
358 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
359 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
360 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
361 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
365 "if test $? -eq 0; then " \
371 "if test $? -ne 0; then " \
382 "if test $? -eq 0; then " \
388 "if test $? -ne 0; then " \
399 "if test $? -eq 0; then " \
402 "if test $? -eq 0; then " \
416 "if test $? -eq 0; then " \
420 "if test $? -ne 0; then " \
431 "if test $? -eq 0; then " \
435 "if test $? -ne 0; then " \
446 "if test $? -eq 0; then " \
450 "if test $? -ne 0; then " \
461 "if test $? -eq 0; then " \
465 "if test $? -ne 0; then " \
475 "autoload=yes\0" \
476 "download_cmd=tftp\0" \
477 "console_args=console=ttyS0,115200\0" \
478 "root_args=root=/dev/nfs rw\0" \
479 "misc_args=ip=on\0" \
480 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
481 "bootfile=/home/user/file\0" \
482 "osfile=/home/user/board.uImage\0" \
483 "fdtfile=/home/user/board.dtb\0" \
484 "ubootfile=/home/user/u-boot.bin\0" \
485 "fdtaddr=0x1e00000\0" \
486 "osaddr=0x1000000\0" \
487 "loadaddr=0x1000000\0" \
488 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
489 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
490 "prog_os1="CONFIG_PROG_OS1"\0" \
491 "prog_os2="CONFIG_PROG_OS2"\0" \
492 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
493 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
494 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
496 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
498 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
499 "bootcmd=run bootcmd_flash1\0"