Lines Matching +full:0 +full:xee000000
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
79 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
81 #define __SW_BOOT_MASK 0x03
82 #define __SW_BOOT_NOR 0x5c
83 #define __SW_BOOT_SPI 0x1c
84 #define __SW_BOOT_SD 0x9c
85 #define __SW_BOOT_NAND 0xec
86 #define __SW_BOOT_PCIE 0x6c
97 #define __SW_BOOT_MASK 0xf3
98 #define __SW_BOOT_NOR 0x00
99 #define __SW_BOOT_SPI 0x08
100 #define __SW_BOOT_SD 0x04
101 #define __SW_BOOT_NAND 0x0c
111 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
113 #define __SW_BOOT_MASK 0xf3
114 #define __SW_BOOT_NOR 0x00
115 #define __SW_BOOT_SPI 0x08
116 #define __SW_BOOT_SD 0x04
117 #define __SW_BOOT_NAND 0x0c
125 #define __SW_BOOT_MASK 0x03
126 #define __SW_BOOT_NOR 0xc8
127 #define __SW_BOOT_SPI 0x28
128 #define __SW_BOOT_SD 0x68 /* or 0x18 */
129 #define __SW_BOOT_NAND 0xe8
130 #define __SW_BOOT_PCIE 0xa8
140 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
141 #define CONFIG_SPL_PAD_TO 0x20000
144 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
145 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
159 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
160 #define CONFIG_SPL_PAD_TO 0x20000
163 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
164 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
181 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
184 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
185 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
191 #define CONFIG_SPL_TEXT_BASE 0xff800000
194 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
195 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
199 #define CONFIG_SPL_PAD_TO 0x20000
200 #define CONFIG_TPL_PAD_TO 0x20000
206 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
252 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
253 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
255 #define CONFIG_SYS_CCSRBAR 0xffe00000
268 #define SPD_EEPROM_ADDRESS 0x52
278 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
285 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
286 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
287 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
288 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
289 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
290 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
292 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
293 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
294 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
295 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
297 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
298 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
299 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
300 #define CONFIG_SYS_DDR_RCW_1 0x00000000
301 #define CONFIG_SYS_DDR_RCW_2 0x00000000
302 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
303 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
304 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
305 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
307 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
308 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
309 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
310 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
311 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
312 #define CONFIG_SYS_DDR_MODE_1 0x40461520
313 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
314 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
322 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
323 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
324 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
325 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
327 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
328 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
329 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
330 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
331 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
332 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
333 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
341 #define CONFIG_SYS_FLASH_BASE 0xec000000
344 #define CONFIG_SYS_FLASH_BASE 0xee000000
347 #define CONFIG_SYS_FLASH_BASE 0xef000000
351 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
359 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
375 #define CONFIG_SYS_NAND_BASE 0xff800000
377 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
416 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
431 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
440 #define CONFIG_SYS_CPLD_BASE 0xffa00000
442 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
449 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
451 #define CONFIG_SYS_PMC_BASE 0xff980000
477 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
480 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
503 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
506 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
517 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
520 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
526 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
529 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
530 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
542 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
550 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
551 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
557 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
558 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
560 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
561 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
562 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
563 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
572 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
573 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
583 * Memory space is mapped 1-1, but I/O space must start from 0.
588 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
590 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
591 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
593 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
594 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
596 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
597 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
598 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
600 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
602 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
604 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
608 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
610 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
611 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
613 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
614 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
616 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
617 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
618 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
620 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
622 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
624 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
638 #define TSEC2_PHY_ADDR 0
645 #define TSEC1_PHYIDX 0
646 #define TSEC2_PHYIDX 0
647 #define TSEC3_PHYIDX 0
659 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
660 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
667 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
676 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
680 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
693 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
703 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
704 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
705 #define CONFIG_ENV_SECT_SIZE 0x10000
708 #define CONFIG_ENV_SIZE 0x2000
709 #define CONFIG_SYS_MMC_ENV_DEV 0
712 #define CONFIG_ENV_SIZE 0x2000
720 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
721 #define CONFIG_ENV_SIZE 0x2000
724 #define CONFIG_ENV_SIZE 0x2000
725 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
756 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
808 "netdev=eth0\0" \
809 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
810 "loadaddr=1000000\0" \
811 "bootfile=uImage\0" \
817 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
818 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
819 "consoledev=ttyS0\0" \
820 "ramdiskaddr=2000000\0" \
821 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
822 "fdtaddr=1e00000\0" \
823 "bdev=sda1\0" \
824 "jffs2nor=mtdblock3\0" \
825 "norbootaddr=ef080000\0" \
826 "norfdtaddr=ef040000\0" \
827 "jffs2nand=mtdblock9\0" \
828 "nandbootaddr=100000\0" \
829 "nandfdtaddr=80000\0" \
830 "ramdisk_size=120000\0" \
831 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
832 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
833 __stringify(__NOR_RST_CMD)"\0" \
834 __stringify(__SPI_RST_CMD)"\0" \
835 __stringify(__SD_RST_CMD)"\0" \
836 __stringify(__NAND_RST_CMD)"\0" \
837 __stringify(__PCIE_RST_CMD)"\0"
852 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
853 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
861 "fatload usb 0:2 $loadaddr $bootfile;" \
862 "fatload usb 0:2 $fdtaddr $fdtfile;" \
863 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
871 "ext2load usb 0:4 $loadaddr $bootfile;" \
872 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
873 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \