119df5959SYoshihiro Shimoda/* SPDX-License-Identifier: GPL-2.0 */ 219df5959SYoshihiro Shimoda/* 319df5959SYoshihiro Shimoda * Device Tree Source for the r8a77990 SoC 419df5959SYoshihiro Shimoda * 519df5959SYoshihiro Shimoda * Copyright (C) 2018 Renesas Electronics Corp. 619df5959SYoshihiro Shimoda */ 719df5959SYoshihiro Shimoda 819df5959SYoshihiro Shimoda#include <dt-bindings/clock/renesas-cpg-mssr.h> 919df5959SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h> 102a1eade8SHiroyuki Yokoyama#include <dt-bindings/power/r8a77990-sysc.h> 1119df5959SYoshihiro Shimoda 1219df5959SYoshihiro Shimoda/ { 1319df5959SYoshihiro Shimoda compatible = "renesas,r8a77990"; 1419df5959SYoshihiro Shimoda #address-cells = <2>; 1519df5959SYoshihiro Shimoda #size-cells = <2>; 1619df5959SYoshihiro Shimoda 1719df5959SYoshihiro Shimoda cpus { 1819df5959SYoshihiro Shimoda #address-cells = <1>; 1919df5959SYoshihiro Shimoda #size-cells = <0>; 2019df5959SYoshihiro Shimoda 2119df5959SYoshihiro Shimoda a53_0: cpu@0 { 2219df5959SYoshihiro Shimoda compatible = "arm,cortex-a53", "arm,armv8"; 23*cbff9f80SMarek Vasut reg = <0>; 2419df5959SYoshihiro Shimoda device_type = "cpu"; 2519df5959SYoshihiro Shimoda power-domains = <&sysc 5>; 2619df5959SYoshihiro Shimoda next-level-cache = <&L2_CA53>; 2719df5959SYoshihiro Shimoda enable-method = "psci"; 2819df5959SYoshihiro Shimoda }; 2919df5959SYoshihiro Shimoda 30*cbff9f80SMarek Vasut a53_1: cpu@1 { 31*cbff9f80SMarek Vasut compatible = "arm,cortex-a53", "arm,armv8"; 32*cbff9f80SMarek Vasut reg = <1>; 33*cbff9f80SMarek Vasut device_type = "cpu"; 34*cbff9f80SMarek Vasut power-domains = <&sysc 6>; 35*cbff9f80SMarek Vasut next-level-cache = <&L2_CA53>; 36*cbff9f80SMarek Vasut enable-method = "psci"; 37*cbff9f80SMarek Vasut }; 38*cbff9f80SMarek Vasut 390bb5d248SMarek Vasut L2_CA53: cache-controller-0 { 4019df5959SYoshihiro Shimoda compatible = "cache"; 4119df5959SYoshihiro Shimoda power-domains = <&sysc 21>; 4219df5959SYoshihiro Shimoda cache-unified; 4319df5959SYoshihiro Shimoda cache-level = <2>; 4419df5959SYoshihiro Shimoda }; 4519df5959SYoshihiro Shimoda }; 4619df5959SYoshihiro Shimoda 4719df5959SYoshihiro Shimoda extal_clk: extal { 4819df5959SYoshihiro Shimoda compatible = "fixed-clock"; 4919df5959SYoshihiro Shimoda #clock-cells = <0>; 5019df5959SYoshihiro Shimoda /* This value must be overridden by the board */ 5119df5959SYoshihiro Shimoda clock-frequency = <0>; 5219df5959SYoshihiro Shimoda }; 5319df5959SYoshihiro Shimoda 540bb5d248SMarek Vasut pmu_a53 { 550bb5d248SMarek Vasut compatible = "arm,cortex-a53-pmu"; 56*cbff9f80SMarek Vasut interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 57*cbff9f80SMarek Vasut <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 58*cbff9f80SMarek Vasut interrupt-affinity = <&a53_0>, <&a53_1>; 590bb5d248SMarek Vasut }; 600bb5d248SMarek Vasut 6119df5959SYoshihiro Shimoda psci { 620bb5d248SMarek Vasut compatible = "arm,psci-1.0", "arm,psci-0.2"; 6319df5959SYoshihiro Shimoda method = "smc"; 6419df5959SYoshihiro Shimoda }; 6519df5959SYoshihiro Shimoda 6619df5959SYoshihiro Shimoda soc: soc { 6719df5959SYoshihiro Shimoda compatible = "simple-bus"; 6819df5959SYoshihiro Shimoda interrupt-parent = <&gic>; 6919df5959SYoshihiro Shimoda #address-cells = <2>; 7019df5959SYoshihiro Shimoda #size-cells = <2>; 7119df5959SYoshihiro Shimoda ranges; 7219df5959SYoshihiro Shimoda 73*cbff9f80SMarek Vasut rwdt: watchdog@e6020000 { 74*cbff9f80SMarek Vasut compatible = "renesas,r8a77990-wdt", 75*cbff9f80SMarek Vasut "renesas,rcar-gen3-wdt"; 76*cbff9f80SMarek Vasut reg = <0 0xe6020000 0 0x0c>; 77*cbff9f80SMarek Vasut clocks = <&cpg CPG_MOD 402>; 78*cbff9f80SMarek Vasut power-domains = <&sysc 32>; 79*cbff9f80SMarek Vasut resets = <&cpg 402>; 80*cbff9f80SMarek Vasut status = "disabled"; 81*cbff9f80SMarek Vasut }; 82*cbff9f80SMarek Vasut 830bb5d248SMarek Vasut gpio0: gpio@e6050000 { 840bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 850bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 860bb5d248SMarek Vasut reg = <0 0xe6050000 0 0x50>; 870bb5d248SMarek Vasut interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 880bb5d248SMarek Vasut #gpio-cells = <2>; 890bb5d248SMarek Vasut gpio-controller; 900bb5d248SMarek Vasut gpio-ranges = <&pfc 0 0 18>; 910bb5d248SMarek Vasut #interrupt-cells = <2>; 920bb5d248SMarek Vasut interrupt-controller; 930bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 912>; 940bb5d248SMarek Vasut power-domains = <&sysc 32>; 950bb5d248SMarek Vasut resets = <&cpg 912>; 960bb5d248SMarek Vasut }; 970bb5d248SMarek Vasut 980bb5d248SMarek Vasut gpio1: gpio@e6051000 { 990bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 1000bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 1010bb5d248SMarek Vasut reg = <0 0xe6051000 0 0x50>; 1020bb5d248SMarek Vasut interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1030bb5d248SMarek Vasut #gpio-cells = <2>; 1040bb5d248SMarek Vasut gpio-controller; 1050bb5d248SMarek Vasut gpio-ranges = <&pfc 0 32 23>; 1060bb5d248SMarek Vasut #interrupt-cells = <2>; 1070bb5d248SMarek Vasut interrupt-controller; 1080bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 911>; 1090bb5d248SMarek Vasut power-domains = <&sysc 32>; 1100bb5d248SMarek Vasut resets = <&cpg 911>; 1110bb5d248SMarek Vasut }; 1120bb5d248SMarek Vasut 1130bb5d248SMarek Vasut gpio2: gpio@e6052000 { 1140bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 1150bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 1160bb5d248SMarek Vasut reg = <0 0xe6052000 0 0x50>; 1170bb5d248SMarek Vasut interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1180bb5d248SMarek Vasut #gpio-cells = <2>; 1190bb5d248SMarek Vasut gpio-controller; 1200bb5d248SMarek Vasut gpio-ranges = <&pfc 0 64 26>; 1210bb5d248SMarek Vasut #interrupt-cells = <2>; 1220bb5d248SMarek Vasut interrupt-controller; 1230bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 910>; 1240bb5d248SMarek Vasut power-domains = <&sysc 32>; 1250bb5d248SMarek Vasut resets = <&cpg 910>; 1260bb5d248SMarek Vasut }; 1270bb5d248SMarek Vasut 1280bb5d248SMarek Vasut gpio3: gpio@e6053000 { 1290bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 1300bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 1310bb5d248SMarek Vasut reg = <0 0xe6053000 0 0x50>; 1320bb5d248SMarek Vasut interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1330bb5d248SMarek Vasut #gpio-cells = <2>; 1340bb5d248SMarek Vasut gpio-controller; 1350bb5d248SMarek Vasut gpio-ranges = <&pfc 0 96 16>; 1360bb5d248SMarek Vasut #interrupt-cells = <2>; 1370bb5d248SMarek Vasut interrupt-controller; 1380bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 909>; 1390bb5d248SMarek Vasut power-domains = <&sysc 32>; 1400bb5d248SMarek Vasut resets = <&cpg 909>; 1410bb5d248SMarek Vasut }; 1420bb5d248SMarek Vasut 1430bb5d248SMarek Vasut gpio4: gpio@e6054000 { 1440bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 1450bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 1460bb5d248SMarek Vasut reg = <0 0xe6054000 0 0x50>; 1470bb5d248SMarek Vasut interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1480bb5d248SMarek Vasut #gpio-cells = <2>; 1490bb5d248SMarek Vasut gpio-controller; 1500bb5d248SMarek Vasut gpio-ranges = <&pfc 0 128 11>; 1510bb5d248SMarek Vasut #interrupt-cells = <2>; 1520bb5d248SMarek Vasut interrupt-controller; 1530bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 908>; 1540bb5d248SMarek Vasut power-domains = <&sysc 32>; 1550bb5d248SMarek Vasut resets = <&cpg 908>; 1560bb5d248SMarek Vasut }; 1570bb5d248SMarek Vasut 1580bb5d248SMarek Vasut gpio5: gpio@e6055000 { 1590bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 1600bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 1610bb5d248SMarek Vasut reg = <0 0xe6055000 0 0x50>; 1620bb5d248SMarek Vasut interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1630bb5d248SMarek Vasut #gpio-cells = <2>; 1640bb5d248SMarek Vasut gpio-controller; 1650bb5d248SMarek Vasut gpio-ranges = <&pfc 0 160 20>; 1660bb5d248SMarek Vasut #interrupt-cells = <2>; 1670bb5d248SMarek Vasut interrupt-controller; 1680bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 907>; 1690bb5d248SMarek Vasut power-domains = <&sysc 32>; 1700bb5d248SMarek Vasut resets = <&cpg 907>; 1710bb5d248SMarek Vasut }; 1720bb5d248SMarek Vasut 1730bb5d248SMarek Vasut gpio6: gpio@e6055400 { 1740bb5d248SMarek Vasut compatible = "renesas,gpio-r8a77990", 1750bb5d248SMarek Vasut "renesas,rcar-gen3-gpio"; 1760bb5d248SMarek Vasut reg = <0 0xe6055400 0 0x50>; 1770bb5d248SMarek Vasut interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1780bb5d248SMarek Vasut #gpio-cells = <2>; 1790bb5d248SMarek Vasut gpio-controller; 1800bb5d248SMarek Vasut gpio-ranges = <&pfc 0 192 18>; 1810bb5d248SMarek Vasut #interrupt-cells = <2>; 1820bb5d248SMarek Vasut interrupt-controller; 1830bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 906>; 1840bb5d248SMarek Vasut power-domains = <&sysc 32>; 1850bb5d248SMarek Vasut resets = <&cpg 906>; 1860bb5d248SMarek Vasut }; 1870bb5d248SMarek Vasut 1880bb5d248SMarek Vasut pfc: pin-controller@e6060000 { 1890bb5d248SMarek Vasut compatible = "renesas,pfc-r8a77990"; 1900bb5d248SMarek Vasut reg = <0 0xe6060000 0 0x508>; 1910bb5d248SMarek Vasut }; 1920bb5d248SMarek Vasut 1930bb5d248SMarek Vasut cpg: clock-controller@e6150000 { 1940bb5d248SMarek Vasut compatible = "renesas,r8a77990-cpg-mssr"; 1950bb5d248SMarek Vasut reg = <0 0xe6150000 0 0x1000>; 1960bb5d248SMarek Vasut clocks = <&extal_clk>; 1970bb5d248SMarek Vasut clock-names = "extal"; 1980bb5d248SMarek Vasut #clock-cells = <2>; 1990bb5d248SMarek Vasut #power-domain-cells = <0>; 2000bb5d248SMarek Vasut #reset-cells = <1>; 2010bb5d248SMarek Vasut }; 2020bb5d248SMarek Vasut 2030bb5d248SMarek Vasut rst: reset-controller@e6160000 { 2040bb5d248SMarek Vasut compatible = "renesas,r8a77990-rst"; 2050bb5d248SMarek Vasut reg = <0 0xe6160000 0 0x0200>; 2060bb5d248SMarek Vasut }; 2070bb5d248SMarek Vasut 2080bb5d248SMarek Vasut sysc: system-controller@e6180000 { 2090bb5d248SMarek Vasut compatible = "renesas,r8a77990-sysc"; 2100bb5d248SMarek Vasut reg = <0 0xe6180000 0 0x0400>; 2110bb5d248SMarek Vasut #power-domain-cells = <1>; 2120bb5d248SMarek Vasut }; 2130bb5d248SMarek Vasut 214*cbff9f80SMarek Vasut ipmmu_ds0: mmu@e6740000 { 215*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 216*cbff9f80SMarek Vasut reg = <0 0xe6740000 0 0x1000>; 217*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 0>; 218*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 219*cbff9f80SMarek Vasut #iommu-cells = <1>; 220*cbff9f80SMarek Vasut }; 221*cbff9f80SMarek Vasut 222*cbff9f80SMarek Vasut ipmmu_ds1: mmu@e7740000 { 223*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 224*cbff9f80SMarek Vasut reg = <0 0xe7740000 0 0x1000>; 225*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 1>; 226*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 227*cbff9f80SMarek Vasut #iommu-cells = <1>; 228*cbff9f80SMarek Vasut }; 229*cbff9f80SMarek Vasut 230*cbff9f80SMarek Vasut ipmmu_hc: mmu@e6570000 { 231*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 232*cbff9f80SMarek Vasut reg = <0 0xe6570000 0 0x1000>; 233*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 2>; 234*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 235*cbff9f80SMarek Vasut #iommu-cells = <1>; 236*cbff9f80SMarek Vasut }; 237*cbff9f80SMarek Vasut 238*cbff9f80SMarek Vasut ipmmu_mm: mmu@e67b0000 { 239*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 240*cbff9f80SMarek Vasut reg = <0 0xe67b0000 0 0x1000>; 241*cbff9f80SMarek Vasut interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 242*cbff9f80SMarek Vasut <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 243*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 244*cbff9f80SMarek Vasut #iommu-cells = <1>; 245*cbff9f80SMarek Vasut }; 246*cbff9f80SMarek Vasut 247*cbff9f80SMarek Vasut ipmmu_mp: mmu@ec670000 { 248*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 249*cbff9f80SMarek Vasut reg = <0 0xec670000 0 0x1000>; 250*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 4>; 251*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 252*cbff9f80SMarek Vasut #iommu-cells = <1>; 253*cbff9f80SMarek Vasut }; 254*cbff9f80SMarek Vasut 255*cbff9f80SMarek Vasut ipmmu_pv0: mmu@fd800000 { 256*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 257*cbff9f80SMarek Vasut reg = <0 0xfd800000 0 0x1000>; 258*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 6>; 259*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 260*cbff9f80SMarek Vasut #iommu-cells = <1>; 261*cbff9f80SMarek Vasut }; 262*cbff9f80SMarek Vasut 263*cbff9f80SMarek Vasut ipmmu_rt: mmu@ffc80000 { 264*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 265*cbff9f80SMarek Vasut reg = <0 0xffc80000 0 0x1000>; 266*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 10>; 267*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 268*cbff9f80SMarek Vasut #iommu-cells = <1>; 269*cbff9f80SMarek Vasut }; 270*cbff9f80SMarek Vasut 271*cbff9f80SMarek Vasut ipmmu_vc0: mmu@fe6b0000 { 272*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 273*cbff9f80SMarek Vasut reg = <0 0xfe6b0000 0 0x1000>; 274*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 12>; 275*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_A3VC>; 276*cbff9f80SMarek Vasut #iommu-cells = <1>; 277*cbff9f80SMarek Vasut }; 278*cbff9f80SMarek Vasut 279*cbff9f80SMarek Vasut ipmmu_vi0: mmu@febd0000 { 280*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 281*cbff9f80SMarek Vasut reg = <0 0xfebd0000 0 0x1000>; 282*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 14>; 283*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 284*cbff9f80SMarek Vasut #iommu-cells = <1>; 285*cbff9f80SMarek Vasut }; 286*cbff9f80SMarek Vasut 287*cbff9f80SMarek Vasut ipmmu_vp0: mmu@fe990000 { 288*cbff9f80SMarek Vasut compatible = "renesas,ipmmu-r8a77990"; 289*cbff9f80SMarek Vasut reg = <0 0xfe990000 0 0x1000>; 290*cbff9f80SMarek Vasut renesas,ipmmu-main = <&ipmmu_mm 16>; 291*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 292*cbff9f80SMarek Vasut #iommu-cells = <1>; 293*cbff9f80SMarek Vasut }; 294*cbff9f80SMarek Vasut 2950bb5d248SMarek Vasut avb: ethernet@e6800000 { 2960bb5d248SMarek Vasut compatible = "renesas,etheravb-r8a77990", 2970bb5d248SMarek Vasut "renesas,etheravb-rcar-gen3"; 298*cbff9f80SMarek Vasut reg = <0 0xe6800000 0 0x800>; 2990bb5d248SMarek Vasut interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 3000bb5d248SMarek Vasut <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 3010bb5d248SMarek Vasut <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 3020bb5d248SMarek Vasut <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 3030bb5d248SMarek Vasut <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 3040bb5d248SMarek Vasut <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 3050bb5d248SMarek Vasut <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 3060bb5d248SMarek Vasut <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 3070bb5d248SMarek Vasut <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 3080bb5d248SMarek Vasut <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 3090bb5d248SMarek Vasut <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 3100bb5d248SMarek Vasut <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 3110bb5d248SMarek Vasut <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 3120bb5d248SMarek Vasut <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 3130bb5d248SMarek Vasut <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 3140bb5d248SMarek Vasut <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 3150bb5d248SMarek Vasut <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 3160bb5d248SMarek Vasut <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 3170bb5d248SMarek Vasut <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 3180bb5d248SMarek Vasut <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 3190bb5d248SMarek Vasut <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 3200bb5d248SMarek Vasut <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 3210bb5d248SMarek Vasut <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 3220bb5d248SMarek Vasut <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 3230bb5d248SMarek Vasut <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 3240bb5d248SMarek Vasut interrupt-names = "ch0", "ch1", "ch2", "ch3", 3250bb5d248SMarek Vasut "ch4", "ch5", "ch6", "ch7", 3260bb5d248SMarek Vasut "ch8", "ch9", "ch10", "ch11", 3270bb5d248SMarek Vasut "ch12", "ch13", "ch14", "ch15", 3280bb5d248SMarek Vasut "ch16", "ch17", "ch18", "ch19", 3290bb5d248SMarek Vasut "ch20", "ch21", "ch22", "ch23", 3300bb5d248SMarek Vasut "ch24"; 3310bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 812>; 3320bb5d248SMarek Vasut power-domains = <&sysc 32>; 3330bb5d248SMarek Vasut resets = <&cpg 812>; 3340bb5d248SMarek Vasut phy-mode = "rgmii"; 3350bb5d248SMarek Vasut #address-cells = <1>; 3360bb5d248SMarek Vasut #size-cells = <0>; 3370bb5d248SMarek Vasut status = "disabled"; 3380bb5d248SMarek Vasut }; 3390bb5d248SMarek Vasut 3400bb5d248SMarek Vasut scif2: serial@e6e88000 { 3410bb5d248SMarek Vasut compatible = "renesas,scif-r8a77990", 3420bb5d248SMarek Vasut "renesas,rcar-gen3-scif", "renesas,scif"; 3430bb5d248SMarek Vasut reg = <0 0xe6e88000 0 64>; 3440bb5d248SMarek Vasut interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3450bb5d248SMarek Vasut clocks = <&cpg CPG_MOD 310>; 3460bb5d248SMarek Vasut clock-names = "fck"; 3470bb5d248SMarek Vasut power-domains = <&sysc 32>; 3480bb5d248SMarek Vasut resets = <&cpg 310>; 3490bb5d248SMarek Vasut status = "disabled"; 3500bb5d248SMarek Vasut }; 3510bb5d248SMarek Vasut 352*cbff9f80SMarek Vasut xhci0: usb@ee000000 { 353*cbff9f80SMarek Vasut compatible = "renesas,xhci-r8a77990", 354*cbff9f80SMarek Vasut "renesas,rcar-gen3-xhci"; 355*cbff9f80SMarek Vasut reg = <0 0xee000000 0 0xc00>; 356*cbff9f80SMarek Vasut interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 357*cbff9f80SMarek Vasut clocks = <&cpg CPG_MOD 328>; 358*cbff9f80SMarek Vasut power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 359*cbff9f80SMarek Vasut resets = <&cpg 328>; 360*cbff9f80SMarek Vasut status = "disabled"; 361*cbff9f80SMarek Vasut }; 362*cbff9f80SMarek Vasut 363*cbff9f80SMarek Vasut ohci0: usb@ee080000 { 364*cbff9f80SMarek Vasut compatible = "generic-ohci"; 365*cbff9f80SMarek Vasut reg = <0 0xee080000 0 0x100>; 366*cbff9f80SMarek Vasut interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 367*cbff9f80SMarek Vasut clocks = <&cpg CPG_MOD 703>; 368*cbff9f80SMarek Vasut phys = <&usb2_phy0>; 369*cbff9f80SMarek Vasut phy-names = "usb"; 370*cbff9f80SMarek Vasut power-domains = <&sysc 32>; 371*cbff9f80SMarek Vasut resets = <&cpg 703>; 372*cbff9f80SMarek Vasut status = "disabled"; 373*cbff9f80SMarek Vasut }; 374*cbff9f80SMarek Vasut 375*cbff9f80SMarek Vasut ehci0: usb@ee080100 { 376*cbff9f80SMarek Vasut compatible = "generic-ehci"; 377*cbff9f80SMarek Vasut reg = <0 0xee080100 0 0x100>; 378*cbff9f80SMarek Vasut interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 379*cbff9f80SMarek Vasut clocks = <&cpg CPG_MOD 703>; 380*cbff9f80SMarek Vasut phys = <&usb2_phy0>; 381*cbff9f80SMarek Vasut phy-names = "usb"; 382*cbff9f80SMarek Vasut companion = <&ohci0>; 383*cbff9f80SMarek Vasut power-domains = <&sysc 32>; 384*cbff9f80SMarek Vasut resets = <&cpg 703>; 385*cbff9f80SMarek Vasut status = "disabled"; 386*cbff9f80SMarek Vasut }; 387*cbff9f80SMarek Vasut 388*cbff9f80SMarek Vasut usb2_phy0: usb-phy@ee080200 { 389*cbff9f80SMarek Vasut compatible = "renesas,usb2-phy-r8a77990", 390*cbff9f80SMarek Vasut "renesas,rcar-gen3-usb2-phy"; 391*cbff9f80SMarek Vasut reg = <0 0xee080200 0 0x700>; 392*cbff9f80SMarek Vasut interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 393*cbff9f80SMarek Vasut clocks = <&cpg CPG_MOD 703>; 394*cbff9f80SMarek Vasut power-domains = <&sysc 32>; 395*cbff9f80SMarek Vasut resets = <&cpg 703>; 396*cbff9f80SMarek Vasut #phy-cells = <0>; 397*cbff9f80SMarek Vasut status = "disabled"; 398*cbff9f80SMarek Vasut }; 399*cbff9f80SMarek Vasut 40019df5959SYoshihiro Shimoda gic: interrupt-controller@f1010000 { 40119df5959SYoshihiro Shimoda compatible = "arm,gic-400"; 40219df5959SYoshihiro Shimoda #interrupt-cells = <3>; 40319df5959SYoshihiro Shimoda #address-cells = <0>; 40419df5959SYoshihiro Shimoda interrupt-controller; 40519df5959SYoshihiro Shimoda reg = <0x0 0xf1010000 0 0x1000>, 40619df5959SYoshihiro Shimoda <0x0 0xf1020000 0 0x20000>, 40719df5959SYoshihiro Shimoda <0x0 0xf1040000 0 0x20000>, 40819df5959SYoshihiro Shimoda <0x0 0xf1060000 0 0x20000>; 40919df5959SYoshihiro Shimoda interrupts = <GIC_PPI 9 410*cbff9f80SMarek Vasut (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 41119df5959SYoshihiro Shimoda clocks = <&cpg CPG_MOD 408>; 41219df5959SYoshihiro Shimoda clock-names = "clk"; 41319df5959SYoshihiro Shimoda power-domains = <&sysc 32>; 41419df5959SYoshihiro Shimoda resets = <&cpg 408>; 41519df5959SYoshihiro Shimoda }; 41619df5959SYoshihiro Shimoda 41719df5959SYoshihiro Shimoda prr: chipid@fff00044 { 41819df5959SYoshihiro Shimoda compatible = "renesas,prr"; 41919df5959SYoshihiro Shimoda reg = <0 0xfff00044 0 4>; 42019df5959SYoshihiro Shimoda }; 42119df5959SYoshihiro Shimoda }; 42219df5959SYoshihiro Shimoda 4230bb5d248SMarek Vasut timer { 4240bb5d248SMarek Vasut compatible = "arm,armv8-timer"; 425*cbff9f80SMarek Vasut interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 426*cbff9f80SMarek Vasut <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 427*cbff9f80SMarek Vasut <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 428*cbff9f80SMarek Vasut <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 42919df5959SYoshihiro Shimoda }; 43019df5959SYoshihiro Shimoda}; 431