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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
H A Dintel,lgm-ebunand.yaml48 minimum: 0
70 reg = <0xe0f00000 0x100>,
71 <0xe1000000 0x300>,
72 <0xe1400000 0x8000>,
73 <0xe1c00000 0x1000>,
74 <0x17400000 0x4>,
75 <0x17c00000 0x4>;
82 #size-cells = <0>;
84 nand@0 {
85 reg = <0>;
/openbmc/linux/tools/testing/selftests/arm64/fp/
H A Dsme-inst.h12 .inst 0x4bf5800 \
33 .macro _ldr_za nw, nxbase, offset=0
34 .inst 0xe1000000 \
44 .macro _str_za nw, nxbase, offset=0
45 .inst 0xe1200000 \
57 .inst 0xe11f8000 \
58 | (((\nx) & 0x1f) << 5)
67 .inst 0xe13f8000 \
68 | (((\nx) & 0x1f) << 5)
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
16 #define DMA_BASE 0x31000000 /* DMA controller registers base */
17 #define USB_BASE 0x31020000 /* USB registers base */
18 #define LCD_BASE 0x31040000 /* LCD registers base */
19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
23 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
/openbmc/linux/include/video/
H A Dcvisionppc.h27 #define CSPPC_PCI_BRIDGE 0xfffe0000
28 #define CSPPC_BRIDGE_ENDIAN 0x0000
29 #define CSPPC_BRIDGE_INT 0x0010
31 #define CVPPC_PCI_CONFIG 0xfffc0000
32 #define CVPPC_ROM_ADDRESS 0xe2000001
33 #define CVPPC_REGS_REGION 0xef000000
34 #define CVPPC_FB_APERTURE_ONE 0xe0000000
35 #define CVPPC_FB_APERTURE_TWO 0xe1000000
36 #define CVPPC_FB_SIZE 0x00800000
37 #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
[all …]
/openbmc/u-boot/include/configs/
H A Dids8313.h29 #define CONFIG_SYS_IMMR 0xF0000000
31 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
32 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
39 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
55 #define CONFIG_SYS_SICRH 0x00000000
60 #define CONFIG_SYS_HID0_INIT 0x000000000
65 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
71 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
73 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
[all …]
H A DMPC8544DS.h28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
41 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
42 #define CONFIG_SYS_MEMTEST_END 0x00400000
44 #define CONFIG_SYS_CCSRBAR 0xe0000000
52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
62 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
74 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
76 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
78 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
[all …]
H A DMPC8610HPCD.h14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
26 #define CONFIG_SYS_DIAG_ADDR 0xff800000
33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
53 #define L2_INIT 0
54 #define L2_ENABLE (L2CR_L2E |0x00100000 )
57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END 0x00400000
67 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
[all …]
H A Dcyrus.h27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
53 #define CONFIG_SYS_MMC_ENV_DEV 0
54 #define CONFIG_ENV_SIZE 0x2000
68 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
81 #define CONFIG_SYS_MEMTEST_END 0x00400000
88 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
96 #define CONFIG_SYS_DCSRBAR 0xf0000000
97 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/openbmc/u-boot/arch/arm/mach-zynq/include/mach/
H A Dhardware.h9 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
10 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
11 #define ZYNQ_SCU_BASEADDR 0xF8F00000
12 #define ZYNQ_QSPI_BASEADDR 0xE000D000
13 #define ZYNQ_SMC_BASEADDR 0xE000E000
14 #define ZYNQ_NAND_BASEADDR 0xE1000000
15 #define ZYNQ_DDRC_BASEADDR 0xF8006000
16 #define ZYNQ_EFUSE_BASEADDR 0xF800D000
17 #define ZYNQ_USB_BASEADDR0 0xE0002000
18 #define ZYNQ_USB_BASEADDR1 0xE0003000
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dhardware.h53 ? OMAP_CS3_PHYS : 0; in omap_cs0m_phys()
59 ? 0 : OMAP_CS3_PHYS; in omap_cs3_phys()
64 #define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */
82 #define OMAP_MPU_TIMER1_BASE (0xfffec500)
83 #define OMAP_MPU_TIMER2_BASE (0xfffec600)
84 #define OMAP_MPU_TIMER3_BASE (0xfffec700)
88 #define MPU_TIMER_ST (1 << 0)
97 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
98 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
99 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
[all …]
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c19 #define DEV_CS0_BASE 0xe0000000
20 #define DEV_CS1_BASE 0xe1000000
21 #define DEV_CS2_BASE 0xe2000000
22 #define DEV_CS3_BASE 0xe3000000
26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8350-sony-xperia-sagami.dtsi33 reg = <0 0xe1000000 0 0x2300000>;
53 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>;
94 reg = <0 0xe1000000 0 0x2300000>;
100 reg = <0 0xffc00000 0 0x100000>;
101 console-size = <0x40000>;
102 record-size = <0x1000>;
124 regulators-0 {
496 reg = <0x40>;
511 reg = <0x41>;
592 power-source = <0>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dfpsimdmacros.h12 stp q0, q1, [\state, #16 * 0]
48 ldp q0, q1, [\state, #16 * 0]
73 .if (\nr) < 0 || (\nr) > 30
79 .if (\znr) < 0 || (\znr) > 31
85 .if (\pnr) < 0 || (\pnr) > 15
106 .macro _sve_str_v nz, nxbase, offset=0
109 _check_num (\offset), -0x100, 0xff
110 .inst 0xe5804000 \
114 | (((\offset) & 0x1f8) << 13)
118 .macro _sve_ldr_v nz, nxbase, offset=0
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/openbmc/linux/tools/testing/selftests/arm64/abi/
H A Dsyscall-abi-asm.S11 // x0: SVE VL, 0 for FP only
33 .macro _ldr_za nw, nxbase, offset=0
34 .inst 0xe1000000 \
44 .macro _str_za nw, nxbase, offset=0
45 .inst 0xe1200000 \
57 .inst 0xe11f8000 \
58 | (((\nx) & 0x1f) << 5)
67 .inst 0xe13f8000 \
68 | (((\nx) & 0x1f) << 5)
91 mov w12, #0
[all …]
/openbmc/qemu/include/hw/arm/
H A Domap.h28 # define OMAP_EMIFS_BASE 0x00000000
29 # define OMAP_CS0_BASE 0x00000000
30 # define OMAP_CS1_BASE 0x04000000
31 # define OMAP_CS2_BASE 0x08000000
32 # define OMAP_CS3_BASE 0x0c000000
33 # define OMAP_EMIFF_BASE 0x10000000
34 # define OMAP_IMIF_BASE 0x20000000
35 # define OMAP_LOCALBUS_BASE 0x30000000
36 # define OMAP_MPUI_BASE 0xe1000000
38 # define OMAP730_SRAM_SIZE 0x00032000
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/qemu/docs/devel/
H A Dmemory.rst227 For example, suppose we have a container A of size 0x8000 with two subregions
228 B and C. B is a container mapped at 0x2000, size 0x4000, priority 2; C is
229 an MMIO region mapped at 0x0, size 0x6000, priority 1. B currently has two
230 of its own subregions: D of size 0x1000 at offset 0 and E of size 0x1000 at
231 offset 0x2000. As a diagram::
233 0 1000 2000 3000 4000 5000 6000 7000 8000
295 system_memory: container@0-2^48-1
297 +---- lomem: alias@0-0xdfffffff ---> #ram (0-0xdfffffff)
299 +---- himem: alias@0x100000000-0x11fffffff ---> #ram (0xe0000000-0xffffffff)
301 +---- vga-window: alias@0xa0000-0xbffff ---> #pci (0xa0000-0xbffff)
[all …]
/openbmc/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/openbmc/u-boot/include/
H A Dsym53c8xx.h14 #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
16 #define SCNTL1 0x01 /* no reset */
17 #define ISCON 0x10 /* connected to scsi */
18 #define CRST 0x08 /* force reset */
19 #define IARB 0x02 /* immediate arbitration */
21 #define SCNTL2 0x02 /* no disconnect expected */
22 #define SDU 0x80 /* cmd: disconnect will raise error */
23 #define CHM 0x40 /* sta: chained mode */
24 #define WSS 0x08 /* sta: wide scsi send [W]*/
25 #define WSR 0x01 /* sta: wide scsi received [W]*/
[all …]

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