10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * Texas Instruments OMAP processors. 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> 50d09e41aSPaolo Bonzini * 60d09e41aSPaolo Bonzini * This program is free software; you can redistribute it and/or 70d09e41aSPaolo Bonzini * modify it under the terms of the GNU General Public License as 80d09e41aSPaolo Bonzini * published by the Free Software Foundation; either version 2 or 90d09e41aSPaolo Bonzini * (at your option) version 3 of the License. 100d09e41aSPaolo Bonzini * 110d09e41aSPaolo Bonzini * This program is distributed in the hope that it will be useful, 120d09e41aSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 130d09e41aSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 140d09e41aSPaolo Bonzini * GNU General Public License for more details. 150d09e41aSPaolo Bonzini * 160d09e41aSPaolo Bonzini * You should have received a copy of the GNU General Public License along 170d09e41aSPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 180d09e41aSPaolo Bonzini */ 190553d895SMarkus Armbruster 200553d895SMarkus Armbruster #ifndef HW_ARM_OMAP_H 210553d895SMarkus Armbruster #define HW_ARM_OMAP_H 220553d895SMarkus Armbruster 230d09e41aSPaolo Bonzini #include "exec/memory.h" 24a331dd02SPhilippe Mathieu-Daudé #include "hw/input/tsc2xxx.h" 25fcf5ef2aSThomas Huth #include "target/arm/cpu-qom.h" 2684b335c6SPhilippe Mathieu-Daudé #include "qemu/log.h" 27db1015e9SEduardo Habkost #include "qom/object.h" 280d09e41aSPaolo Bonzini 290d09e41aSPaolo Bonzini # define OMAP_EMIFS_BASE 0x00000000 300d09e41aSPaolo Bonzini # define OMAP2_Q0_BASE 0x00000000 310d09e41aSPaolo Bonzini # define OMAP_CS0_BASE 0x00000000 320d09e41aSPaolo Bonzini # define OMAP_CS1_BASE 0x04000000 330d09e41aSPaolo Bonzini # define OMAP_CS2_BASE 0x08000000 340d09e41aSPaolo Bonzini # define OMAP_CS3_BASE 0x0c000000 350d09e41aSPaolo Bonzini # define OMAP_EMIFF_BASE 0x10000000 360d09e41aSPaolo Bonzini # define OMAP_IMIF_BASE 0x20000000 370d09e41aSPaolo Bonzini # define OMAP_LOCALBUS_BASE 0x30000000 380d09e41aSPaolo Bonzini # define OMAP2_Q1_BASE 0x40000000 390d09e41aSPaolo Bonzini # define OMAP2_L4_BASE 0x48000000 400d09e41aSPaolo Bonzini # define OMAP2_SRAM_BASE 0x40200000 410d09e41aSPaolo Bonzini # define OMAP2_L3_BASE 0x68000000 420d09e41aSPaolo Bonzini # define OMAP2_Q2_BASE 0x80000000 430d09e41aSPaolo Bonzini # define OMAP2_Q3_BASE 0xc0000000 440d09e41aSPaolo Bonzini # define OMAP_MPUI_BASE 0xe1000000 450d09e41aSPaolo Bonzini 460d09e41aSPaolo Bonzini # define OMAP730_SRAM_SIZE 0x00032000 470d09e41aSPaolo Bonzini # define OMAP15XX_SRAM_SIZE 0x00030000 480d09e41aSPaolo Bonzini # define OMAP16XX_SRAM_SIZE 0x00004000 490d09e41aSPaolo Bonzini # define OMAP1611_SRAM_SIZE 0x0003e800 500d09e41aSPaolo Bonzini # define OMAP242X_SRAM_SIZE 0x000a0000 510d09e41aSPaolo Bonzini # define OMAP243X_SRAM_SIZE 0x00010000 520d09e41aSPaolo Bonzini # define OMAP_CS0_SIZE 0x04000000 530d09e41aSPaolo Bonzini # define OMAP_CS1_SIZE 0x04000000 540d09e41aSPaolo Bonzini # define OMAP_CS2_SIZE 0x04000000 550d09e41aSPaolo Bonzini # define OMAP_CS3_SIZE 0x04000000 560d09e41aSPaolo Bonzini 570d09e41aSPaolo Bonzini /* omap_clk.c */ 580d09e41aSPaolo Bonzini struct omap_mpu_state_s; 590d09e41aSPaolo Bonzini typedef struct clk *omap_clk; 600d09e41aSPaolo Bonzini omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); 610d09e41aSPaolo Bonzini void omap_clk_init(struct omap_mpu_state_s *mpu); 620d09e41aSPaolo Bonzini void omap_clk_adduser(struct clk *clk, qemu_irq user); 630d09e41aSPaolo Bonzini void omap_clk_get(omap_clk clk); 640d09e41aSPaolo Bonzini void omap_clk_put(omap_clk clk); 650d09e41aSPaolo Bonzini void omap_clk_onoff(omap_clk clk, int on); 660d09e41aSPaolo Bonzini void omap_clk_canidle(omap_clk clk, int can); 670d09e41aSPaolo Bonzini void omap_clk_setrate(omap_clk clk, int divide, int multiply); 680d09e41aSPaolo Bonzini int64_t omap_clk_getrate(omap_clk clk); 690d09e41aSPaolo Bonzini void omap_clk_reparent(omap_clk clk, omap_clk parent); 700d09e41aSPaolo Bonzini 71bab592a2SMarc-André Lureau /* omap_intc.c */ 72bab592a2SMarc-André Lureau #define TYPE_OMAP_INTC "common-omap-intc" 73bded15c9SPhilippe Mathieu-Daudé typedef struct OMAPIntcState OMAPIntcState; 74bded15c9SPhilippe Mathieu-Daudé DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) 75bab592a2SMarc-André Lureau 76bab592a2SMarc-André Lureau 77bab592a2SMarc-André Lureau /* 78bab592a2SMarc-André Lureau * TODO: Ideally we should have a clock framework that 79bab592a2SMarc-André Lureau * let us wire these clocks up with QOM properties or links. 80ba2aba83SMarc-André Lureau * 81ba2aba83SMarc-André Lureau * qdev should support a generic means of defining a 'port' with 82ba2aba83SMarc-André Lureau * an arbitrary interface for connecting two devices. Then we 83ba2aba83SMarc-André Lureau * could reframe the omap clock API in terms of clock ports, 84ba2aba83SMarc-André Lureau * and get some type safety. For now the best qdev provides is 85ba2aba83SMarc-André Lureau * passing an arbitrary pointer. 86ba2aba83SMarc-André Lureau * (It's not possible to pass in the string which is the clock 87ba2aba83SMarc-André Lureau * name, because this device does not have the necessary information 88ba2aba83SMarc-André Lureau * (ie the struct omap_mpu_state_s*) to do the clockname to pointer 89ba2aba83SMarc-André Lureau * translation.) 90bab592a2SMarc-André Lureau */ 91bded15c9SPhilippe Mathieu-Daudé void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); 92bded15c9SPhilippe Mathieu-Daudé void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); 93bab592a2SMarc-André Lureau 940fd20c53SMarc-André Lureau /* omap_i2c.c */ 950fd20c53SMarc-André Lureau #define TYPE_OMAP_I2C "omap_i2c" 968063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) 970fd20c53SMarc-André Lureau 980fd20c53SMarc-André Lureau 99ba2aba83SMarc-André Lureau /* TODO: clock framework (see above) */ 1000fd20c53SMarc-André Lureau void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); 1010fd20c53SMarc-André Lureau void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); 1020fd20c53SMarc-André Lureau 103ba2aba83SMarc-André Lureau /* omap_gpio.c */ 104ba2aba83SMarc-André Lureau #define TYPE_OMAP1_GPIO "omap-gpio" 105bbcdf7d0SPhilippe Mathieu-Daudé typedef struct Omap1GpioState Omap1GpioState; 106bbcdf7d0SPhilippe Mathieu-Daudé DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, 1078110fa1dSEduardo Habkost TYPE_OMAP1_GPIO) 108ba2aba83SMarc-André Lureau 109ba2aba83SMarc-André Lureau #define TYPE_OMAP2_GPIO "omap2-gpio" 110bb3d1c61SPhilippe Mathieu-Daudé typedef struct Omap2GpioState Omap2GpioState; 111bb3d1c61SPhilippe Mathieu-Daudé DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO, 1128110fa1dSEduardo Habkost TYPE_OMAP2_GPIO) 113ba2aba83SMarc-André Lureau 114ba2aba83SMarc-André Lureau /* TODO: clock framework (see above) */ 115bbcdf7d0SPhilippe Mathieu-Daudé void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); 116ba2aba83SMarc-André Lureau 117bb3d1c61SPhilippe Mathieu-Daudé void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk); 118bb3d1c61SPhilippe Mathieu-Daudé void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk); 119ba2aba83SMarc-André Lureau 1200d09e41aSPaolo Bonzini /* OMAP2 l4 Interconnect */ 1210d09e41aSPaolo Bonzini struct omap_l4_s; 1220d09e41aSPaolo Bonzini struct omap_l4_region_s { 1230d09e41aSPaolo Bonzini hwaddr offset; 1240d09e41aSPaolo Bonzini size_t size; 1250d09e41aSPaolo Bonzini int access; 1260d09e41aSPaolo Bonzini }; 1270d09e41aSPaolo Bonzini struct omap_l4_agent_info_s { 1280d09e41aSPaolo Bonzini int ta; 1290d09e41aSPaolo Bonzini int region; 1300d09e41aSPaolo Bonzini int regions; 1310d09e41aSPaolo Bonzini int ta_region; 1320d09e41aSPaolo Bonzini }; 1330d09e41aSPaolo Bonzini struct omap_target_agent_s { 1340d09e41aSPaolo Bonzini MemoryRegion iomem; 1350d09e41aSPaolo Bonzini struct omap_l4_s *bus; 1360d09e41aSPaolo Bonzini int regions; 1370d09e41aSPaolo Bonzini const struct omap_l4_region_s *start; 1380d09e41aSPaolo Bonzini hwaddr base; 1390d09e41aSPaolo Bonzini uint32_t component; 1400d09e41aSPaolo Bonzini uint32_t control; 1410d09e41aSPaolo Bonzini uint32_t status; 1420d09e41aSPaolo Bonzini }; 1430d09e41aSPaolo Bonzini struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, 1440d09e41aSPaolo Bonzini hwaddr base, int ta_num); 1450d09e41aSPaolo Bonzini 1460d09e41aSPaolo Bonzini struct omap_target_agent_s; 1470d09e41aSPaolo Bonzini struct omap_target_agent_s *omap_l4ta_get( 1480d09e41aSPaolo Bonzini struct omap_l4_s *bus, 1490d09e41aSPaolo Bonzini const struct omap_l4_region_s *regions, 1500d09e41aSPaolo Bonzini const struct omap_l4_agent_info_s *agents, 1510d09e41aSPaolo Bonzini int cs); 1520d09e41aSPaolo Bonzini hwaddr omap_l4_attach(struct omap_target_agent_s *ta, 1530d09e41aSPaolo Bonzini int region, MemoryRegion *mr); 1540d09e41aSPaolo Bonzini hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, 1550d09e41aSPaolo Bonzini int region); 1560d09e41aSPaolo Bonzini hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, 1570d09e41aSPaolo Bonzini int region); 1580d09e41aSPaolo Bonzini 1590d09e41aSPaolo Bonzini /* OMAP2 SDRAM controller */ 1600d09e41aSPaolo Bonzini struct omap_sdrc_s; 1610d09e41aSPaolo Bonzini struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, 1620d09e41aSPaolo Bonzini hwaddr base); 1630d09e41aSPaolo Bonzini void omap_sdrc_reset(struct omap_sdrc_s *s); 1640d09e41aSPaolo Bonzini 1650d09e41aSPaolo Bonzini /* OMAP2 general purpose memory controller */ 1660d09e41aSPaolo Bonzini struct omap_gpmc_s; 1670d09e41aSPaolo Bonzini struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, 1680d09e41aSPaolo Bonzini hwaddr base, 1690d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq drq); 1700d09e41aSPaolo Bonzini void omap_gpmc_reset(struct omap_gpmc_s *s); 1710d09e41aSPaolo Bonzini void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); 1720d09e41aSPaolo Bonzini void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); 1730d09e41aSPaolo Bonzini 1740d09e41aSPaolo Bonzini /* 1750d09e41aSPaolo Bonzini * Common IRQ numbers for level 1 interrupt handler 1760d09e41aSPaolo Bonzini * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. 1770d09e41aSPaolo Bonzini */ 1780d09e41aSPaolo Bonzini # define OMAP_INT_CAMERA 1 1790d09e41aSPaolo Bonzini # define OMAP_INT_FIQ 3 1800d09e41aSPaolo Bonzini # define OMAP_INT_RTDX 6 1810d09e41aSPaolo Bonzini # define OMAP_INT_DSP_MMU_ABORT 7 1820d09e41aSPaolo Bonzini # define OMAP_INT_HOST 8 1830d09e41aSPaolo Bonzini # define OMAP_INT_ABORT 9 1840d09e41aSPaolo Bonzini # define OMAP_INT_BRIDGE_PRIV 13 1850d09e41aSPaolo Bonzini # define OMAP_INT_GPIO_BANK1 14 1860d09e41aSPaolo Bonzini # define OMAP_INT_UART3 15 1870d09e41aSPaolo Bonzini # define OMAP_INT_TIMER3 16 1880d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH0_6 19 1890d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH1_7 20 1900d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH2_8 21 1910d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH3 22 1920d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH4 23 1930d09e41aSPaolo Bonzini # define OMAP_INT_DMA_CH5 24 1940d09e41aSPaolo Bonzini # define OMAP_INT_DMA_LCD 25 1950d09e41aSPaolo Bonzini # define OMAP_INT_TIMER1 26 1960d09e41aSPaolo Bonzini # define OMAP_INT_WD_TIMER 27 1970d09e41aSPaolo Bonzini # define OMAP_INT_BRIDGE_PUB 28 1980d09e41aSPaolo Bonzini # define OMAP_INT_TIMER2 30 1990d09e41aSPaolo Bonzini # define OMAP_INT_LCD_CTRL 31 2000d09e41aSPaolo Bonzini 2010d09e41aSPaolo Bonzini /* 2020d09e41aSPaolo Bonzini * Common OMAP-15xx IRQ numbers for level 1 interrupt handler 2030d09e41aSPaolo Bonzini */ 2040d09e41aSPaolo Bonzini # define OMAP_INT_15XX_IH2_IRQ 0 2050d09e41aSPaolo Bonzini # define OMAP_INT_15XX_LB_MMU 17 2060d09e41aSPaolo Bonzini # define OMAP_INT_15XX_LOCAL_BUS 29 2070d09e41aSPaolo Bonzini 2080d09e41aSPaolo Bonzini /* 2090d09e41aSPaolo Bonzini * OMAP-1510 specific IRQ numbers for level 1 interrupt handler 2100d09e41aSPaolo Bonzini */ 2110d09e41aSPaolo Bonzini # define OMAP_INT_1510_SPI_TX 4 2120d09e41aSPaolo Bonzini # define OMAP_INT_1510_SPI_RX 5 2130d09e41aSPaolo Bonzini # define OMAP_INT_1510_DSP_MAILBOX1 10 2140d09e41aSPaolo Bonzini # define OMAP_INT_1510_DSP_MAILBOX2 11 2150d09e41aSPaolo Bonzini 2160d09e41aSPaolo Bonzini /* 2170d09e41aSPaolo Bonzini * OMAP-310 specific IRQ numbers for level 1 interrupt handler 2180d09e41aSPaolo Bonzini */ 2190d09e41aSPaolo Bonzini # define OMAP_INT_310_McBSP2_TX 4 2200d09e41aSPaolo Bonzini # define OMAP_INT_310_McBSP2_RX 5 2210d09e41aSPaolo Bonzini # define OMAP_INT_310_HSB_MAILBOX1 12 2220d09e41aSPaolo Bonzini # define OMAP_INT_310_HSAB_MMU 18 2230d09e41aSPaolo Bonzini 2240d09e41aSPaolo Bonzini /* 2250d09e41aSPaolo Bonzini * OMAP-1610 specific IRQ numbers for level 1 interrupt handler 2260d09e41aSPaolo Bonzini */ 2270d09e41aSPaolo Bonzini # define OMAP_INT_1610_IH2_IRQ 0 2280d09e41aSPaolo Bonzini # define OMAP_INT_1610_IH2_FIQ 2 2290d09e41aSPaolo Bonzini # define OMAP_INT_1610_McBSP2_TX 4 2300d09e41aSPaolo Bonzini # define OMAP_INT_1610_McBSP2_RX 5 2310d09e41aSPaolo Bonzini # define OMAP_INT_1610_DSP_MAILBOX1 10 2320d09e41aSPaolo Bonzini # define OMAP_INT_1610_DSP_MAILBOX2 11 2330d09e41aSPaolo Bonzini # define OMAP_INT_1610_LCD_LINE 12 2340d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER1 17 2350d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER2 18 2360d09e41aSPaolo Bonzini # define OMAP_INT_1610_SSR_FIFO_0 29 2370d09e41aSPaolo Bonzini 2380d09e41aSPaolo Bonzini /* 2390d09e41aSPaolo Bonzini * OMAP-730 specific IRQ numbers for level 1 interrupt handler 2400d09e41aSPaolo Bonzini */ 2410d09e41aSPaolo Bonzini # define OMAP_INT_730_IH2_FIQ 0 2420d09e41aSPaolo Bonzini # define OMAP_INT_730_IH2_IRQ 1 2430d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_NON_ISO 2 2440d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_ISO 3 2450d09e41aSPaolo Bonzini # define OMAP_INT_730_ICR 4 2460d09e41aSPaolo Bonzini # define OMAP_INT_730_EAC 5 2470d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK1 6 2480d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK2 7 2490d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK3 8 2500d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP2TX 10 2510d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP2RX 11 2520d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP2RX_OVF 12 2530d09e41aSPaolo Bonzini # define OMAP_INT_730_LCD_LINE 14 2540d09e41aSPaolo Bonzini # define OMAP_INT_730_GSM_PROTECT 15 2550d09e41aSPaolo Bonzini # define OMAP_INT_730_TIMER3 16 2560d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK5 17 2570d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK6 18 2580d09e41aSPaolo Bonzini # define OMAP_INT_730_SPGIO_WR 29 2590d09e41aSPaolo Bonzini 2600d09e41aSPaolo Bonzini /* 2610d09e41aSPaolo Bonzini * Common IRQ numbers for level 2 interrupt handler 2620d09e41aSPaolo Bonzini */ 2630d09e41aSPaolo Bonzini # define OMAP_INT_KEYBOARD 1 2640d09e41aSPaolo Bonzini # define OMAP_INT_uWireTX 2 2650d09e41aSPaolo Bonzini # define OMAP_INT_uWireRX 3 2660d09e41aSPaolo Bonzini # define OMAP_INT_I2C 4 2670d09e41aSPaolo Bonzini # define OMAP_INT_MPUIO 5 2680d09e41aSPaolo Bonzini # define OMAP_INT_USB_HHC_1 6 2690d09e41aSPaolo Bonzini # define OMAP_INT_McBSP3TX 10 2700d09e41aSPaolo Bonzini # define OMAP_INT_McBSP3RX 11 2710d09e41aSPaolo Bonzini # define OMAP_INT_McBSP1TX 12 2720d09e41aSPaolo Bonzini # define OMAP_INT_McBSP1RX 13 2730d09e41aSPaolo Bonzini # define OMAP_INT_UART1 14 2740d09e41aSPaolo Bonzini # define OMAP_INT_UART2 15 2750d09e41aSPaolo Bonzini # define OMAP_INT_USB_W2FC 20 2760d09e41aSPaolo Bonzini # define OMAP_INT_1WIRE 21 2770d09e41aSPaolo Bonzini # define OMAP_INT_OS_TIMER 22 2780d09e41aSPaolo Bonzini # define OMAP_INT_OQN 23 2790d09e41aSPaolo Bonzini # define OMAP_INT_GAUGE_32K 24 2800d09e41aSPaolo Bonzini # define OMAP_INT_RTC_TIMER 25 2810d09e41aSPaolo Bonzini # define OMAP_INT_RTC_ALARM 26 2820d09e41aSPaolo Bonzini # define OMAP_INT_DSP_MMU 28 2830d09e41aSPaolo Bonzini 2840d09e41aSPaolo Bonzini /* 2850d09e41aSPaolo Bonzini * OMAP-1510 specific IRQ numbers for level 2 interrupt handler 2860d09e41aSPaolo Bonzini */ 2870d09e41aSPaolo Bonzini # define OMAP_INT_1510_BT_MCSI1TX 16 2880d09e41aSPaolo Bonzini # define OMAP_INT_1510_BT_MCSI1RX 17 2890d09e41aSPaolo Bonzini # define OMAP_INT_1510_SoSSI_MATCH 19 2900d09e41aSPaolo Bonzini # define OMAP_INT_1510_MEM_STICK 27 2910d09e41aSPaolo Bonzini # define OMAP_INT_1510_COM_SPI_RO 31 2920d09e41aSPaolo Bonzini 2930d09e41aSPaolo Bonzini /* 2940d09e41aSPaolo Bonzini * OMAP-310 specific IRQ numbers for level 2 interrupt handler 2950d09e41aSPaolo Bonzini */ 2960d09e41aSPaolo Bonzini # define OMAP_INT_310_FAC 0 2970d09e41aSPaolo Bonzini # define OMAP_INT_310_USB_HHC_2 7 2980d09e41aSPaolo Bonzini # define OMAP_INT_310_MCSI1_FE 16 2990d09e41aSPaolo Bonzini # define OMAP_INT_310_MCSI2_FE 17 3000d09e41aSPaolo Bonzini # define OMAP_INT_310_USB_W2FC_ISO 29 3010d09e41aSPaolo Bonzini # define OMAP_INT_310_USB_W2FC_NON_ISO 30 3020d09e41aSPaolo Bonzini # define OMAP_INT_310_McBSP2RX_OF 31 3030d09e41aSPaolo Bonzini 3040d09e41aSPaolo Bonzini /* 3050d09e41aSPaolo Bonzini * OMAP-1610 specific IRQ numbers for level 2 interrupt handler 3060d09e41aSPaolo Bonzini */ 3070d09e41aSPaolo Bonzini # define OMAP_INT_1610_FAC 0 3080d09e41aSPaolo Bonzini # define OMAP_INT_1610_USB_HHC_2 7 3090d09e41aSPaolo Bonzini # define OMAP_INT_1610_USB_OTG 8 3100d09e41aSPaolo Bonzini # define OMAP_INT_1610_SoSSI 9 3110d09e41aSPaolo Bonzini # define OMAP_INT_1610_BT_MCSI1TX 16 3120d09e41aSPaolo Bonzini # define OMAP_INT_1610_BT_MCSI1RX 17 3130d09e41aSPaolo Bonzini # define OMAP_INT_1610_SoSSI_MATCH 19 3140d09e41aSPaolo Bonzini # define OMAP_INT_1610_MEM_STICK 27 3150d09e41aSPaolo Bonzini # define OMAP_INT_1610_McBSP2RX_OF 31 3160d09e41aSPaolo Bonzini # define OMAP_INT_1610_STI 32 3170d09e41aSPaolo Bonzini # define OMAP_INT_1610_STI_WAKEUP 33 3180d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER3 34 3190d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER4 35 3200d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER5 36 3210d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER6 37 3220d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER7 38 3230d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPTIMER8 39 3240d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPIO_BANK2 40 3250d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPIO_BANK3 41 3260d09e41aSPaolo Bonzini # define OMAP_INT_1610_MMC2 42 3270d09e41aSPaolo Bonzini # define OMAP_INT_1610_CF 43 3280d09e41aSPaolo Bonzini # define OMAP_INT_1610_WAKE_UP_REQ 46 3290d09e41aSPaolo Bonzini # define OMAP_INT_1610_GPIO_BANK4 48 3300d09e41aSPaolo Bonzini # define OMAP_INT_1610_SPI 49 3310d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH6 53 3320d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH7 54 3330d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH8 55 3340d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH9 56 3350d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH10 57 3360d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH11 58 3370d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH12 59 3380d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH13 60 3390d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH14 61 3400d09e41aSPaolo Bonzini # define OMAP_INT_1610_DMA_CH15 62 3410d09e41aSPaolo Bonzini # define OMAP_INT_1610_NAND 63 3420d09e41aSPaolo Bonzini 3430d09e41aSPaolo Bonzini /* 3440d09e41aSPaolo Bonzini * OMAP-730 specific IRQ numbers for level 2 interrupt handler 3450d09e41aSPaolo Bonzini */ 3460d09e41aSPaolo Bonzini # define OMAP_INT_730_HW_ERRORS 0 3470d09e41aSPaolo Bonzini # define OMAP_INT_730_NFIQ_PWR_FAIL 1 3480d09e41aSPaolo Bonzini # define OMAP_INT_730_CFCD 2 3490d09e41aSPaolo Bonzini # define OMAP_INT_730_CFIREQ 3 3500d09e41aSPaolo Bonzini # define OMAP_INT_730_I2C 4 3510d09e41aSPaolo Bonzini # define OMAP_INT_730_PCC 5 3520d09e41aSPaolo Bonzini # define OMAP_INT_730_MPU_EXT_NIRQ 6 3530d09e41aSPaolo Bonzini # define OMAP_INT_730_SPI_100K_1 7 3540d09e41aSPaolo Bonzini # define OMAP_INT_730_SYREN_SPI 8 3550d09e41aSPaolo Bonzini # define OMAP_INT_730_VLYNQ 9 3560d09e41aSPaolo Bonzini # define OMAP_INT_730_GPIO_BANK4 10 3570d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP1TX 11 3580d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP1RX 12 3590d09e41aSPaolo Bonzini # define OMAP_INT_730_McBSP1RX_OF 13 3600d09e41aSPaolo Bonzini # define OMAP_INT_730_UART_MODEM_IRDA_2 14 3610d09e41aSPaolo Bonzini # define OMAP_INT_730_UART_MODEM_1 15 3620d09e41aSPaolo Bonzini # define OMAP_INT_730_MCSI 16 3630d09e41aSPaolo Bonzini # define OMAP_INT_730_uWireTX 17 3640d09e41aSPaolo Bonzini # define OMAP_INT_730_uWireRX 18 3650d09e41aSPaolo Bonzini # define OMAP_INT_730_SMC_CD 19 3660d09e41aSPaolo Bonzini # define OMAP_INT_730_SMC_IREQ 20 3670d09e41aSPaolo Bonzini # define OMAP_INT_730_HDQ_1WIRE 21 3680d09e41aSPaolo Bonzini # define OMAP_INT_730_TIMER32K 22 3690d09e41aSPaolo Bonzini # define OMAP_INT_730_MMC_SDIO 23 3700d09e41aSPaolo Bonzini # define OMAP_INT_730_UPLD 24 3710d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_HHC_1 27 3720d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_HHC_2 28 3730d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_GENI 29 3740d09e41aSPaolo Bonzini # define OMAP_INT_730_USB_OTG 30 3750d09e41aSPaolo Bonzini # define OMAP_INT_730_CAMERA_IF 31 3760d09e41aSPaolo Bonzini # define OMAP_INT_730_RNG 32 3770d09e41aSPaolo Bonzini # define OMAP_INT_730_DUAL_MODE_TIMER 33 3780d09e41aSPaolo Bonzini # define OMAP_INT_730_DBB_RF_EN 34 3790d09e41aSPaolo Bonzini # define OMAP_INT_730_MPUIO_KEYPAD 35 3800d09e41aSPaolo Bonzini # define OMAP_INT_730_SHA1_MD5 36 3810d09e41aSPaolo Bonzini # define OMAP_INT_730_SPI_100K_2 37 3820d09e41aSPaolo Bonzini # define OMAP_INT_730_RNG_IDLE 38 3830d09e41aSPaolo Bonzini # define OMAP_INT_730_MPUIO 39 3840d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 3850d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_OE_FALLING 41 3860d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_OE_RISING 42 3870d09e41aSPaolo Bonzini # define OMAP_INT_730_LLPC_VSYNC 43 3880d09e41aSPaolo Bonzini # define OMAP_INT_730_WAKE_UP_REQ 46 3890d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH6 53 3900d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH7 54 3910d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH8 55 3920d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH9 56 3930d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH10 57 3940d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH11 58 3950d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH12 59 3960d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH13 60 3970d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH14 61 3980d09e41aSPaolo Bonzini # define OMAP_INT_730_DMA_CH15 62 3990d09e41aSPaolo Bonzini # define OMAP_INT_730_NAND 63 4000d09e41aSPaolo Bonzini 4010d09e41aSPaolo Bonzini /* 4020d09e41aSPaolo Bonzini * OMAP-24xx common IRQ numbers 4030d09e41aSPaolo Bonzini */ 4040d09e41aSPaolo Bonzini # define OMAP_INT_24XX_STI 4 4050d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SYS_NIRQ 7 4060d09e41aSPaolo Bonzini # define OMAP_INT_24XX_L3_IRQ 10 4070d09e41aSPaolo Bonzini # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 4080d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ0 12 4090d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ1 13 4100d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ2 14 4110d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SDMA_IRQ3 15 4120d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP2_IRQ 16 4130d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP3_IRQ 17 4140d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP4_IRQ 18 4150d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP5_IRQ 19 4160d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPMC_IRQ 20 4170d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GUFFAW_IRQ 21 4180d09e41aSPaolo Bonzini # define OMAP_INT_24XX_IVA_IRQ 22 4190d09e41aSPaolo Bonzini # define OMAP_INT_24XX_EAC_IRQ 23 4200d09e41aSPaolo Bonzini # define OMAP_INT_24XX_CAM_IRQ 24 4210d09e41aSPaolo Bonzini # define OMAP_INT_24XX_DSS_IRQ 25 4220d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MAIL_U0_MPU 26 4230d09e41aSPaolo Bonzini # define OMAP_INT_24XX_DSP_UMA 27 4240d09e41aSPaolo Bonzini # define OMAP_INT_24XX_DSP_MMU 28 4250d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK1 29 4260d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK2 30 4270d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK3 31 4280d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPIO_BANK4 32 4290d09e41aSPaolo Bonzini # define OMAP_INT_243X_GPIO_BANK5 33 4300d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MAIL_U3_MPU 34 4310d09e41aSPaolo Bonzini # define OMAP_INT_24XX_WDT3 35 4320d09e41aSPaolo Bonzini # define OMAP_INT_24XX_WDT4 36 4330d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER1 37 4340d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER2 38 4350d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER3 39 4360d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER4 40 4370d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER5 41 4380d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER6 42 4390d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER7 43 4400d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER8 44 4410d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER9 45 4420d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER10 46 4430d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER11 47 4440d09e41aSPaolo Bonzini # define OMAP_INT_24XX_GPTIMER12 48 4450d09e41aSPaolo Bonzini # define OMAP_INT_24XX_PKA_IRQ 50 4460d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SHA1MD5_IRQ 51 4470d09e41aSPaolo Bonzini # define OMAP_INT_24XX_RNG_IRQ 52 4480d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MG_IRQ 53 4490d09e41aSPaolo Bonzini # define OMAP_INT_24XX_I2C1_IRQ 56 4500d09e41aSPaolo Bonzini # define OMAP_INT_24XX_I2C2_IRQ 57 4510d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 4520d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 4530d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 4540d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 4550d09e41aSPaolo Bonzini # define OMAP_INT_243X_MCBSP1_IRQ 64 4560d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCSPI1_IRQ 65 4570d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCSPI2_IRQ 66 4580d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI1_IRQ0 67 4590d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI1_IRQ1 68 4600d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI2_IRQ0 69 4610d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI2_IRQ1 70 4620d09e41aSPaolo Bonzini # define OMAP_INT_24XX_SSI_GDD_IRQ 71 4630d09e41aSPaolo Bonzini # define OMAP_INT_24XX_UART1_IRQ 72 4640d09e41aSPaolo Bonzini # define OMAP_INT_24XX_UART2_IRQ 73 4650d09e41aSPaolo Bonzini # define OMAP_INT_24XX_UART3_IRQ 74 4660d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_GEN 75 4670d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_NISO 76 4680d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_ISO 77 4690d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_HGEN 78 4700d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_HSOF 79 4710d09e41aSPaolo Bonzini # define OMAP_INT_24XX_USB_IRQ_OTG 80 4720d09e41aSPaolo Bonzini # define OMAP_INT_24XX_VLYNQ_IRQ 81 4730d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MMC_IRQ 83 4740d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MS_IRQ 84 4750d09e41aSPaolo Bonzini # define OMAP_INT_24XX_FAC_IRQ 85 4760d09e41aSPaolo Bonzini # define OMAP_INT_24XX_MCSPI3_IRQ 91 4770d09e41aSPaolo Bonzini # define OMAP_INT_243X_HS_USB_MC 92 4780d09e41aSPaolo Bonzini # define OMAP_INT_243X_HS_USB_DMA 93 4790d09e41aSPaolo Bonzini # define OMAP_INT_243X_CARKIT 94 4800d09e41aSPaolo Bonzini # define OMAP_INT_34XX_GPTIMER12 95 4810d09e41aSPaolo Bonzini 4820d09e41aSPaolo Bonzini /* omap_dma.c */ 4830d09e41aSPaolo Bonzini enum omap_dma_model { 4840d09e41aSPaolo Bonzini omap_dma_3_0, 4850d09e41aSPaolo Bonzini omap_dma_3_1, 4860d09e41aSPaolo Bonzini omap_dma_3_2, 4870d09e41aSPaolo Bonzini omap_dma_4, 4880d09e41aSPaolo Bonzini }; 4890d09e41aSPaolo Bonzini 4900d09e41aSPaolo Bonzini struct soc_dma_s; 4910d09e41aSPaolo Bonzini struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, 4920d09e41aSPaolo Bonzini MemoryRegion *sysmem, 4930d09e41aSPaolo Bonzini qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, 4940d09e41aSPaolo Bonzini enum omap_dma_model model); 4950d09e41aSPaolo Bonzini struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, 4960d09e41aSPaolo Bonzini MemoryRegion *sysmem, 4970d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu, int fifo, 4980d09e41aSPaolo Bonzini int chans, omap_clk iclk, omap_clk fclk); 4990d09e41aSPaolo Bonzini void omap_dma_reset(struct soc_dma_s *s); 5000d09e41aSPaolo Bonzini 5010d09e41aSPaolo Bonzini struct dma_irq_map { 5020d09e41aSPaolo Bonzini int ih; 5030d09e41aSPaolo Bonzini int intr; 5040d09e41aSPaolo Bonzini }; 5050d09e41aSPaolo Bonzini 5060d09e41aSPaolo Bonzini /* Only used in OMAP DMA 3.x gigacells */ 5070d09e41aSPaolo Bonzini enum omap_dma_port { 5080d09e41aSPaolo Bonzini emiff = 0, 5090d09e41aSPaolo Bonzini emifs, 5100d09e41aSPaolo Bonzini imif, /* omap16xx: ocp_t1 */ 5110d09e41aSPaolo Bonzini tipb, 5120d09e41aSPaolo Bonzini local, /* omap16xx: ocp_t2 */ 5130d09e41aSPaolo Bonzini tipb_mpui, 5140d09e41aSPaolo Bonzini __omap_dma_port_last, 5150d09e41aSPaolo Bonzini }; 5160d09e41aSPaolo Bonzini 5170d09e41aSPaolo Bonzini typedef enum { 5180d09e41aSPaolo Bonzini constant = 0, 5190d09e41aSPaolo Bonzini post_incremented, 5200d09e41aSPaolo Bonzini single_index, 5210d09e41aSPaolo Bonzini double_index, 5220d09e41aSPaolo Bonzini } omap_dma_addressing_t; 5230d09e41aSPaolo Bonzini 5240d09e41aSPaolo Bonzini /* Only used in OMAP DMA 3.x gigacells */ 5250d09e41aSPaolo Bonzini struct omap_dma_lcd_channel_s { 5260d09e41aSPaolo Bonzini enum omap_dma_port src; 5270d09e41aSPaolo Bonzini hwaddr src_f1_top; 5280d09e41aSPaolo Bonzini hwaddr src_f1_bottom; 5290d09e41aSPaolo Bonzini hwaddr src_f2_top; 5300d09e41aSPaolo Bonzini hwaddr src_f2_bottom; 5310d09e41aSPaolo Bonzini 5320d09e41aSPaolo Bonzini /* Used in OMAP DMA 3.2 gigacell */ 5330d09e41aSPaolo Bonzini unsigned char brust_f1; 5340d09e41aSPaolo Bonzini unsigned char pack_f1; 5350d09e41aSPaolo Bonzini unsigned char data_type_f1; 5360d09e41aSPaolo Bonzini unsigned char brust_f2; 5370d09e41aSPaolo Bonzini unsigned char pack_f2; 5380d09e41aSPaolo Bonzini unsigned char data_type_f2; 5390d09e41aSPaolo Bonzini unsigned char end_prog; 5400d09e41aSPaolo Bonzini unsigned char repeat; 5410d09e41aSPaolo Bonzini unsigned char auto_init; 5420d09e41aSPaolo Bonzini unsigned char priority; 5430d09e41aSPaolo Bonzini unsigned char fs; 5440d09e41aSPaolo Bonzini unsigned char running; 5450d09e41aSPaolo Bonzini unsigned char bs; 5460d09e41aSPaolo Bonzini unsigned char omap_3_1_compatible_disable; 5470d09e41aSPaolo Bonzini unsigned char dst; 5480d09e41aSPaolo Bonzini unsigned char lch_type; 5490d09e41aSPaolo Bonzini int16_t element_index_f1; 5500d09e41aSPaolo Bonzini int16_t element_index_f2; 5510d09e41aSPaolo Bonzini int32_t frame_index_f1; 5520d09e41aSPaolo Bonzini int32_t frame_index_f2; 5530d09e41aSPaolo Bonzini uint16_t elements_f1; 5540d09e41aSPaolo Bonzini uint16_t frames_f1; 5550d09e41aSPaolo Bonzini uint16_t elements_f2; 5560d09e41aSPaolo Bonzini uint16_t frames_f2; 5570d09e41aSPaolo Bonzini omap_dma_addressing_t mode_f1; 5580d09e41aSPaolo Bonzini omap_dma_addressing_t mode_f2; 5590d09e41aSPaolo Bonzini 5600d09e41aSPaolo Bonzini /* Destination port is fixed. */ 5610d09e41aSPaolo Bonzini int interrupts; 5620d09e41aSPaolo Bonzini int condition; 5630d09e41aSPaolo Bonzini int dual; 5640d09e41aSPaolo Bonzini 5650d09e41aSPaolo Bonzini int current_frame; 5660d09e41aSPaolo Bonzini hwaddr phys_framebuffer[2]; 5670d09e41aSPaolo Bonzini qemu_irq irq; 5680d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu; 5690d09e41aSPaolo Bonzini } *omap_dma_get_lcdch(struct soc_dma_s *s); 5700d09e41aSPaolo Bonzini 5710d09e41aSPaolo Bonzini /* 5720d09e41aSPaolo Bonzini * DMA request numbers for OMAP1 5730d09e41aSPaolo Bonzini * See /usr/include/asm-arm/arch-omap/dma.h in Linux. 5740d09e41aSPaolo Bonzini */ 5750d09e41aSPaolo Bonzini # define OMAP_DMA_NO_DEVICE 0 5760d09e41aSPaolo Bonzini # define OMAP_DMA_MCSI1_TX 1 5770d09e41aSPaolo Bonzini # define OMAP_DMA_MCSI1_RX 2 5780d09e41aSPaolo Bonzini # define OMAP_DMA_I2C_RX 3 5790d09e41aSPaolo Bonzini # define OMAP_DMA_I2C_TX 4 5800d09e41aSPaolo Bonzini # define OMAP_DMA_EXT_NDMA_REQ0 5 5810d09e41aSPaolo Bonzini # define OMAP_DMA_EXT_NDMA_REQ1 6 5820d09e41aSPaolo Bonzini # define OMAP_DMA_UWIRE_TX 7 5830d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP1_TX 8 5840d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP1_RX 9 5850d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP3_TX 10 5860d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP3_RX 11 5870d09e41aSPaolo Bonzini # define OMAP_DMA_UART1_TX 12 5880d09e41aSPaolo Bonzini # define OMAP_DMA_UART1_RX 13 5890d09e41aSPaolo Bonzini # define OMAP_DMA_UART2_TX 14 5900d09e41aSPaolo Bonzini # define OMAP_DMA_UART2_RX 15 5910d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP2_TX 16 5920d09e41aSPaolo Bonzini # define OMAP_DMA_MCBSP2_RX 17 5930d09e41aSPaolo Bonzini # define OMAP_DMA_UART3_TX 18 5940d09e41aSPaolo Bonzini # define OMAP_DMA_UART3_RX 19 5950d09e41aSPaolo Bonzini # define OMAP_DMA_CAMERA_IF_RX 20 5960d09e41aSPaolo Bonzini # define OMAP_DMA_MMC_TX 21 5970d09e41aSPaolo Bonzini # define OMAP_DMA_MMC_RX 22 5980d09e41aSPaolo Bonzini # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ 5990d09e41aSPaolo Bonzini # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ 6000d09e41aSPaolo Bonzini # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ 6010d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_RX0 26 6020d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_RX1 27 6030d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_RX2 28 6040d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_TX0 29 6050d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_TX1 30 6060d09e41aSPaolo Bonzini # define OMAP_DMA_USB_W2FC_TX2 31 6070d09e41aSPaolo Bonzini 6080d09e41aSPaolo Bonzini /* These are only for 1610 */ 6090d09e41aSPaolo Bonzini # define OMAP_DMA_CRYPTO_DES_IN 32 6100d09e41aSPaolo Bonzini # define OMAP_DMA_SPI_TX 33 6110d09e41aSPaolo Bonzini # define OMAP_DMA_SPI_RX 34 6120d09e41aSPaolo Bonzini # define OMAP_DMA_CRYPTO_HASH 35 6130d09e41aSPaolo Bonzini # define OMAP_DMA_CCP_ATTN 36 6140d09e41aSPaolo Bonzini # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 6150d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 6160d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 6170d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 6180d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 6190d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 6200d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 6210d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 6220d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 6230d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 6240d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 6250d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 6260d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 6270d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 6280d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 6290d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 6300d09e41aSPaolo Bonzini # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 6310d09e41aSPaolo Bonzini # define OMAP_DMA_MMC2_TX 54 6320d09e41aSPaolo Bonzini # define OMAP_DMA_MMC2_RX 55 6330d09e41aSPaolo Bonzini # define OMAP_DMA_CRYPTO_DES_OUT 56 6340d09e41aSPaolo Bonzini 6350d09e41aSPaolo Bonzini /* 6360d09e41aSPaolo Bonzini * DMA request numbers for the OMAP2 6370d09e41aSPaolo Bonzini */ 6380d09e41aSPaolo Bonzini # define OMAP24XX_DMA_NO_DEVICE 0 6390d09e41aSPaolo Bonzini # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ 6400d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ0 2 6410d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ1 3 6420d09e41aSPaolo Bonzini # define OMAP24XX_DMA_GPMC 4 6430d09e41aSPaolo Bonzini # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ 6440d09e41aSPaolo Bonzini # define OMAP24XX_DMA_DSS 6 6450d09e41aSPaolo Bonzini # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ 6460d09e41aSPaolo Bonzini # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ 6470d09e41aSPaolo Bonzini # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ 6480d09e41aSPaolo Bonzini # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ 6490d09e41aSPaolo Bonzini # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ 6500d09e41aSPaolo Bonzini # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ 6510d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ 6520d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ2 14 6530d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ3 15 6540d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ4 16 6550d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_AC_RD 17 6560d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_AC_WR 18 6570d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_UL_RD 19 6580d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_UL_WR 20 6590d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_DL_RD 21 6600d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_MD_DL_WR 22 6610d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_UL_RD 23 6620d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_UL_WR 24 6630d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_DL_RD 25 6640d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EAC_BT_DL_WR 26 6650d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C1_TX 27 6660d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C1_RX 28 6670d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C2_TX 29 6680d09e41aSPaolo Bonzini # define OMAP24XX_DMA_I2C2_RX 30 6690d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP1_TX 31 6700d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP1_RX 32 6710d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP2_TX 33 6720d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MCBSP2_RX 34 6730d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX0 35 6740d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX0 36 6750d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX1 37 6760d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX1 38 6770d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX2 39 6780d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX2 40 6790d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_TX3 41 6800d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI1_RX3 42 6810d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_TX0 43 6820d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_RX0 44 6830d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_TX1 45 6840d09e41aSPaolo Bonzini # define OMAP24XX_DMA_SPI2_RX1 46 6850d09e41aSPaolo Bonzini 6860d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART1_TX 49 6870d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART1_RX 50 6880d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART2_TX 51 6890d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART2_RX 52 6900d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART3_TX 53 6910d09e41aSPaolo Bonzini # define OMAP24XX_DMA_UART3_RX 54 6920d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_TX0 55 6930d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_RX0 56 6940d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_TX1 57 6950d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_RX1 58 6960d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_TX2 59 6970d09e41aSPaolo Bonzini # define OMAP24XX_DMA_USB_W2FC_RX2 60 6980d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MMC1_TX 61 6990d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MMC1_RX 62 7000d09e41aSPaolo Bonzini # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ 7010d09e41aSPaolo Bonzini # define OMAP24XX_DMA_EXT_DMAREQ5 64 7020d09e41aSPaolo Bonzini 7030d09e41aSPaolo Bonzini /* omap[123].c */ 7040d09e41aSPaolo Bonzini /* OMAP2 gp timer */ 7050d09e41aSPaolo Bonzini struct omap_gp_timer_s; 7060d09e41aSPaolo Bonzini struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, 7070d09e41aSPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk); 7080d09e41aSPaolo Bonzini void omap_gp_timer_reset(struct omap_gp_timer_s *s); 7090d09e41aSPaolo Bonzini 7100d09e41aSPaolo Bonzini /* OMAP2 sysctimer */ 7110d09e41aSPaolo Bonzini struct omap_synctimer_s; 7120d09e41aSPaolo Bonzini struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, 7130d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); 7140d09e41aSPaolo Bonzini void omap_synctimer_reset(struct omap_synctimer_s *s); 7150d09e41aSPaolo Bonzini 7160d09e41aSPaolo Bonzini struct omap_uart_s; 7170d09e41aSPaolo Bonzini struct omap_uart_s *omap_uart_init(hwaddr base, 7180d09e41aSPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk, 7190d09e41aSPaolo Bonzini qemu_irq txdma, qemu_irq rxdma, 7200ec7b3e7SMarc-André Lureau const char *label, Chardev *chr); 7210d09e41aSPaolo Bonzini struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, 7220d09e41aSPaolo Bonzini struct omap_target_agent_s *ta, 7230d09e41aSPaolo Bonzini qemu_irq irq, omap_clk fclk, omap_clk iclk, 7240d09e41aSPaolo Bonzini qemu_irq txdma, qemu_irq rxdma, 7250ec7b3e7SMarc-André Lureau const char *label, Chardev *chr); 7260d09e41aSPaolo Bonzini void omap_uart_reset(struct omap_uart_s *s); 7270d09e41aSPaolo Bonzini 7280d09e41aSPaolo Bonzini struct omap_mpuio_s; 7290d09e41aSPaolo Bonzini qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); 7300d09e41aSPaolo Bonzini void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); 7310d09e41aSPaolo Bonzini void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); 7320d09e41aSPaolo Bonzini 7330d09e41aSPaolo Bonzini struct omap_uwire_s; 7340d09e41aSPaolo Bonzini void omap_uwire_attach(struct omap_uwire_s *s, 7350d09e41aSPaolo Bonzini uWireSlave *slave, int chipselect); 7360d09e41aSPaolo Bonzini 7370d09e41aSPaolo Bonzini /* OMAP2 spi */ 7380d09e41aSPaolo Bonzini struct omap_mcspi_s; 7390d09e41aSPaolo Bonzini struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, 7400d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); 7410d09e41aSPaolo Bonzini void omap_mcspi_attach(struct omap_mcspi_s *s, 7420d09e41aSPaolo Bonzini uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, 7430d09e41aSPaolo Bonzini int chipselect); 7440d09e41aSPaolo Bonzini void omap_mcspi_reset(struct omap_mcspi_s *s); 7450d09e41aSPaolo Bonzini 7460d09e41aSPaolo Bonzini struct I2SCodec { 7470d09e41aSPaolo Bonzini void *opaque; 7480d09e41aSPaolo Bonzini 7490d09e41aSPaolo Bonzini /* The CPU can call this if it is generating the clock signal on the 7500d09e41aSPaolo Bonzini * i2s port. The CODEC can ignore it if it is set up as a clock 7510d09e41aSPaolo Bonzini * master and generates its own clock. */ 7520d09e41aSPaolo Bonzini void (*set_rate)(void *opaque, int in, int out); 7530d09e41aSPaolo Bonzini 7540d09e41aSPaolo Bonzini void (*tx_swallow)(void *opaque); 7550d09e41aSPaolo Bonzini qemu_irq rx_swallow; 7560d09e41aSPaolo Bonzini qemu_irq tx_start; 7570d09e41aSPaolo Bonzini 7580d09e41aSPaolo Bonzini int tx_rate; 7590d09e41aSPaolo Bonzini int cts; 7600d09e41aSPaolo Bonzini int rx_rate; 7610d09e41aSPaolo Bonzini int rts; 7620d09e41aSPaolo Bonzini 7630d09e41aSPaolo Bonzini struct i2s_fifo_s { 7640d09e41aSPaolo Bonzini uint8_t *fifo; 7650d09e41aSPaolo Bonzini int len; 7660d09e41aSPaolo Bonzini int start; 7670d09e41aSPaolo Bonzini int size; 7680d09e41aSPaolo Bonzini } in, out; 7690d09e41aSPaolo Bonzini }; 7700d09e41aSPaolo Bonzini struct omap_mcbsp_s; 7710d09e41aSPaolo Bonzini void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); 7720d09e41aSPaolo Bonzini 7730d09e41aSPaolo Bonzini void omap_tap_init(struct omap_target_agent_s *ta, 7740d09e41aSPaolo Bonzini struct omap_mpu_state_s *mpu); 7750d09e41aSPaolo Bonzini 7760d09e41aSPaolo Bonzini /* omap_lcdc.c */ 7770d09e41aSPaolo Bonzini struct omap_lcd_panel_s; 7780d09e41aSPaolo Bonzini void omap_lcdc_reset(struct omap_lcd_panel_s *s); 7790d09e41aSPaolo Bonzini struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, 7800d09e41aSPaolo Bonzini hwaddr base, 7810d09e41aSPaolo Bonzini qemu_irq irq, 7820d09e41aSPaolo Bonzini struct omap_dma_lcd_channel_s *dma, 7830d09e41aSPaolo Bonzini omap_clk clk); 7840d09e41aSPaolo Bonzini 7850d09e41aSPaolo Bonzini /* omap_dss.c */ 7860d09e41aSPaolo Bonzini struct rfbi_chip_s { 7870d09e41aSPaolo Bonzini void *opaque; 7880d09e41aSPaolo Bonzini void (*write)(void *opaque, int dc, uint16_t value); 7890d09e41aSPaolo Bonzini void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); 7900d09e41aSPaolo Bonzini uint16_t (*read)(void *opaque, int dc); 7910d09e41aSPaolo Bonzini }; 7920d09e41aSPaolo Bonzini struct omap_dss_s; 7930d09e41aSPaolo Bonzini void omap_dss_reset(struct omap_dss_s *s); 7940d09e41aSPaolo Bonzini struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, 7950d09e41aSPaolo Bonzini MemoryRegion *sysmem, 7960d09e41aSPaolo Bonzini hwaddr l3_base, 7970d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq drq, 7980d09e41aSPaolo Bonzini omap_clk fck1, omap_clk fck2, omap_clk ck54m, 7990d09e41aSPaolo Bonzini omap_clk ick1, omap_clk ick2); 8000d09e41aSPaolo Bonzini void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); 8010d09e41aSPaolo Bonzini 8020d09e41aSPaolo Bonzini /* omap_mmc.c */ 8030d09e41aSPaolo Bonzini struct omap_mmc_s; 8040d09e41aSPaolo Bonzini struct omap_mmc_s *omap_mmc_init(hwaddr base, 8050d09e41aSPaolo Bonzini MemoryRegion *sysmem, 8064be74634SMarkus Armbruster BlockBackend *blk, 8070d09e41aSPaolo Bonzini qemu_irq irq, qemu_irq dma[], omap_clk clk); 8080d09e41aSPaolo Bonzini struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, 8094be74634SMarkus Armbruster BlockBackend *blk, qemu_irq irq, qemu_irq dma[], 8100d09e41aSPaolo Bonzini omap_clk fclk, omap_clk iclk); 8110d09e41aSPaolo Bonzini void omap_mmc_reset(struct omap_mmc_s *s); 8120d09e41aSPaolo Bonzini void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); 8130d09e41aSPaolo Bonzini void omap_mmc_enable(struct omap_mmc_s *s, int enable); 8140d09e41aSPaolo Bonzini 8150d09e41aSPaolo Bonzini /* omap_i2c.c */ 816a5c82852SAndreas Färber I2CBus *omap_i2c_bus(DeviceState *omap_i2c); 8170d09e41aSPaolo Bonzini 8180d09e41aSPaolo Bonzini # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) 8190d09e41aSPaolo Bonzini # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) 8200d09e41aSPaolo Bonzini # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) 8210d09e41aSPaolo Bonzini # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) 8220d09e41aSPaolo Bonzini # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) 8230d09e41aSPaolo Bonzini # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) 8240d09e41aSPaolo Bonzini # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) 8250d09e41aSPaolo Bonzini # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) 8260d09e41aSPaolo Bonzini # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) 8270d09e41aSPaolo Bonzini 8280d09e41aSPaolo Bonzini # define cpu_is_omap15xx(cpu) \ 8290d09e41aSPaolo Bonzini (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) 8300d09e41aSPaolo Bonzini # define cpu_is_omap16xx(cpu) \ 8310d09e41aSPaolo Bonzini (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) 8320d09e41aSPaolo Bonzini # define cpu_is_omap24xx(cpu) \ 8330d09e41aSPaolo Bonzini (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) 8340d09e41aSPaolo Bonzini 8350d09e41aSPaolo Bonzini # define cpu_class_omap1(cpu) \ 8360d09e41aSPaolo Bonzini (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) 8370d09e41aSPaolo Bonzini # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) 8380d09e41aSPaolo Bonzini # define cpu_class_omap3(cpu) \ 8390d09e41aSPaolo Bonzini (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) 8400d09e41aSPaolo Bonzini 8410d09e41aSPaolo Bonzini struct omap_mpu_state_s { 8420d09e41aSPaolo Bonzini enum omap_mpu_model { 8430d09e41aSPaolo Bonzini omap310, 8440d09e41aSPaolo Bonzini omap1510, 8450d09e41aSPaolo Bonzini omap1610, 8460d09e41aSPaolo Bonzini omap1710, 8470d09e41aSPaolo Bonzini omap2410, 8480d09e41aSPaolo Bonzini omap2420, 8490d09e41aSPaolo Bonzini omap2422, 8500d09e41aSPaolo Bonzini omap2423, 8510d09e41aSPaolo Bonzini omap2430, 8520d09e41aSPaolo Bonzini omap3430, 8530d09e41aSPaolo Bonzini omap3630, 8540d09e41aSPaolo Bonzini } mpu_model; 8550d09e41aSPaolo Bonzini 8560d09e41aSPaolo Bonzini ARMCPU *cpu; 8570d09e41aSPaolo Bonzini 8580d09e41aSPaolo Bonzini qemu_irq *drq; 8590d09e41aSPaolo Bonzini 8600d09e41aSPaolo Bonzini qemu_irq wakeup; 8610d09e41aSPaolo Bonzini 8620d09e41aSPaolo Bonzini MemoryRegion ulpd_pm_iomem; 8630d09e41aSPaolo Bonzini MemoryRegion pin_cfg_iomem; 8640d09e41aSPaolo Bonzini MemoryRegion id_iomem; 8650d09e41aSPaolo Bonzini MemoryRegion id_iomem_e18; 8660d09e41aSPaolo Bonzini MemoryRegion id_iomem_ed4; 8670d09e41aSPaolo Bonzini MemoryRegion id_iomem_e20; 8680d09e41aSPaolo Bonzini MemoryRegion mpui_iomem; 8690d09e41aSPaolo Bonzini MemoryRegion tcmi_iomem; 8700d09e41aSPaolo Bonzini MemoryRegion clkm_iomem; 8710d09e41aSPaolo Bonzini MemoryRegion clkdsp_iomem; 8720d09e41aSPaolo Bonzini MemoryRegion mpui_io_iomem; 8730d09e41aSPaolo Bonzini MemoryRegion tap_iomem; 8740d09e41aSPaolo Bonzini MemoryRegion imif_ram; 8750d09e41aSPaolo Bonzini MemoryRegion sram; 8760d09e41aSPaolo Bonzini 8770d09e41aSPaolo Bonzini struct omap_dma_port_if_s { 8780d09e41aSPaolo Bonzini uint32_t (*read[3])(struct omap_mpu_state_s *s, 8790d09e41aSPaolo Bonzini hwaddr offset); 8800d09e41aSPaolo Bonzini void (*write[3])(struct omap_mpu_state_s *s, 8810d09e41aSPaolo Bonzini hwaddr offset, uint32_t value); 8820d09e41aSPaolo Bonzini int (*addr_valid)(struct omap_mpu_state_s *s, 8830d09e41aSPaolo Bonzini hwaddr addr); 8840d09e41aSPaolo Bonzini } port[__omap_dma_port_last]; 8850d09e41aSPaolo Bonzini 8864387b253SPhilippe Mathieu-Daudé uint64_t sdram_size; 8870d09e41aSPaolo Bonzini unsigned long sram_size; 8880d09e41aSPaolo Bonzini 8890d09e41aSPaolo Bonzini /* MPUI-TIPB peripherals */ 8900d09e41aSPaolo Bonzini struct omap_uart_s *uart[3]; 8910d09e41aSPaolo Bonzini 8920d09e41aSPaolo Bonzini DeviceState *gpio; 8930d09e41aSPaolo Bonzini 8940d09e41aSPaolo Bonzini struct omap_mcbsp_s *mcbsp1; 8950d09e41aSPaolo Bonzini struct omap_mcbsp_s *mcbsp3; 8960d09e41aSPaolo Bonzini 8970d09e41aSPaolo Bonzini /* MPU public TIPB peripherals */ 8980d09e41aSPaolo Bonzini struct omap_32khz_timer_s *os_timer; 8990d09e41aSPaolo Bonzini 9000d09e41aSPaolo Bonzini struct omap_mmc_s *mmc; 9010d09e41aSPaolo Bonzini 9020d09e41aSPaolo Bonzini struct omap_mpuio_s *mpuio; 9030d09e41aSPaolo Bonzini 9040d09e41aSPaolo Bonzini struct omap_uwire_s *microwire; 9050d09e41aSPaolo Bonzini 9060d09e41aSPaolo Bonzini struct omap_pwl_s *pwl; 9070d09e41aSPaolo Bonzini struct omap_pwt_s *pwt; 9080d09e41aSPaolo Bonzini DeviceState *i2c[2]; 9090d09e41aSPaolo Bonzini 9100d09e41aSPaolo Bonzini struct omap_rtc_s *rtc; 9110d09e41aSPaolo Bonzini 9120d09e41aSPaolo Bonzini struct omap_mcbsp_s *mcbsp2; 9130d09e41aSPaolo Bonzini 9140d09e41aSPaolo Bonzini struct omap_lpg_s *led[2]; 9150d09e41aSPaolo Bonzini 9160d09e41aSPaolo Bonzini /* MPU private TIPB peripherals */ 9170d09e41aSPaolo Bonzini DeviceState *ih[2]; 9180d09e41aSPaolo Bonzini 9190d09e41aSPaolo Bonzini struct soc_dma_s *dma; 9200d09e41aSPaolo Bonzini 9210d09e41aSPaolo Bonzini struct omap_mpu_timer_s *timer[3]; 9220d09e41aSPaolo Bonzini struct omap_watchdog_timer_s *wdt; 9230d09e41aSPaolo Bonzini 9240d09e41aSPaolo Bonzini struct omap_lcd_panel_s *lcd; 9250d09e41aSPaolo Bonzini 9260d09e41aSPaolo Bonzini uint32_t ulpd_pm_regs[21]; 9270d09e41aSPaolo Bonzini int64_t ulpd_gauge_start; 9280d09e41aSPaolo Bonzini 9290d09e41aSPaolo Bonzini uint32_t func_mux_ctrl[14]; 9300d09e41aSPaolo Bonzini uint32_t comp_mode_ctrl[1]; 9310d09e41aSPaolo Bonzini uint32_t pull_dwn_ctrl[4]; 9320d09e41aSPaolo Bonzini uint32_t gate_inh_ctrl[1]; 9330d09e41aSPaolo Bonzini uint32_t voltage_ctrl[1]; 9340d09e41aSPaolo Bonzini uint32_t test_dbg_ctrl[1]; 9350d09e41aSPaolo Bonzini uint32_t mod_conf_ctrl[1]; 9360d09e41aSPaolo Bonzini int compat1509; 9370d09e41aSPaolo Bonzini 9380d09e41aSPaolo Bonzini uint32_t mpui_ctrl; 9390d09e41aSPaolo Bonzini 9400d09e41aSPaolo Bonzini struct omap_tipb_bridge_s *private_tipb; 9410d09e41aSPaolo Bonzini struct omap_tipb_bridge_s *public_tipb; 9420d09e41aSPaolo Bonzini 9430d09e41aSPaolo Bonzini uint32_t tcmi_regs[17]; 9440d09e41aSPaolo Bonzini 9450d09e41aSPaolo Bonzini struct dpll_ctl_s *dpll[3]; 9460d09e41aSPaolo Bonzini 9470d09e41aSPaolo Bonzini omap_clk clks; 9480d09e41aSPaolo Bonzini struct { 9490d09e41aSPaolo Bonzini int cold_start; 9500d09e41aSPaolo Bonzini int clocking_scheme; 9510d09e41aSPaolo Bonzini uint16_t arm_ckctl; 9520d09e41aSPaolo Bonzini uint16_t arm_idlect1; 9530d09e41aSPaolo Bonzini uint16_t arm_idlect2; 9540d09e41aSPaolo Bonzini uint16_t arm_ewupct; 9550d09e41aSPaolo Bonzini uint16_t arm_rstct1; 9560d09e41aSPaolo Bonzini uint16_t arm_rstct2; 9570d09e41aSPaolo Bonzini uint16_t arm_ckout1; 9580d09e41aSPaolo Bonzini int dpll1_mode; 9590d09e41aSPaolo Bonzini uint16_t dsp_idlect1; 9600d09e41aSPaolo Bonzini uint16_t dsp_idlect2; 9610d09e41aSPaolo Bonzini uint16_t dsp_rstct2; 9620d09e41aSPaolo Bonzini } clkm; 9630d09e41aSPaolo Bonzini 9640d09e41aSPaolo Bonzini /* OMAP2-only peripherals */ 9650d09e41aSPaolo Bonzini struct omap_l4_s *l4; 9660d09e41aSPaolo Bonzini 9670d09e41aSPaolo Bonzini struct omap_gp_timer_s *gptimer[12]; 9680d09e41aSPaolo Bonzini struct omap_synctimer_s *synctimer; 9690d09e41aSPaolo Bonzini 9700d09e41aSPaolo Bonzini struct omap_prcm_s *prcm; 9710d09e41aSPaolo Bonzini struct omap_sdrc_s *sdrc; 9720d09e41aSPaolo Bonzini struct omap_gpmc_s *gpmc; 9730d09e41aSPaolo Bonzini struct omap_sysctl_s *sysc; 9740d09e41aSPaolo Bonzini 9750d09e41aSPaolo Bonzini struct omap_mcspi_s *mcspi[2]; 9760d09e41aSPaolo Bonzini 9770d09e41aSPaolo Bonzini struct omap_dss_s *dss; 9780d09e41aSPaolo Bonzini 9790d09e41aSPaolo Bonzini struct omap_eac_s *eac; 9800d09e41aSPaolo Bonzini }; 9810d09e41aSPaolo Bonzini 9820d09e41aSPaolo Bonzini /* omap1.c */ 9834387b253SPhilippe Mathieu-Daudé struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, 9840d09e41aSPaolo Bonzini const char *core); 9850d09e41aSPaolo Bonzini 9860d09e41aSPaolo Bonzini /* omap2.c */ 987e285e867SPhilippe Mathieu-Daudé struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, 9880d09e41aSPaolo Bonzini const char *core); 9890d09e41aSPaolo Bonzini 9900d09e41aSPaolo Bonzini uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); 9910d09e41aSPaolo Bonzini void omap_badwidth_write8(void *opaque, hwaddr addr, 9920d09e41aSPaolo Bonzini uint32_t value); 9930d09e41aSPaolo Bonzini uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); 9940d09e41aSPaolo Bonzini void omap_badwidth_write16(void *opaque, hwaddr addr, 9950d09e41aSPaolo Bonzini uint32_t value); 9960d09e41aSPaolo Bonzini uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); 9970d09e41aSPaolo Bonzini void omap_badwidth_write32(void *opaque, hwaddr addr, 9980d09e41aSPaolo Bonzini uint32_t value); 9990d09e41aSPaolo Bonzini 10000d09e41aSPaolo Bonzini void omap_mpu_wakeup(void *opaque, int irq, int req); 10010d09e41aSPaolo Bonzini 10020d09e41aSPaolo Bonzini # define OMAP_BAD_REG(paddr) \ 100384b335c6SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ 1004a89f364aSAlistair Francis __func__, paddr) 10050d09e41aSPaolo Bonzini # define OMAP_RO_REG(paddr) \ 100684b335c6SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ 100784b335c6SPhilippe Mathieu-Daudé HWADDR_PRIx "\n", \ 1008a89f364aSAlistair Francis __func__, paddr) 10090d09e41aSPaolo Bonzini 10100d09e41aSPaolo Bonzini /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area 1011*c3aa4206SManos Pitsidianakis * (Board-specific tags are not here) 1012*c3aa4206SManos Pitsidianakis */ 10130d09e41aSPaolo Bonzini #define OMAP_TAG_CLOCK 0x4f01 10140d09e41aSPaolo Bonzini #define OMAP_TAG_MMC 0x4f02 10150d09e41aSPaolo Bonzini #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 10160d09e41aSPaolo Bonzini #define OMAP_TAG_USB 0x4f04 10170d09e41aSPaolo Bonzini #define OMAP_TAG_LCD 0x4f05 10180d09e41aSPaolo Bonzini #define OMAP_TAG_GPIO_SWITCH 0x4f06 10190d09e41aSPaolo Bonzini #define OMAP_TAG_UART 0x4f07 10200d09e41aSPaolo Bonzini #define OMAP_TAG_FBMEM 0x4f08 10210d09e41aSPaolo Bonzini #define OMAP_TAG_STI_CONSOLE 0x4f09 10220d09e41aSPaolo Bonzini #define OMAP_TAG_CAMERA_SENSOR 0x4f0a 10230d09e41aSPaolo Bonzini #define OMAP_TAG_PARTITION 0x4f0b 10240d09e41aSPaolo Bonzini #define OMAP_TAG_TEA5761 0x4f10 10250d09e41aSPaolo Bonzini #define OMAP_TAG_TMP105 0x4f11 10260d09e41aSPaolo Bonzini #define OMAP_TAG_BOOT_REASON 0x4f80 10270d09e41aSPaolo Bonzini #define OMAP_TAG_FLASH_PART_STR 0x4f81 10280d09e41aSPaolo Bonzini #define OMAP_TAG_VERSION_STR 0x4f82 10290d09e41aSPaolo Bonzini 10300d09e41aSPaolo Bonzini enum { 10310d09e41aSPaolo Bonzini OMAP_GPIOSW_TYPE_COVER = 0 << 4, 10320d09e41aSPaolo Bonzini OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, 10330d09e41aSPaolo Bonzini OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, 10340d09e41aSPaolo Bonzini }; 10350d09e41aSPaolo Bonzini 10360d09e41aSPaolo Bonzini #define OMAP_GPIOSW_INVERTED 0x0001 10370d09e41aSPaolo Bonzini #define OMAP_GPIOSW_OUTPUT 0x0002 10380d09e41aSPaolo Bonzini 10390d09e41aSPaolo Bonzini # define OMAP_MPUI_REG_MASK 0x000007ff 10400d09e41aSPaolo Bonzini 10410553d895SMarkus Armbruster #endif 1042