Lines Matching +full:0 +full:xe1000000
14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
26 #define CONFIG_SYS_DIAG_ADDR 0xff800000
33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000
53 #define L2_INIT 0
54 #define L2_ENABLE (L2CR_L2E |0x00100000 )
57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END 0x00400000
67 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
79 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
81 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
83 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
89 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
94 #if 0 /* TODO */
95 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
96 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
97 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
98 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
99 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
100 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
101 #define CONFIG_SYS_DDR_MODE_1 0x00480432
102 #define CONFIG_SYS_DDR_MODE_2 0x00000000
103 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
104 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
105 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
106 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
107 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
108 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
109 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
111 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
112 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
113 #define CONFIG_SYS_DDR_SBE 0x000f0000
120 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
123 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
124 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
128 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
129 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
131 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
132 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
133 #if 0 /* TODO */
134 #define CONFIG_SYS_BR2_PRELIM 0xf0000000
135 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
137 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
138 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
141 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */
142 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
143 #define PIXIS_VER 0x1 /* Board version at offset 1 */
144 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
145 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
146 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
147 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
148 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
149 #define PIXIS_VCTL 0x10 /* VELA Control Register */
150 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
151 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
152 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
153 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
154 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
155 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
156 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
157 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
166 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
185 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
187 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
189 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
200 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
225 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
228 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
229 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000
230 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
231 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
232 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
234 /* controller 1, Base address 0xa000 */
236 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
238 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
239 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
240 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
241 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
243 /* controller 2, Base Address 0x9000 */
245 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
247 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
248 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
249 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
250 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
268 #define PCI_ENET0_IOADDR 0xe0000000
269 #define PCI_ENET0_MEMADDR 0xe0000000
270 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
284 * 0x0000_0000 2G DDR
291 * 0x8000_0000 256M PCI-1 Memory
292 * 0xa000_0000 256M PCI-Express 1 Memory
293 * 0x9000_0000 256M PCI-Express 2 Memory
304 * 0xe100_0000 1M PCI-1 I/O
315 * 0xe000_0000 4M CCSR
337 * 0xe200_0000 1M PCI-Express 2 I/O
338 * 0xe300_0000 1M PCI-Express 1 I/O
349 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
358 * 0xf000_0000 256M FLASH
376 * 0xe800_0000 4M PIXIS
389 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
390 #define CONFIG_ENV_SIZE 0x2000
392 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
393 #define CONFIG_ENV_SIZE 0x2000
414 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
443 #define CONFIG_LOADADDR 0x10000000
448 "echo e;md ${a}e00 9\0" \
449 "pci1regs=setenv a e0008; run pcireg\0" \
450 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
451 "pci d.w $b.0 56 1\0" \
452 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
453 "pci w.w $b.0 56 ffff\0" \
454 "pci1err=setenv a e0008; run pcierr\0" \
455 "pci1errc=setenv a e0008; run pcierrc\0"
463 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
464 "pcie1regs=setenv a e000a; run pciereg\0" \
465 "pcie2regs=setenv a e0009; run pciereg\0" \
466 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
467 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
468 "pci d $b.0 130 1\0" \
469 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
470 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
471 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
472 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
473 "pcie1err=setenv a e000a; run pcieerr\0" \
474 "pcie2err=setenv a e0009; run pcieerr\0" \
475 "pcie1errc=setenv a e000a; run pcieerrc\0" \
476 "pcie2errc=setenv a e0009; run pcieerrc\0"
483 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
485 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
487 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
489 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
493 "netdev=eth0\0" \
494 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
505 " $filesize\0" \
506 "consoledev=ttyS0\0" \
507 "ramdiskaddr=0x18000000\0" \
508 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
509 "fdtaddr=0x17c00000\0" \
510 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
511 "bdev=sda3\0" \
512 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
513 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
515 "eoi=mw e00400b0 0\0" \
516 "iack=md e00400a0 1\0" \
519 "md ${a}f00 5\0" \
520 "ddr1regs=setenv a e0002; run ddrreg\0" \
521 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
523 "md ${a}e60 1; md ${a}ef0 1d\0" \
524 "guregs=setenv a e00e0; run gureg\0" \
525 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
526 "mcmregs=setenv a e0001; run mcmreg\0" \
527 "diuregs=md e002c000 1d\0" \
528 "dium=mw e002c01c\0" \
529 "diuerr=md e002c014 1\0" \
530 "pmregs=md e00e1000 2b\0" \
531 "lawregs=md e0000c08 4b\0" \
532 "lbcregs=md e0005000 36\0" \
533 "dma0regs=md e0021100 12\0" \
534 "dma1regs=md e0021180 12\0" \
535 "dma2regs=md e0021200 12\0" \
536 "dma3regs=md e0021280 12\0" \
542 "netdev=eth0\0" \
543 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
544 "consoledev=ttyS0\0" \
545 "ramdiskaddr=0x18000000\0" \
546 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
547 "fdtaddr=0x17c00000\0" \
548 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
549 "bdev=sda3\0"