1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e85390dcSwdenk /* 3e85390dcSwdenk * (C) Copyright 2001 4e85390dcSwdenk * Denis Peter, MPL AG Switzerland 5e85390dcSwdenk * 6e85390dcSwdenk * Most of these definitions are derived from 7e85390dcSwdenk * linux/drivers/scsi/sym53c8xx_defs.h 8e85390dcSwdenk */ 9e85390dcSwdenk 10e85390dcSwdenk #ifndef _SYM53C8XX_DEFS_H 11e85390dcSwdenk #define _SYM53C8XX_DEFS_H 12e85390dcSwdenk 13e85390dcSwdenk 14e85390dcSwdenk #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ 15e85390dcSwdenk 16e85390dcSwdenk #define SCNTL1 0x01 /* no reset */ 17e85390dcSwdenk #define ISCON 0x10 /* connected to scsi */ 18e85390dcSwdenk #define CRST 0x08 /* force reset */ 19e85390dcSwdenk #define IARB 0x02 /* immediate arbitration */ 20e85390dcSwdenk 21e85390dcSwdenk #define SCNTL2 0x02 /* no disconnect expected */ 22e85390dcSwdenk #define SDU 0x80 /* cmd: disconnect will raise error */ 23e85390dcSwdenk #define CHM 0x40 /* sta: chained mode */ 24e85390dcSwdenk #define WSS 0x08 /* sta: wide scsi send [W]*/ 25e85390dcSwdenk #define WSR 0x01 /* sta: wide scsi received [W]*/ 26e85390dcSwdenk 27e85390dcSwdenk #define SCNTL3 0x03 /* cnf system clock dependent */ 28e85390dcSwdenk #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 29e85390dcSwdenk #define ULTRA 0x80 /* cmd: ULTRA enable */ 30e85390dcSwdenk /* bits 0-2, 7 rsvd for C1010 */ 31e85390dcSwdenk 32e85390dcSwdenk #define SCID 0x04 /* cnf host adapter scsi address */ 33e85390dcSwdenk #define RRE 0x40 /* r/w:e enable response to resel. */ 34e85390dcSwdenk #define SRE 0x20 /* r/w:e enable response to select */ 35e85390dcSwdenk 36e85390dcSwdenk #define SXFER 0x05 /* ### Sync speed and count */ 37e85390dcSwdenk /* bits 6-7 rsvd for C1010 */ 38e85390dcSwdenk 39e85390dcSwdenk #define SDID 0x06 /* ### Destination-ID */ 40e85390dcSwdenk 41e85390dcSwdenk #define GPREG 0x07 /* ??? IO-Pins */ 42e85390dcSwdenk 43e85390dcSwdenk #define SFBR 0x08 /* ### First byte in phase */ 44e85390dcSwdenk 45e85390dcSwdenk #define SOCL 0x09 46e85390dcSwdenk #define CREQ 0x80 /* r/w: SCSI-REQ */ 47e85390dcSwdenk #define CACK 0x40 /* r/w: SCSI-ACK */ 48e85390dcSwdenk #define CBSY 0x20 /* r/w: SCSI-BSY */ 49e85390dcSwdenk #define CSEL 0x10 /* r/w: SCSI-SEL */ 50e85390dcSwdenk #define CATN 0x08 /* r/w: SCSI-ATN */ 51e85390dcSwdenk #define CMSG 0x04 /* r/w: SCSI-MSG */ 52e85390dcSwdenk #define CC_D 0x02 /* r/w: SCSI-C_D */ 53e85390dcSwdenk #define CI_O 0x01 /* r/w: SCSI-I_O */ 54e85390dcSwdenk 55e85390dcSwdenk #define SSID 0x0a 56e85390dcSwdenk 57e85390dcSwdenk #define SBCL 0x0b 58e85390dcSwdenk 59e85390dcSwdenk #define DSTAT 0x0c 60e85390dcSwdenk #define DFE 0x80 /* sta: dma fifo empty */ 61e85390dcSwdenk #define MDPE 0x40 /* int: master data parity error */ 62e85390dcSwdenk #define BF 0x20 /* int: script: bus fault */ 63e85390dcSwdenk #define ABRT 0x10 /* int: script: command aborted */ 64e85390dcSwdenk #define SSI 0x08 /* int: script: single step */ 65e85390dcSwdenk #define SIR 0x04 /* int: script: interrupt instruct. */ 66e85390dcSwdenk #define IID 0x01 /* int: script: illegal instruct. */ 67e85390dcSwdenk 68e85390dcSwdenk #define SSTAT0 0x0d 69e85390dcSwdenk #define ILF 0x80 /* sta: data in SIDL register lsb */ 70e85390dcSwdenk #define ORF 0x40 /* sta: data in SODR register lsb */ 71e85390dcSwdenk #define OLF 0x20 /* sta: data in SODL register lsb */ 72e85390dcSwdenk #define AIP 0x10 /* sta: arbitration in progress */ 73e85390dcSwdenk #define LOA 0x08 /* sta: arbitration lost */ 74e85390dcSwdenk #define WOA 0x04 /* sta: arbitration won */ 75e85390dcSwdenk #define IRST 0x02 /* sta: scsi reset signal */ 76e85390dcSwdenk #define SDP 0x01 /* sta: scsi parity signal */ 77e85390dcSwdenk 78e85390dcSwdenk #define SSTAT1 0x0e 79e85390dcSwdenk #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 80e85390dcSwdenk 81e85390dcSwdenk #define SSTAT2 0x0f 82e85390dcSwdenk #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 83e85390dcSwdenk #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 84e85390dcSwdenk #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 85e85390dcSwdenk #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 86e85390dcSwdenk #define LDSC 0x02 /* sta: disconnect & reconnect */ 87e85390dcSwdenk 88e85390dcSwdenk #define DSA 0x10 /* --> Base page */ 89e85390dcSwdenk #define DSA1 0x11 90e85390dcSwdenk #define DSA2 0x12 91e85390dcSwdenk #define DSA3 0x13 92e85390dcSwdenk 93e85390dcSwdenk #define ISTAT 0x14 /* --> Main Command and status */ 94e85390dcSwdenk #define CABRT 0x80 /* cmd: abort current operation */ 95e85390dcSwdenk #define SRST 0x40 /* mod: reset chip */ 96e85390dcSwdenk #define SIGP 0x20 /* r/w: message from host to ncr */ 97e85390dcSwdenk #define SEM 0x10 /* r/w: message between host + ncr */ 98e85390dcSwdenk #define CON 0x08 /* sta: connected to scsi */ 99e85390dcSwdenk #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 100e85390dcSwdenk #define SIP 0x02 /* sta: scsi-interrupt */ 101e85390dcSwdenk #define DIP 0x01 /* sta: host/script interrupt */ 102e85390dcSwdenk 103e85390dcSwdenk 104e85390dcSwdenk #define CTEST0 0x18 105e85390dcSwdenk #define CTEST1 0x19 106e85390dcSwdenk #define CTEST2 0x1a 107e85390dcSwdenk #define CSIGP 0x40 108e85390dcSwdenk /* bits 0-2,7 rsvd for C1010 */ 109e85390dcSwdenk 110e85390dcSwdenk #define CTEST3 0x1b 111e85390dcSwdenk #define FLF 0x08 /* cmd: flush dma fifo */ 112e85390dcSwdenk #define CLF 0x04 /* cmd: clear dma fifo */ 113e85390dcSwdenk #define FM 0x02 /* mod: fetch pin mode */ 114e85390dcSwdenk #define WRIE 0x01 /* mod: write and invalidate enable */ 115e85390dcSwdenk /* bits 4-7 rsvd for C1010 */ 116e85390dcSwdenk 117e85390dcSwdenk #define DFIFO 0x20 118e85390dcSwdenk #define CTEST4 0x21 119e85390dcSwdenk #define BDIS 0x80 /* mod: burst disable */ 120e85390dcSwdenk #define MPEE 0x08 /* mod: master parity error enable */ 121e85390dcSwdenk 122e85390dcSwdenk #define CTEST5 0x22 123e85390dcSwdenk #define DFS 0x20 /* mod: dma fifo size */ 124e85390dcSwdenk /* bits 0-1, 3-7 rsvd for C1010 */ 125e85390dcSwdenk #define CTEST6 0x23 126e85390dcSwdenk 127e85390dcSwdenk #define DBC 0x24 /* ### Byte count and command */ 128e85390dcSwdenk #define DNAD 0x28 /* ### Next command register */ 129e85390dcSwdenk #define DSP 0x2c /* --> Script Pointer */ 130e85390dcSwdenk #define DSPS 0x30 /* --> Script pointer save/opcode#2 */ 131e85390dcSwdenk 132e85390dcSwdenk #define SCRATCHA 0x34 /* Temporary register a */ 133e85390dcSwdenk #define SCRATCHA1 0x35 134e85390dcSwdenk #define SCRATCHA2 0x36 135e85390dcSwdenk #define SCRATCHA3 0x37 136e85390dcSwdenk 137e85390dcSwdenk #define DMODE 0x38 138e85390dcSwdenk #define BL_2 0x80 /* mod: burst length shift value +2 */ 139e85390dcSwdenk #define BL_1 0x40 /* mod: burst length shift value +1 */ 140e85390dcSwdenk #define ERL 0x08 /* mod: enable read line */ 141e85390dcSwdenk #define ERMP 0x04 /* mod: enable read multiple */ 142e85390dcSwdenk #define BOF 0x02 /* mod: burst op code fetch */ 143e85390dcSwdenk #define MAN 0x01 /* mod: manual start */ 144e85390dcSwdenk 145e85390dcSwdenk #define DIEN 0x39 146e85390dcSwdenk #define SBR 0x3a 147e85390dcSwdenk 148e85390dcSwdenk #define DCNTL 0x3b /* --> Script execution control */ 149e85390dcSwdenk #define CLSE 0x80 /* mod: cache line size enable */ 150e85390dcSwdenk #define PFF 0x40 /* cmd: pre-fetch flush */ 151e85390dcSwdenk #define PFEN 0x20 /* mod: pre-fetch enable */ 152e85390dcSwdenk #define SSM 0x10 /* mod: single step mode */ 153e85390dcSwdenk #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 154e85390dcSwdenk #define STD 0x04 /* cmd: start dma mode */ 155e85390dcSwdenk #define IRQD 0x02 /* mod: irq disable */ 156e85390dcSwdenk #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 157e85390dcSwdenk /* bits 0-1 rsvd for C1010 */ 158e85390dcSwdenk 159e85390dcSwdenk #define ADDER 0x3c 160e85390dcSwdenk 161e85390dcSwdenk #define SIEN 0x40 /* -->: interrupt enable */ 162e85390dcSwdenk #define SIST 0x42 /* <--: interrupt status */ 163e85390dcSwdenk #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 164e85390dcSwdenk #define STO 0x0400/* sta: timeout (select) */ 165e85390dcSwdenk #define GEN 0x0200/* sta: timeout (general) */ 166e85390dcSwdenk #define HTH 0x0100/* sta: timeout (handshake) */ 167e85390dcSwdenk #define MA 0x80 /* sta: phase mismatch */ 168e85390dcSwdenk #define CMP 0x40 /* sta: arbitration complete */ 169e85390dcSwdenk #define SEL 0x20 /* sta: selected by another device */ 170e85390dcSwdenk #define RSL 0x10 /* sta: reselected by another device*/ 171e85390dcSwdenk #define SGE 0x08 /* sta: gross error (over/underflow)*/ 172e85390dcSwdenk #define UDC 0x04 /* sta: unexpected disconnect */ 173e85390dcSwdenk #define RST 0x02 /* sta: scsi bus reset detected */ 174e85390dcSwdenk #define PAR 0x01 /* sta: scsi parity error */ 175e85390dcSwdenk 176e85390dcSwdenk #define SLPAR 0x44 177e85390dcSwdenk #define SWIDE 0x45 178e85390dcSwdenk #define MACNTL 0x46 179e85390dcSwdenk #define GPCNTL 0x47 180e85390dcSwdenk #define STIME0 0x48 /* cmd: timeout for select&handshake*/ 181e85390dcSwdenk #define STIME1 0x49 /* cmd: timeout user defined */ 182e85390dcSwdenk #define RESPID 0x4a /* sta: Reselect-IDs */ 183e85390dcSwdenk 184e85390dcSwdenk #define STEST0 0x4c 185e85390dcSwdenk 186e85390dcSwdenk #define STEST1 0x4d 187e85390dcSwdenk #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 188e85390dcSwdenk #define DBLEN 0x08 /* clock doubler running */ 189e85390dcSwdenk #define DBLSEL 0x04 /* clock doubler selected */ 190e85390dcSwdenk 191e85390dcSwdenk 192e85390dcSwdenk #define STEST2 0x4e 193e85390dcSwdenk #define ROF 0x40 /* reset scsi offset (after gross error!) */ 194e85390dcSwdenk #define EXT 0x02 /* extended filtering */ 195e85390dcSwdenk 196e85390dcSwdenk #define STEST3 0x4f 197e85390dcSwdenk #define TE 0x80 /* c: tolerAnt enable */ 198e85390dcSwdenk #define HSC 0x20 /* c: Halt SCSI Clock */ 199e85390dcSwdenk #define CSF 0x02 /* c: clear scsi fifo */ 200e85390dcSwdenk 201e85390dcSwdenk #define SIDL 0x50 /* Lowlevel: latched from scsi data */ 202e85390dcSwdenk #define STEST4 0x52 203e85390dcSwdenk #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 204e85390dcSwdenk #define SMODE_HVD 0x40 /* High Voltage Differential */ 205e85390dcSwdenk #define SMODE_SE 0x80 /* Single Ended */ 206e85390dcSwdenk #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 207e85390dcSwdenk #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 208e85390dcSwdenk /* bits 0-5 rsvd for C1010 */ 209e85390dcSwdenk 210e85390dcSwdenk #define SODL 0x54 /* Lowlevel: data out to scsi data */ 211e85390dcSwdenk 212e85390dcSwdenk #define SBDL 0x58 /* Lowlevel: data from scsi data */ 213e85390dcSwdenk 214e85390dcSwdenk 215e85390dcSwdenk /*----------------------------------------------------------- 216e85390dcSwdenk ** 217e85390dcSwdenk ** Utility macros for the script. 218e85390dcSwdenk ** 219e85390dcSwdenk **----------------------------------------------------------- 220e85390dcSwdenk */ 221e85390dcSwdenk 222e85390dcSwdenk #define REG(r) (r) 223e85390dcSwdenk 224e85390dcSwdenk /*----------------------------------------------------------- 225e85390dcSwdenk ** 226e85390dcSwdenk ** SCSI phases 227e85390dcSwdenk ** 228e85390dcSwdenk ** DT phases illegal for ncr driver. 229e85390dcSwdenk ** 230e85390dcSwdenk **----------------------------------------------------------- 231e85390dcSwdenk */ 232e85390dcSwdenk 233e85390dcSwdenk #define SCR_DATA_OUT 0x00000000 234e85390dcSwdenk #define SCR_DATA_IN 0x01000000 235e85390dcSwdenk #define SCR_COMMAND 0x02000000 236e85390dcSwdenk #define SCR_STATUS 0x03000000 237e85390dcSwdenk #define SCR_DT_DATA_OUT 0x04000000 238e85390dcSwdenk #define SCR_DT_DATA_IN 0x05000000 239e85390dcSwdenk #define SCR_MSG_OUT 0x06000000 240e85390dcSwdenk #define SCR_MSG_IN 0x07000000 241e85390dcSwdenk 242e85390dcSwdenk #define SCR_ILG_OUT 0x04000000 243e85390dcSwdenk #define SCR_ILG_IN 0x05000000 244e85390dcSwdenk 245e85390dcSwdenk /*----------------------------------------------------------- 246e85390dcSwdenk ** 247e85390dcSwdenk ** Data transfer via SCSI. 248e85390dcSwdenk ** 249e85390dcSwdenk **----------------------------------------------------------- 250e85390dcSwdenk ** 251e85390dcSwdenk ** MOVE_ABS (LEN) 252e85390dcSwdenk ** <<start address>> 253e85390dcSwdenk ** 254e85390dcSwdenk ** MOVE_IND (LEN) 255e85390dcSwdenk ** <<dnad_offset>> 256e85390dcSwdenk ** 257e85390dcSwdenk ** MOVE_TBL 258e85390dcSwdenk ** <<dnad_offset>> 259e85390dcSwdenk ** 260e85390dcSwdenk **----------------------------------------------------------- 261e85390dcSwdenk */ 262e85390dcSwdenk 263e85390dcSwdenk #define OPC_MOVE 0x08000000 264e85390dcSwdenk 265e85390dcSwdenk #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 266e85390dcSwdenk #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 267e85390dcSwdenk #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 268e85390dcSwdenk 269e85390dcSwdenk #define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 270e85390dcSwdenk #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 271e85390dcSwdenk #define SCR_CHMOV_TBL (0x10000000) 272e85390dcSwdenk 273e85390dcSwdenk 274e85390dcSwdenk /*----------------------------------------------------------- 275e85390dcSwdenk ** 276e85390dcSwdenk ** Selection 277e85390dcSwdenk ** 278e85390dcSwdenk **----------------------------------------------------------- 279e85390dcSwdenk ** 280e85390dcSwdenk ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 281e85390dcSwdenk ** <<alternate_address>> 282e85390dcSwdenk ** 283e85390dcSwdenk ** SEL_TBL | << dnad_offset>> [ | REL_JMP] 284e85390dcSwdenk ** <<alternate_address>> 285e85390dcSwdenk ** 286e85390dcSwdenk **----------------------------------------------------------- 287e85390dcSwdenk */ 288e85390dcSwdenk 289e85390dcSwdenk #define SCR_SEL_ABS 0x40000000 290e85390dcSwdenk #define SCR_SEL_ABS_ATN 0x41000000 291e85390dcSwdenk #define SCR_SEL_TBL 0x42000000 292e85390dcSwdenk #define SCR_SEL_TBL_ATN 0x43000000 293e85390dcSwdenk 294e85390dcSwdenk 295e85390dcSwdenk #define SCR_JMP_REL 0x04000000 296e85390dcSwdenk #define SCR_ID(id) (((unsigned long)(id)) << 16) 297e85390dcSwdenk 298e85390dcSwdenk /*----------------------------------------------------------- 299e85390dcSwdenk ** 300e85390dcSwdenk ** Waiting for Disconnect or Reselect 301e85390dcSwdenk ** 302e85390dcSwdenk **----------------------------------------------------------- 303e85390dcSwdenk ** 304e85390dcSwdenk ** WAIT_DISC 305e85390dcSwdenk ** dummy: <<alternate_address>> 306e85390dcSwdenk ** 307e85390dcSwdenk ** WAIT_RESEL 308e85390dcSwdenk ** <<alternate_address>> 309e85390dcSwdenk ** 310e85390dcSwdenk **----------------------------------------------------------- 311e85390dcSwdenk */ 312e85390dcSwdenk 313e85390dcSwdenk #define SCR_WAIT_DISC 0x48000000 314e85390dcSwdenk #define SCR_WAIT_RESEL 0x50000000 315e85390dcSwdenk 316e85390dcSwdenk /*----------------------------------------------------------- 317e85390dcSwdenk ** 318e85390dcSwdenk ** Bit Set / Reset 319e85390dcSwdenk ** 320e85390dcSwdenk **----------------------------------------------------------- 321e85390dcSwdenk ** 322e85390dcSwdenk ** SET (flags {|.. }) 323e85390dcSwdenk ** 324e85390dcSwdenk ** CLR (flags {|.. }) 325e85390dcSwdenk ** 326e85390dcSwdenk **----------------------------------------------------------- 327e85390dcSwdenk */ 328e85390dcSwdenk 329e85390dcSwdenk #define SCR_SET(f) (0x58000000 | (f)) 330e85390dcSwdenk #define SCR_CLR(f) (0x60000000 | (f)) 331e85390dcSwdenk 332e85390dcSwdenk #define SCR_CARRY 0x00000400 333e85390dcSwdenk #define SCR_TRG 0x00000200 334e85390dcSwdenk #define SCR_ACK 0x00000040 335e85390dcSwdenk #define SCR_ATN 0x00000008 336e85390dcSwdenk 337e85390dcSwdenk 338e85390dcSwdenk /*----------------------------------------------------------- 339e85390dcSwdenk ** 340e85390dcSwdenk ** Memory to memory move 341e85390dcSwdenk ** 342e85390dcSwdenk **----------------------------------------------------------- 343e85390dcSwdenk ** 344e85390dcSwdenk ** COPY (bytecount) 345e85390dcSwdenk ** << source_address >> 346e85390dcSwdenk ** << destination_address >> 347e85390dcSwdenk ** 348e85390dcSwdenk ** SCR_COPY sets the NO FLUSH option by default. 349e85390dcSwdenk ** SCR_COPY_F does not set this option. 350e85390dcSwdenk ** 351e85390dcSwdenk ** For chips which do not support this option, 352e85390dcSwdenk ** ncr_copy_and_bind() will remove this bit. 353e85390dcSwdenk **----------------------------------------------------------- 354e85390dcSwdenk */ 355e85390dcSwdenk 356e85390dcSwdenk #define SCR_NO_FLUSH 0x01000000 357e85390dcSwdenk 358e85390dcSwdenk #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 359e85390dcSwdenk #define SCR_COPY_F(n) (0xc0000000 | (n)) 360e85390dcSwdenk 361e85390dcSwdenk /*----------------------------------------------------------- 362e85390dcSwdenk ** 363e85390dcSwdenk ** Register move and binary operations 364e85390dcSwdenk ** 365e85390dcSwdenk **----------------------------------------------------------- 366e85390dcSwdenk ** 367e85390dcSwdenk ** SFBR_REG (reg, op, data) reg = SFBR op data 368e85390dcSwdenk ** << 0 >> 369e85390dcSwdenk ** 370e85390dcSwdenk ** REG_SFBR (reg, op, data) SFBR = reg op data 371e85390dcSwdenk ** << 0 >> 372e85390dcSwdenk ** 373e85390dcSwdenk ** REG_REG (reg, op, data) reg = reg op data 374e85390dcSwdenk ** << 0 >> 375e85390dcSwdenk ** 376e85390dcSwdenk **----------------------------------------------------------- 377e85390dcSwdenk ** On 810A, 860, 825A, 875, 895 and 896 chips the content 378e85390dcSwdenk ** of SFBR register can be used as data (SCR_SFBR_DATA). 379e85390dcSwdenk ** The 896 has additionnal IO registers starting at 380e85390dcSwdenk ** offset 0x80. Bit 7 of register offset is stored in 381e85390dcSwdenk ** bit 7 of the SCRIPTS instruction first DWORD. 382e85390dcSwdenk **----------------------------------------------------------- 383e85390dcSwdenk */ 384e85390dcSwdenk 385e85390dcSwdenk #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ 386e85390dcSwdenk 387e85390dcSwdenk #define SCR_SFBR_REG(reg,op,data) \ 388e85390dcSwdenk (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 389e85390dcSwdenk 390e85390dcSwdenk #define SCR_REG_SFBR(reg,op,data) \ 391e85390dcSwdenk (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 392e85390dcSwdenk 393e85390dcSwdenk #define SCR_REG_REG(reg,op,data) \ 394e85390dcSwdenk (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 395e85390dcSwdenk 396e85390dcSwdenk 397e85390dcSwdenk #define SCR_LOAD 0x00000000 398e85390dcSwdenk #define SCR_SHL 0x01000000 399e85390dcSwdenk #define SCR_OR 0x02000000 400e85390dcSwdenk #define SCR_XOR 0x03000000 401e85390dcSwdenk #define SCR_AND 0x04000000 402e85390dcSwdenk #define SCR_SHR 0x05000000 403e85390dcSwdenk #define SCR_ADD 0x06000000 404e85390dcSwdenk #define SCR_ADDC 0x07000000 405e85390dcSwdenk 406e85390dcSwdenk #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 407e85390dcSwdenk 408e85390dcSwdenk /*----------------------------------------------------------- 409e85390dcSwdenk ** 410e85390dcSwdenk ** FROM_REG (reg) SFBR = reg 411e85390dcSwdenk ** << 0 >> 412e85390dcSwdenk ** 413e85390dcSwdenk ** TO_REG (reg) reg = SFBR 414e85390dcSwdenk ** << 0 >> 415e85390dcSwdenk ** 416e85390dcSwdenk ** LOAD_REG (reg, data) reg = <data> 417e85390dcSwdenk ** << 0 >> 418e85390dcSwdenk ** 419e85390dcSwdenk ** LOAD_SFBR(data) SFBR = <data> 420e85390dcSwdenk ** << 0 >> 421e85390dcSwdenk ** 422e85390dcSwdenk **----------------------------------------------------------- 423e85390dcSwdenk */ 424e85390dcSwdenk 425e85390dcSwdenk #define SCR_FROM_REG(reg) \ 426e85390dcSwdenk SCR_REG_SFBR(reg,SCR_OR,0) 427e85390dcSwdenk 428e85390dcSwdenk #define SCR_TO_REG(reg) \ 429e85390dcSwdenk SCR_SFBR_REG(reg,SCR_OR,0) 430e85390dcSwdenk 431e85390dcSwdenk #define SCR_LOAD_REG(reg,data) \ 432e85390dcSwdenk SCR_REG_REG(reg,SCR_LOAD,data) 433e85390dcSwdenk 434e85390dcSwdenk #define SCR_LOAD_SFBR(data) \ 435e85390dcSwdenk (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 436e85390dcSwdenk 437e85390dcSwdenk /*----------------------------------------------------------- 438e85390dcSwdenk ** 439e85390dcSwdenk ** LOAD from memory to register. 440e85390dcSwdenk ** STORE from register to memory. 441e85390dcSwdenk ** 442e85390dcSwdenk ** Only supported by 810A, 860, 825A, 875, 895 and 896. 443e85390dcSwdenk ** 444e85390dcSwdenk **----------------------------------------------------------- 445e85390dcSwdenk ** 446e85390dcSwdenk ** LOAD_ABS (LEN) 447e85390dcSwdenk ** <<start address>> 448e85390dcSwdenk ** 449e85390dcSwdenk ** LOAD_REL (LEN) (DSA relative) 450e85390dcSwdenk ** <<dsa_offset>> 451e85390dcSwdenk ** 452e85390dcSwdenk **----------------------------------------------------------- 453e85390dcSwdenk */ 454e85390dcSwdenk 455e85390dcSwdenk #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 456e85390dcSwdenk #define SCR_NO_FLUSH2 0x02000000 457e85390dcSwdenk #define SCR_DSA_REL2 0x10000000 458e85390dcSwdenk 459e85390dcSwdenk #define SCR_LOAD_R(reg, how, n) \ 460e85390dcSwdenk (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 461e85390dcSwdenk 462e85390dcSwdenk #define SCR_STORE_R(reg, how, n) \ 463e85390dcSwdenk (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 464e85390dcSwdenk 465e85390dcSwdenk #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 466e85390dcSwdenk #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 467e85390dcSwdenk #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 468e85390dcSwdenk #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 469e85390dcSwdenk 470e85390dcSwdenk #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 471e85390dcSwdenk #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 472e85390dcSwdenk #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 473e85390dcSwdenk #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 474e85390dcSwdenk 475e85390dcSwdenk 476e85390dcSwdenk /*----------------------------------------------------------- 477e85390dcSwdenk ** 478e85390dcSwdenk ** Waiting for Disconnect or Reselect 479e85390dcSwdenk ** 480e85390dcSwdenk **----------------------------------------------------------- 481e85390dcSwdenk ** 482e85390dcSwdenk ** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 483e85390dcSwdenk ** <<address>> 484e85390dcSwdenk ** 485e85390dcSwdenk ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 486e85390dcSwdenk ** <<distance>> 487e85390dcSwdenk ** 488e85390dcSwdenk ** CALL [ | IFTRUE/IFFALSE ( ... ) ] 489e85390dcSwdenk ** <<address>> 490e85390dcSwdenk ** 491e85390dcSwdenk ** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 492e85390dcSwdenk ** <<distance>> 493e85390dcSwdenk ** 494e85390dcSwdenk ** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 495e85390dcSwdenk ** <<dummy>> 496e85390dcSwdenk ** 497e85390dcSwdenk ** INT [ | IFTRUE/IFFALSE ( ... ) ] 498e85390dcSwdenk ** <<ident>> 499e85390dcSwdenk ** 500e85390dcSwdenk ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 501e85390dcSwdenk ** <<ident>> 502e85390dcSwdenk ** 503e85390dcSwdenk ** Conditions: 504e85390dcSwdenk ** WHEN (phase) 505e85390dcSwdenk ** IF (phase) 506e85390dcSwdenk ** CARRYSET 507e85390dcSwdenk ** DATA (data, mask) 508e85390dcSwdenk ** 509e85390dcSwdenk **----------------------------------------------------------- 510e85390dcSwdenk */ 511e85390dcSwdenk 512e85390dcSwdenk #define SCR_NO_OP 0x80000000 513e85390dcSwdenk #define SCR_JUMP 0x80080000 514e85390dcSwdenk #define SCR_JUMP64 0x80480000 515e85390dcSwdenk #define SCR_JUMPR 0x80880000 516e85390dcSwdenk #define SCR_CALL 0x88080000 517e85390dcSwdenk #define SCR_CALLR 0x88880000 518e85390dcSwdenk #define SCR_RETURN 0x90080000 519e85390dcSwdenk #define SCR_INT 0x98080000 520e85390dcSwdenk #define SCR_INT_FLY 0x98180000 521e85390dcSwdenk 522e85390dcSwdenk #define IFFALSE(arg) (0x00080000 | (arg)) 523e85390dcSwdenk #define IFTRUE(arg) (0x00000000 | (arg)) 524e85390dcSwdenk 525e85390dcSwdenk #define WHEN(phase) (0x00030000 | (phase)) 526e85390dcSwdenk #define IF(phase) (0x00020000 | (phase)) 527e85390dcSwdenk 528e85390dcSwdenk #define DATA(D) (0x00040000 | ((D) & 0xff)) 529e85390dcSwdenk #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 530e85390dcSwdenk 531e85390dcSwdenk #define CARRYSET (0x00200000) 532e85390dcSwdenk 533e85390dcSwdenk 534e85390dcSwdenk #define SIR_COMPLETE 0x10000000 535e85390dcSwdenk /* script errors */ 536e85390dcSwdenk #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 537e85390dcSwdenk #define SIR_CMD_OUT_ILL_PH 0x00000002 538e85390dcSwdenk #define SIR_STATUS_ILL_PH 0x00000003 539e85390dcSwdenk #define SIR_MSG_RECEIVED 0x00000004 540e85390dcSwdenk #define SIR_DATA_IN_ERR 0x00000005 541e85390dcSwdenk #define SIR_DATA_OUT_ERR 0x00000006 542e85390dcSwdenk #define SIR_SCRIPT_ERROR 0x00000007 543e85390dcSwdenk #define SIR_MSG_OUT_NO_CMD 0x00000008 544e85390dcSwdenk #define SIR_MSG_OVER7 0x00000009 545e85390dcSwdenk /* Fly interrupt */ 546e85390dcSwdenk #define INT_ON_FY 0x00000080 547e85390dcSwdenk 548e85390dcSwdenk /* Hardware errors are defined in scsi.h */ 549e85390dcSwdenk 550e85390dcSwdenk #define SCSI_IDENTIFY 0xC0 551e85390dcSwdenk 552e85390dcSwdenk #endif 553