Lines Matching +full:0 +full:xe1000000
28 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
41 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
42 #define CONFIG_SYS_MEMTEST_END 0x00400000
44 #define CONFIG_SYS_CCSRBAR 0xe0000000
52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
62 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
74 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
76 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
78 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
80 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
81 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
85 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
86 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
90 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
91 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
92 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
99 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
101 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
103 #define CONFIG_SYS_BR0_PRELIM 0xff801001
104 #define CONFIG_SYS_BR1_PRELIM 0xfe801001
106 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
107 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
123 #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
125 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
126 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
128 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
129 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
132 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
133 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
134 #define PIXIS_VER 0x1 /* Board version at offset 1 */
135 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
136 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
137 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
139 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
140 #define PIXIS_VCTL 0x10 /* VELA Control Register */
141 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
142 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
143 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
144 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
145 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
146 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
147 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
148 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
149 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
150 #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
151 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
152 #define PIXIS_VSPEED2_TSEC1SER 0x2
153 #define PIXIS_VSPEED2_TSEC3SER 0x1
154 #define PIXIS_VCFGEN1_TSEC1SER 0x20
155 #define PIXIS_VCFGEN1_TSEC3SER 0x40
160 #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
161 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
175 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
180 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
181 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
187 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
188 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
189 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
194 * Memory space is mapped 1-1, but I/O space must start from 0.
196 #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
197 #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
198 #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
199 #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
201 #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
202 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
203 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
204 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
205 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
206 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
207 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
208 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
212 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
213 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
214 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
215 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
216 #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
217 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
218 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
219 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
223 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
224 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
225 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
226 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
227 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
228 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
229 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
230 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
234 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
235 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
236 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
237 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
238 #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
239 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
240 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
241 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
242 #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
243 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
244 #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
245 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
270 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
294 #define SGMII_RISER_PHY_OFFSET 0x1c
296 #define TSEC1_PHY_ADDR 0
302 #define TSEC1_PHYIDX 0
303 #define TSEC3_PHYIDX 0
311 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
312 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
313 #define CONFIG_ENV_ADDR 0xfff80000
317 #define CONFIG_ENV_SIZE 0x2000
333 #define CONFIG_PCI_EHCI_DEVICE 0
341 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
379 "netdev=eth0\0" \
380 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
391 " $filesize\0" \
392 "consoledev=ttyS0\0" \
393 "ramdiskaddr=2000000\0" \
394 "ramdiskfile=8544ds/ramdisk.uboot\0" \
395 "fdtaddr=1e00000\0" \
396 "fdtfile=8544ds/mpc8544ds.dtb\0" \
397 "bdev=sda3\0"